CN116318511A - Method and device for determining sending timestamp - Google Patents

Abstract

The method and the device for determining the sending time stamp are used for solving the problem of path delay jitter caused by sending time stamp jitter due to unfixed number of logical lane where the sending time stamp is located, effectively inhibiting the sending time stamp jitter and the path delay jitter, and being not limited by the number of channels, the method is suitable for a scene where a plurality of sending time stamp stamping points are unfixed.

Description

Method and device for determining sending timestamp

Technical Field

The present disclosure relates to the field of optical communication network time synchronization technologies, and in particular, to a method and an apparatus for determining a transmission timestamp.

Background

As shown in fig. 1, the interface of the optical channel transmission unit OTU4 has 20 logical channels (logical lanes), and has a parallel interface (hereinafter referred to as serial deserializing parallel interface) in which a plurality of physical channels (physical lanes) communicate with the serial deserializer SerDes. Lane fifo refers to a SerDes channel buffer, namely a serial deserializing channel buffer, an inlet of Lane fifo is a system clock domain, an outlet of Lane fifo is a SerDes clock domain, and Lane fifo converts data of the system clock domain into the SerDes clock domain. The frame header indication FP is cyclically presented on 20 logical lanes in the manner of a round-robin schedule, one multiframe is formed every 256 frames in the OTU4, the multiframe indicates that the MFP will also be presented on a different logical lane, and the transmission time stamp of the OTU4 is stamped at the first bit position of the MFP.

In the related art, the OTU4 is operated so that the MFP, which is the position of the transmission time stamp in the transmission direction, is carried close to the serial-deserialized parallel interface. When analyzing path delay, from single channel analysis, when stamping point is in SerDes clock domain, buffer lane fifo of clock domain has been passed, so that the level fifo waterline and the processing delay of preceding-stage circuit have no influence on path delay. However, when a scenario in which the logical lane number where the transmission time stamp point on the MFP is located is not fixed is involved, delay deviation among a plurality of logical lanes may cause jitter in the transmission time stamp, thereby affecting path delay. Assuming that multiple logical lanes are sent in perfect alignment, in an actual circuit, multiple physical lanes correspond to different SerDes, the SerDes phases cannot be identical completely, and there is a cross-clock domain processing at the SerDes, so there is some delay skew between the multiple physical lanes. The protocol defines the logic lane with the longest received delay, namely the latest logic lane, as a reference lane. The receiving direction subtracts the MFP sending timestamp carried in the PTP message from the receiving timestamp of the MFP position on the latest logical lane as a path delay. The MFP in the transmission direction appears in different logical lanes, which causes that the logical lanes corresponding to the transmission time stamp are not fixed, so that delay deviation between multiple logical lanes in the transmission direction may aggravate path delay jitter.

Along with the development of 5G and the continuous evolution of network technology, the clock synchronization precision requirement reaches nanosecond level, and higher requirements are also provided for jitter of a transmission time stamp, so that how to reduce the jitter of the transmission time stamp and thus reduce the path delay jitter is a technical problem to be solved.

Disclosure of Invention

The main purpose of the present application is to provide a method and apparatus for determining suppression of transmission timestamp jitter, which aims to solve the technical problem of path delay jitter caused by transmission timestamp jitter when optical channel transmission units transmit timestamps on different logic lanes.

In a first aspect, the present application provides a method for determining a transmission timestamp, the method including the steps of:

performing alignment adjustment on all serial deserialized channel buffer cache in the optical channel transmission unit;

setting a virtual frame header VFP for indicating the time sequence position of the frame header FP on a preset logic channel of the optical channel transmission unit;

a transmit timestamp for determining the path delay is generated based on the timestamp of the VFP arrival at the serial deserialization parallel interface.

In some embodiments, the aligning all serial de-serialized channel buffers lane fifo in the optical channel transmission unit includes:

generating a timing pulse based on a system clock of the optical channel transmission unit;

locking the waterline value of each lane fifo at the timing pulse;

determining whether a waterline difference value between a maximum lane fifo waterline value and a minimum lane fifo waterline value is greater than a preset first threshold value;

if yes, resetting all the Lane fifo at the same time to align and adjust all the Lane fifo, otherwise, not resetting each Lane fifo.

In some embodiments, resetting all the lane fifo at the same time to align all the lane fifo includes:

clearing all the Lane fifo and controlling the read function preparation signals of all the Lane fifo to be set to a low level;

when the real-time waterline value of each lane fifo reaches a preset second threshold value, the read function preparation signal of the corresponding lane fifo is controlled to be set to a high level so as to respond to the corresponding read request.

In some embodiments, before determining whether the difference between the maximum and minimum lane fifo watermark values is greater than a preset first threshold value, further comprising,

sequencing the waterline values of the Lane fifo locked at the timing pulse by an bubbling sequencing method;

wherein the period of the timing pulse is greater than or equal to the number of beats required to order the watermark values of the respective lane fifo.

In some embodiments, setting a virtual frame header VFP for indicating a frame header FP timing position on a predetermined logic channel of the optical channel transmission unit includes:

selecting one logic channel of the optical channel transmission unit as the preset logic channel;

when the FP appears on any logic channel of the optical channel transmission unit, generating the VFP at the position which is the same as the FP time sequence position on the preset logic channel;

wherein the VFP is a sideband signal.

In some embodiments, the generating a transmission timestamp for determining the path delay based on the timestamp of the VFP arriving at the serial-deserialized parallel interface includes:

and generating a sending time stamp for determining path delay according to the time stamp of the VFP reaching the serial deserializing parallel interface and the offset of the VFP in one beat of data after the data bit width conversion.

In some embodiments, the generating a transmission timestamp for determining a path delay according to the timestamp of the VFP reaching the serial deserializing parallel interface and the offset of the VFP in one beat of data after the data bit width conversion includes:

determining a sending time compensation value according to the offset of the VFP in one beat of data after the data bit width conversion and the transmission rate of the optical channel transmission unit;

compensating the time stamp of the VFP reaching the serial deserializing parallel interface according to the transmission time compensation value;

and taking the compensated VFP timestamp as a multiframe for determining path delay to instruct the MFP to send the timestamp, and loading the timestamp into the PTP message.

In some embodiments, before generating the transmission time stamp for determining the path delay according to the offset of the VFP in one beat of data after the VFP arrives at the serial deserialization parallel interface and the data bit width conversion, the method further comprises:

when any lane fifo detects that a multi-frame indicates an MFP, after delaying for a preset time, acquiring the offset of the VFP in one beat of data and the time stamp of the VFP reaching a serial deserializing and parallel interface after data bit width conversion;

the preset time is greater than the time required for transmitting the data quantity corresponding to the first threshold value.

In some embodiments, the method further comprises:

and setting the time stamp of the next VFP reaching the serial deserializing and parallel interface to cover the time stamp of the next VFP reaching the serial deserializing and parallel interface.

In a second aspect, the present application further provides a device for determining a sending timestamp, where the device includes:

the alignment module is used for carrying out alignment adjustment on all serial deserialized channel buffers lane fifo in the optical channel transmission unit;

a setting module, configured to set a virtual frame header VFP for indicating a frame header FP timing position on a predetermined logic channel of the optical channel transmission unit;

and the generating module is used for generating a sending time stamp for determining the path delay based on the time stamp of the VFP reaching the serial deserializing parallel interface.

In some embodiments, the alignment module is further to:

generating a timing pulse based on a system clock of the optical channel transmission unit;

locking the waterline value of each lane fifo at the timing pulse;

determining whether a waterline difference value between a maximum lane fifo waterline value and a minimum lane fifo waterline value is greater than a preset first threshold value;

if yes, resetting all the Lane fifo at the same time to align and adjust all the Lane fifo, otherwise, not resetting each Lane fifo.

In some embodiments, the alignment module is further to:

clearing all the Lane fifo and controlling the read function preparation signals of all the Lane fifo to be set to a low level;

when the real-time waterline value of each lane fifo reaches a preset second threshold value, the read function preparation signal of the corresponding lane fifo is controlled to be set to a high level so as to respond to the corresponding read request.

In some embodiments, the alignment module is further to:

sequencing the waterline values of the Lane fifo locked at the timing pulse by an bubbling sequencing method;

wherein the period of the timing pulse is greater than or equal to the number of beats required to order the watermark values of the respective lane fifo.

In some embodiments, the setting module is further configured to:

selecting one logic channel of the optical channel transmission unit as the preset logic channel;

when the FP appears on any logic channel of the optical channel transmission unit, generating the VFP at the position which is the same as the FP time sequence position on the preset logic channel;

wherein the VFP is a sideband signal.

In some embodiments, the generating module is further configured to:

and generating a sending time stamp for determining path delay according to the time stamp of the VFP reaching the serial deserializing parallel interface and the offset of the VFP in one beat of data after the data bit width conversion.

In some embodiments, the generating module is further configured to:

determining a sending time compensation value according to the offset of the VFP in one beat of data after the data bit width conversion and the transmission rate of the optical channel transmission unit;

compensating the time stamp of the VFP reaching the serial deserializing parallel interface according to the transmission time compensation value;

and taking the compensated VFP timestamp as a multiframe for determining path delay to instruct the MFP to send the timestamp, and loading the timestamp into the PTP message.

In some embodiments, the generating module is further configured to:

when any lane fifo detects that a multi-frame indicates an MFP, after delaying for a preset time, acquiring the offset of the VFP in one beat of data and the time stamp of the VFP reaching a serial deserializing and parallel interface after data bit width conversion;

the preset time is greater than the time required for transmitting the data quantity corresponding to the first threshold value.

In some embodiments, the apparatus is further to:

and setting the time stamp of the next VFP reaching the serial deserializing and parallel interface to cover the time stamp of the next VFP reaching the serial deserializing and parallel interface.

The utility model provides a method and a device for determining a sending time stamp, which are used for adjusting the alignment of all serial deserializing channel buffer Lane fifo in an optical channel transmission unit so as to reduce time delay deviation caused by inconsistent water line values of different Lane fifo, setting a virtual frame head VFP for indicating the time sequence position of a frame head FP on a preset logic channel of the optical channel transmission unit, generating the sending time stamp for determining the path time delay based on the time stamp of the VFP reaching a serial deserializing parallel interface, realizing the fixation of the sending time stamp on a single logic Lane, solving the problem of path time delay jitter caused by the sending time stamp jitter caused by the unfixed logic Lane number of the sending time stamp, effectively inhibiting the sending time stamp jitter and the path time delay jitter, and being not limited by the quantity of channels, and being suitable for the scene of unfixed channels where a plurality of sending time stamp stamping points are located.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of the structure of an OTU4 unit;

fig. 2 is a flowchart of a method for determining a transmission timestamp according to an embodiment of the present application;

FIG. 3 is a logical schematic diagram of a lane fifo waterline consistency comparison and alignment method;

FIG. 4 is a flowchart illustrating a method for determining a transmission time stamp;

fig. 5 is a schematic diagram of the timing positional relationship of the MFP and the corresponding VFP.

Fig. 6 is a schematic block diagram of a configuration of a device for determining a transmission timestamp according to an embodiment of the present application;

the realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The flow diagrams depicted in the figures are merely illustrative and not necessarily all of the elements and operations/steps are included or performed in the order described. For example, some operations/steps may be further divided, combined, or partially combined, so that the order of actual execution may be changed according to actual situations.

The embodiment of the application provides a method and a device for determining a sending timestamp, and the method can be applied to computer equipment.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.

It should be noted that, the method for determining the transmission timestamp in the present application may be applicable to a scenario where the logic lane where the transmission timestamp of the MFP is located is not fixed, for example, may be applied to an optical channel transmission unit such as OUT4 or OTU5 (U). The embodiments of the present application will be described in terms of the implementation of this method in OTU 4.

It should be understood that the OTU4 transmitting side, after distributing the plurality of logical lanes, becomes OTL4.4 or OTL4.10.OTL4.4 has 4 physical lanes and OTL4.10 has 10 physical lanes, this example is illustrated with OTL 4.4. As shown in fig. 1, there are multiple lanes of fifo in parallel at the serial deserialization and parallel interface, the fifo write side is the system clock domain clk_sys, 4 logical lanes of writing and measuring are aligned, the read side is the SerDes clock domain, 4 physical lanes of the read side are homologous but have instantaneous phase deviation, so that the waterline of the 4 lanes fifo is not completely consistent, the OTU4 multiframe indicates that the MFP has deviation in time delay sent from different lanes fifo, thus the multiframe indicates that the transmission timestamp of the MFP has jitter, and further the path delay jitter occurs.

Referring to fig. 2, fig. 2 is a flowchart of a method for determining a transmission timestamp according to an embodiment of the present application.

As shown in fig. 2, the method includes steps S1 to S3.

Step S1, performing alignment adjustment on all serial de-serial channel buffers lane fifo in the optical channel transmission unit.

Specifically, the aligning adjustment of all serial deserialized channel buffers lane fifo in the optical channel transmission unit includes: generating a timing pulse based on a system clock of the optical channel transmission unit; locking the waterline value of each lane fifo at the timing pulse; determining whether a waterline difference value between a maximum lane fifo waterline value and a minimum lane fifo waterline value is greater than a preset first threshold value; if yes, resetting all the Lane fifo at the same time to align and adjust all the Lane fifo, otherwise, not resetting each Lane fifo.

Illustratively, as shown in fig. 3, the timing pulse chk_point is generated based on the system clock clk_sys of the OTU4, and the waterline values of all the lane fifo are locked at the same timing pulse chk_point, and the OTL4.4 of the present embodiment has 4 lane fifo, and thus the waterline values of the 4 lane fifo are locked. And then sorting the waterline values of the 4 Lane fifo, finding out the maximum Lane fifo waterline value Wmax and the minimum Lane fifo waterline value Wmin, and determining whether the consistency of all Lane fifo is qualified according to whether the difference between the maximum Lane fifo waterline value Wmax and the minimum Lane fifo waterline value Wmin is larger than a preset first threshold Wt value. If the waterline difference value is larger than a preset first threshold value Wt, the fact that the consistency of each lane fifo is poor can lead to large deviation of transmission delay, and alignment processing is needed; if the waterline difference value is smaller than or equal to a preset first threshold value Wt, the fact that each lane fifo has good consistency is indicated, and processing is not needed.

It should be noted that, the write enable alignment of the lane fifo, the read enable thereof is derived from the SerDes clock, the configuration of the first threshold Wt needs to consider the clock synchronization state of the SerDes between the multiple physical lanes on the read side, if the local clock is the local clock, the first threshold Wt is configured as a smaller value, and if the local clock is the clock recovered by the phase-locked loop, the first threshold Wt is configured as a larger value. And the first threshold can be configured as a range according to the fluctuation range of the lane fifo waterline deviation, so that the consistency protection is not frequently triggered when the lane fifo works normally.

Further, resetting all the lane fifo at the same time to adjust the alignment of all the lane fifo includes the following steps: all the lane fifo is cleared, and the read function preparation signal for controlling all the lane fifo is set to low level, and at this time, the lane fifo does not send data to the outside, but can write data. The same second threshold value Ws is set for each lane fifo, when the real-time waterline value Wr of each lane fifo reaches the preset second threshold value Ws, the read function preparation signal of the corresponding lane fifo is controlled to be set to be high level to respond to the corresponding read request, so that all lane fifos of the same OTU4 port are set with the same initial waterline, all lane fifo are simultaneously ready after being reset, and simultaneously read is started, and time delay deviation caused by inconsistent waterline values of different lane fifo can be effectively reduced. The deviation of the water line value of each lane fifo after consistency protection is small and is approximately about Ws.

Preferably, in this embodiment, the waterline values of the respective lane fifo locked at the same timing pulse are sorted by the bubble sorting method, so as to determine the order of magnitudes of the waterline values of the respective lane fifo. It will be appreciated that the watermark value of Lane fifo refers to the amount of data that Lane fifo currently stores, e.g., if Lane fifo stores 10 beats of data, the watermark value is 10. In this embodiment, the period duration of the timing pulse is also configured according to the speed of the lane fifo consistency detection, and the period of the timing pulse needs to be ensured to be greater than or equal to the number of beats required by the sorting process of the multiple lane fifo water lines, if the bubble sorting method is adopted, the period of the timing pulse is at least the number of clk_sys clock beats of the total entries of the physical lane.

In the actual circuit, all the local fifo write-side clocks are the same and are all system clocks, but the read-side clocks belong to the clock domains corresponding to the SerDes local and have certain phase deviation. Therefore, after the consistency check and correction of the lane fifo waterline, there is still a certain deviation from the lane fifo waterline, so further processing is required to reduce the deviation.

Step S2, setting a virtual frame head VFP for indicating the time sequence position of the frame head FP on a preset logic channel of the optical channel transmission unit.

Specifically, setting a virtual frame header VFP for indicating a frame header FP timing position on a predetermined logic channel of the optical channel transmission unit includes: selecting one logic channel of the optical channel transmission unit as the preset logic channel; when the FP appears on any logic channel of the optical channel transmission unit, generating the VFP at the position which is the same as the FP time sequence position on the preset logic channel; wherein the VFP is a sideband signal.

Exemplary, as shown in FIG. 4, a 20bit configuration cfg_en [19:0] is set to correspond to logical Lane#0-19, respectively, and if cfg_en [ i ] is set to 1, lane#i generates a virtual frame header VFP. Only one logical lane can be selected from 20 logical lanes as a predetermined logical lane, and a configuration of 20 bits is set in order to flexibly select any one lane as a reference lane. And setting a 1bit sideband signal, namely a virtual frame header VFP, by the selected lane#i, and generating a beat of virtual frame header pulse VFP at the same position on the preset logic lane as the FP time sequence position no matter whether the real FP falls on the preset logic lane or not in the rotation process of each OTU4 frame header when each OTU4 frame header carries out multi-lane distribution, wherein the VFP corresponds to the first bit position of the FP. Therefore, it can be understood that when the MFP is generated, there must be a corresponding VFP generated on the predetermined logic lane.

And step S3, generating a sending time stamp for determining the path delay based on the time stamp of the VFP reaching the serial deserializing parallel interface.

Specifically, generating a transmission timestamp for determining a path delay based on a timestamp of the VFP arriving at the serial deserialization parallel interface includes: and generating a sending time stamp for determining path delay according to the time stamp of the VFP reaching the serial deserializing parallel interface and the offset of the VFP in one beat of data after the data bit width conversion.

Further, generating a transmission time stamp for determining path delay according to the time stamp of the VFP reaching the serial deserializing parallel interface and the offset of the VFP in one beat of data after the data bit width conversion, including: determining a sending time compensation value according to the offset of the VFP in one beat of data after the data bit width conversion and the transmission rate of the optical channel transmission unit; compensating the time stamp of the VFP reaching the serial deserializing parallel interface according to the transmission time compensation value; and taking the compensated VFP timestamp as a multiframe for determining path delay to instruct the MFP to send the timestamp, and loading the timestamp into the PTP message.

It should be noted that, when the 20-way logic lane bit interleaving of the OTU4 is changed into OTL4.4 or OTL4.10, the VFP is brought into 4 or 10-way logic lane through or operation, and the VFP is used as a sideband signal and is transmitted to the SerDes clock domain at the serial deserializing and parallel interface along with the data stream through the processes of clock domain buffering, bit width conversion and the like. The bit position of the VFP within the current beat of data is indicated by an offset upon data bit width conversion. The offset here refers to the position of the VFP corresponding bit in one beat of data after the bit width conversion. For example, if the bit width of the serial deserializing parallel interface is 40 bits, the data needs to be converted into 40 bits per beat before being written into the lane fifo, the vfp may correspond to bit15, and the offset is 15.

Then, when each VFP reaches the serial deserializing and parallel interface, a timestamp Ts corresponding to the current moment is marked at the position indicated by the VFP, the timestamp Ts of the VFP reaching the serial deserializing and parallel interface is collected, and the timestamp of the next VFP reaching the serial deserializing and parallel interface covers the timestamp of the last VFP reaching the serial deserializing and parallel interface. And simultaneously latching the acquired Ts and the corresponding offset. After the timestamp Ts corresponding to the current time is marked at the position indicated by the VFP, signal demodulation can be performed to eliminate the 1bit sideband signal serving as the VFP.

In some embodiments, before generating the transmission time stamp for determining the path delay according to the offset of the VFP in one beat of data after the VFP arrives at the serial deserialization parallel interface and the data bit width conversion, the method further comprises: when any lane fifo detects that a multiframe indicates an MFP, the offset of the VFP in one beat of data and the time stamp of the VFP reaching a serial deserializing parallel interface are acquired after the data bit width conversion is delayed for a preset time. The preset time is greater than the time required for transmitting the data quantity corresponding to the first threshold value.

It should be understood that, as shown in fig. 5, since the frequency of occurrence of the MFP is lower than that of the VFP, in order to save the calculation amount, the MFP transmission time stamp may be calculated by delaying the preset time Td after detecting the MFP on the reading side of any lane fifo, and acquiring the VFP time stamp Ts acquired at the VFP and the corresponding offset. After consistency checking and correction of the lane fifo, the deviation between the lane fifo is ensured not to exceed a first threshold Wt of a waterline difference value, wherein the first threshold Wt is a plurality of SerDes clock beats and is far smaller than an OTU4 frame period. The delayed preset time Td is slightly larger than the time required for transmitting the data amount corresponding to the first threshold value Wt by a few beats, so that when the MFP arrives at the serial deserializing and parallel interface, the latched VFP timestamp is the timestamp of the VFP corresponding to the MFP, and is not the timestamp of the last VFP. Since the actually used time stamp is the time stamp value of the VFP position on the predetermined logic lane, the MFP position is deviated one by one and two beats, and the result is not affected, so that the MFP only needs to judge whether the current beat exists or not, and the bit offset position in the current beat is not needed to be recorded.

And calculating a transmission time stamp corresponding to the position of the MFP according to the Ts and the offset, determining a path time delay, and determining a transmission time compensation value according to the offset of the VFP in one beat of data after the data bit width conversion and the transmission rate of the optical channel transmission unit. The single lane rate of the OTL4.4 is 255/227×99.5328/4Gb/s, so that the time offset value corresponding to each UI (Unit Interval,1bit data transmission time) of the OTL4.4 is 1/(255/227×99.5328/4) ≡ 35.775 picoseconds. Thus, taking the offset of VFP as 15 as an example, a transmit time offset value of 15×35.775 picoseconds can be calculated. And compensating the time stamp of the VFP reaching the serial deserializing parallel interface according to the calculated transmission time compensation value, and obtaining the transmission time stamp corresponding to the position of the MFP. And loading the compensated VFP timestamp into a PTP message as an MFP sending timestamp, and then inserting the PTP message into OTN overhead. And subtracting the corresponding compensated VFP timestamp from the receiving timestamp of the MFP position to obtain the path delay.

In this embodiment, by performing alignment adjustment on all serial deserialized channel buffers lane fifo in an optical channel transmission unit to reduce delay deviation caused by inconsistent water line values of different lane fifo, and setting a virtual frame header VFP for indicating a time sequence position of a frame header FP on a predetermined logic channel of the optical channel transmission unit, generating a transmission timestamp for determining a path delay based on a timestamp of the VFP reaching the serial deserialized parallel interface, fixing the transmission timestamp onto a single logic lane is achieved, solving the problem of path delay jitter caused by transmission timestamp jitter due to unfixed number of the logic lane where the transmission timestamp is located, effectively inhibiting the transmission timestamp jitter and the path delay jitter, and the method is not limited by the number of channels, and is suitable for a scenario where the channels where the stamping points of multiple transmission timestamps are unfixed.

Referring to fig. 6, fig. 6 is a schematic block diagram of a device for determining a transmission timestamp according to an embodiment of the present application.

As shown in fig. 6, the apparatus includes:

the alignment module is used for carrying out alignment adjustment on all serial deserialized channel buffers lane fifo in the optical channel transmission unit;

a setting module, configured to set a virtual frame header VFP for indicating a frame header FP timing position on a predetermined logic channel of the optical channel transmission unit;

and the generating module is used for generating a sending time stamp for determining the path delay based on the time stamp of the VFP reaching the serial deserializing parallel interface.

Wherein the alignment module is further configured to:

generating a timing pulse based on a system clock of the optical channel transmission unit;

locking the waterline value of each lane fifo at the timing pulse;

determining whether a waterline difference value between a maximum lane fifo waterline value and a minimum lane fifo waterline value is greater than a preset first threshold value;

if yes, resetting all the Lane fifo at the same time to align and adjust all the Lane fifo, otherwise, not resetting each Lane fifo.

Wherein the alignment module is further configured to:

clearing all the Lane fifo and controlling the read function preparation signals of all the Lane fifo to be set to a low level;

when the real-time waterline value of each lane fifo reaches a preset second threshold value, the read function preparation signal of the corresponding lane fifo is controlled to be set to a high level so as to respond to the corresponding read request.

Wherein the alignment module is further configured to:

sequencing the waterline values of the Lane fifo locked at the timing pulse by an bubbling sequencing method;

wherein the period of the timing pulse is greater than or equal to the number of beats required to order the watermark values of the respective lane fifo.

Wherein, the setting module is further used for:

when each frame header FP of the optical channel transmission unit performs multi-logical channel distribution, a virtual frame header VFP is set on a predetermined logical channel.

Wherein, the generating module is further used for:

selecting one logic channel of the optical channel transmission unit as the preset logic channel;

when the FP appears on any logic channel of the optical channel transmission unit, generating the VFP at the position which is the same as the FP time sequence position on the preset logic channel;

wherein the VFP is a sideband signal.

Wherein, the generating module is further used for:

determining a sending time compensation value according to the offset of the VFP in one beat of data after the data bit width conversion and the transmission rate of the optical channel transmission unit;

compensating the time stamp of the VFP reaching the serial deserializing parallel interface according to the transmission time compensation value;

and taking the compensated VFP timestamp as a multiframe for determining path delay to instruct the MFP to send the timestamp, and loading the timestamp into the PTP message.

Wherein, the generating module is further used for:

when any lane fifo detects that a multi-frame indicates an MFP, after delaying for a preset time, acquiring the offset of the VFP in one beat of data and the time stamp of the VFP reaching a serial deserializing and parallel interface after data bit width conversion;

the preset time is greater than the time required for transmitting the data quantity corresponding to the first threshold value.

Wherein the device is also used for:

and setting the time stamp of the next VFP reaching the serial deserializing and parallel interface to cover the time stamp of the next VFP reaching the serial deserializing and parallel interface.

It should be noted that, for convenience and brevity of description, specific working procedures of the above-described apparatus and each module and unit may refer to corresponding procedures in the foregoing embodiments, and are not repeated herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments. While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method for determining a transmission time stamp, comprising:

performing alignment adjustment on all serial deserialized channel buffer cache in the optical channel transmission unit;

setting a virtual frame header VFP for indicating the time sequence position of the frame header FP on a preset logic channel of the optical channel transmission unit;

a transmit timestamp for determining the path delay is generated based on the timestamp of the VFP arrival at the serial deserialization parallel interface.

2. The method for determining a transmission time stamp according to claim 1, wherein the aligning all serial de-concatenated channel buffers lane fifo in the optical channel transmission unit includes:

generating a timing pulse based on a system clock of the optical channel transmission unit;

locking the waterline value of each lane fifo at the timing pulse;

determining whether a waterline difference value between a maximum lane fifo waterline value and a minimum lane fifo waterline value is greater than a preset first threshold value;

if yes, resetting all the Lane fifo at the same time to align and adjust all the Lane fifo, otherwise, not resetting each Lane fifo.

3. The method for determining a transmission time stamp according to claim 2, wherein resetting all the lane fifo at the same time to perform alignment adjustment of all the lane fifo comprises:

clearing all the Lane fifo and controlling the read function preparation signals of all the Lane fifo to be set to a low level;

when the real-time waterline value of each lane fifo reaches a preset second threshold value, the read function preparation signal of the corresponding lane fifo is controlled to be set to a high level so as to respond to the corresponding read request.

4. The method for determining a transmission time stamp as recited in claim 2, further comprising, before determining whether a difference between a maximum lane fifo watermark value and a minimum lane fifo watermark value is greater than a preset first threshold value,

sequencing the waterline values of the Lane fifo locked at the timing pulse by an bubbling sequencing method;

wherein the period of the timing pulse is greater than or equal to the number of beats required to order the watermark values of the respective lane fifo.

5. The method for determining a transmission time stamp according to claim 1, wherein setting a virtual frame header VFP for indicating a frame header FP timing position on a predetermined logical channel of the optical channel transmission unit, comprises:

selecting one logic channel of the optical channel transmission unit as the preset logic channel;

when the FP appears on any logic channel of the optical channel transmission unit, generating the VFP at the position which is the same as the FP time sequence position on the preset logic channel;

wherein the VFP is a sideband signal.

6. The method for determining a transmission time stamp according to claim 2, wherein the generating a transmission time stamp for determining a path delay based on a time stamp of the VFP arrival at the serial-deserialized parallel interface comprises:

and generating a sending time stamp for determining path delay according to the time stamp of the VFP reaching the serial deserializing parallel interface and the offset of the VFP in one beat of data after the data bit width conversion.

7. The method for determining a transmission time stamp according to claim 6, wherein the generating a transmission time stamp for determining a path delay according to an offset of the VFP in one beat of data after the VFP arrives at the serial-to-deserialized parallel interface and the data bit width conversion includes:

determining a sending time compensation value according to the offset of the VFP in one beat of data after the data bit width conversion and the transmission rate of the optical channel transmission unit;

compensating the time stamp of the VFP reaching the serial deserializing parallel interface according to the transmission time compensation value;

and taking the compensated VFP timestamp as a multiframe for determining path delay to instruct the MFP to send the timestamp, and loading the timestamp into the PTP message.

8. The method for determining a transmission time stamp according to claim 6, further comprising, before generating a transmission time stamp for determining a path delay from an offset of the VFP in one beat of data after the VFP arrives at the serial-to-deserialized parallel interface based on a time stamp of the VFP and a data bit width conversion:

when any lane fifo detects that a multi-frame indicates an MFP, after delaying for a preset time, acquiring the offset of the VFP in one beat of data and the time stamp of the VFP reaching a serial deserializing and parallel interface after data bit width conversion;

the preset time is greater than the time required for transmitting the data quantity corresponding to the first threshold value.

9. The method for determining a transmission time stamp according to claim 6, further comprising:

and setting the time stamp of the next VFP reaching the serial deserializing and parallel interface to cover the time stamp of the next VFP reaching the serial deserializing and parallel interface.

10. A transmission time stamp determining apparatus, comprising:

the alignment module is used for carrying out alignment adjustment on all serial deserialized channel buffers lane fifo in the optical channel transmission unit;

a setting module, configured to set a virtual frame header VFP for indicating a frame header FP timing position on a predetermined logic channel of the optical channel transmission unit;

and the generating module is used for generating a sending time stamp for determining the path delay based on the time stamp of the VFP reaching the serial deserializing parallel interface.

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