JPH05175928A - Synchronization terminal station equipment - Google Patents

Abstract

PURPOSE:To reduce the circuit scale without changing a frame phase of a signal by implementing transfer of an in-equipment clock and replacing a pointer at the output of a low-order group signal of an active reception unit. CONSTITUTION:A selection section 103 of an active system 106 selects an output of a reception section 101 or an output from a standby system 108 via a branch circuit 102 and sends the selected output to a pointer replacement section 105. The replacement section 105 transfers the clock into a clock generated by an in-equipment clock source 104 in frequency-synchronization with a synchronization system reference clock and replaces a pointer and sends the resulting signal to a subordinate equipment. An output of the active system reception section 101 is selected in the normal state and an output of the circuit 102 is selected on the occurrence of a fault. Then the replacement section 105 transfers the clock to the clock from the clock source 104 and changes the pointer of the signal to be sent based on the frame phase generated by the clock source 104. Thus, the circuit scale of the memory is reduced without changing the phase of the frame to be sent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is based on the NNI standard STM-
The present invention relates to a synchronous terminal device that transmits n signals and is redundantly configured from a plurality of active systems and one standby system.

[0002]

2. Description of the Related Art In a conventional N to 1 redundant configuration synchronous terminal device, as shown in FIG. 4, an output of a branch circuit 202 for branching an output of an active system reception unit 201 and a signal input from a standby system 208. After selecting one of the two in the selecting unit 203, the buffer memory 205 sends a signal to the lower device in synchronization with the frame phase generated by the in-device clock source 204 that is frequency-synchronized with the synchronization system reference clock, and also when switching. The frame phase of the signal received by the lower device is made constant.

[0003]

In such a conventional example, a clock source is provided for each device of the active system and the standby system, and these are frequency-synchronized with the reference clock in the office, but the frames between the devices are provided. The phase relationship is not specified. Therefore, the buffer memory unit 205 for frame phase adjustment in FIG. 4 requires a memory capacity for one frame. This is 1 of STM-1 for STM-1 transmission.
There is a drawback in that the circuit scale is remarkably large because a high-speed and large-capacity memory of 19440 bits is required at 155.52 Mb / s per book.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a synchronous terminal device in which the circuit scale of the memory for replacement is reduced.

[0005]

SUMMARY OF THE INVENTION The present invention comprises a plurality of working systems and one standby system, and the working system comprises
A receiving unit that receives a signal input from a transmission line to generate an in-station signal and a signal that is input from the standby system or another working system are branched, and one of the branched signals is sent to the own device and the other is sent to the other. In the synchronous terminal equipment of the synchronous system, which includes a branch circuit for sending to the active system, and a selecting unit for selecting one of the signal output by the receiving unit and the signal output by the branch circuit,
The present invention is characterized by including a pointer replacement unit that transfers the signal output by the selection unit to the in-device clock and replaces the pointer.

[0006]

The pointer is replaced so as not to change the frame phase of the signal transmitted to the lower device at the time of switching. As a result, a memory size that only considers clock replacement is considered, and therefore the memory capacity can be reduced.

Here, clock replacement means that writing to the memory section is performed by the input clock paired with the input data, and reading is performed by the clock input from the clock / frame pulse generating section. In this way, changing a clock paired with input data from one clock to another clock. This clock transfer is realized in the memory unit in the point changing unit.
In addition, the point replacement means that the phase relationship between the memory read frame and the start position in the payload of the read signal is the phase between the write frame at the memory input and the start position in the payload of the input signal. Since it is different from the relationship, it means changing the pointer to correct the change. This is realized by generating a new pointer value corresponding to the post-replacement frame phase by the pointer calculation unit and inserting the value by the pointer insertion unit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of an N to 1 redundant configuration synchronous terminal device using the synchronous terminal device of the present invention. Figure 1 is 2 to 1
In the case of a redundant configuration, 106 and 109 are the active system and 108 is the standby system. As shown in FIG. 1, this embodiment is composed of a plurality of working systems and one standby system, and the working system receives a signal input from a transmission line and generates an in-station signal. A system receiving unit 101, a branch circuit 102 for branching a signal input from the standby system or another active system, and sending one of the branched signals to its own device and the other to the other active system, and an active system reception A selection unit 103 that selects one of the signal output by the unit 101 and the signal output by the branch circuit 102 is provided.Furthermore, as a feature of the present invention, the signal output by the selection unit 103 is used as an internal clock. A pointer reassigning unit 105 is provided for relocating and reassigning pointers.

Next, the operation of this embodiment will be described. FIG. 2 shows the input / output phases of the pointer reassignment unit 105. A in the figure
Indicates an intra-apparatus frame by the intra-apparatus clock, b in the figure represents an input frame from the selecting section 103, c in the figure represents input data from the selecting section 103, and d in the figure.
Shows the output data of the pointer replacement unit 105. The pointer replacement unit 105 first confirms the value of the pointer in the input data. After that, in the memory, the clock input from the selection unit 103 is replaced with the clock of the in-device clock 104, and then the phase difference information between the frame from the selection unit 103 and the frame of the in-device clock source 104 is also acquired. And the pointer value (value indicating the start position of the payload, which is the actual data other than overhead) is changed. That is, as shown in FIG. 3, the phase relationship between the head of the frame and the head of the payload after changing the clock is different from that before changing the clock. Therefore, change the pointer value indicating the beginning of the payload by the variation. It suffices for the memory to simply change the clock. In the figure, a indicates the frame before the clock change, b in the figure indicates the data before the clock change, and c in the figure.
Indicates the frame after the clock change, and d in the figure
Indicates the data after the clock change.

In the active system 106, a branch circuit for branching the output of the active system receiving unit 101 and the signal output from the standby system 108.
After one of the outputs of 102 is selected by the selection circuit 103, the pointer reassigning unit 105 replaces it with the in-device clock generated by the in-device clock source 104 that is frequency-synchronized with the synchronous reference clock, and changes the pointer It replaces and sends a signal to the lower device. When normal, the output of the active system reception unit 101 is selected, and when an abnormality occurs on the transmission line, the output is switched to the standby system and the output of the branch circuit 102 is selected. Usually, the output of the active system reception unit 101 and the output of the branch circuit 102 have different frame phases, and when switching occurs, the frame phase of the input of the pointer reassignment circuit 105 changes. In response to this, the pointer reassignment unit 105 changes the pointer value of the signal to be sent to the lower device based on the frame phase generated by the in-device clock source 104 by changing the clock to the clock of the in-device clock source 104. The frame phase sent to the lower device is not changed.

Next, a second embodiment of the present invention will be described with reference to the drawings. 5 to 8 are block diagrams showing the structure of the second embodiment. In this embodiment, as shown in FIGS. 5 to 8 and FIG. 10, a first clock for generating an in-device clock whose matching with the frequency of the clock generated by another clock source is restricted and whose matching with the phase is not restricted is provided. A clock / frame pulse generator 5, which is a clock source, and a first out-of-office signal frame carrying a plurality of multiplexed data signals and pointer information indicating the start position of the data signals are transmitted from the working transmission path 300. In-station signal generation means for receiving and demultiplexing the data signal on the first out-of-station signal frame to generate a first in-station signal frame, which occurs in the first out-of-station signal frame passing through the working transmission path 300. Transmission path abnormality detecting means for detecting abnormalities (the intra-station signal generating means and the transmission path abnormality detecting means are the frame synchronization unit 1,
The overhead termination unit 2 and the demultiplexing unit 3), and the information carried in the first intra-station signal frame is transferred to the second intra-station signal frame synchronized with the in-device clock generated by the clock source of the own unit. A plurality of working receiving units including a first receiving means including a point changing section 4a for changing the contents of the pointer information.
100, and a clock / frame pulse generator 250 that is a second clock source that generates an in-apparatus clock whose matching with the frequency of the clock generated by another clock source is restricted and whose matching with the phase is not restricted; The second out-of-office signal frame carrying the same information as that in the out-of-office signal frame is received from the backup transmission line 400, and the data signal on this second out-of-office signal frame is demultiplexed. Intra-station signal generation means for generating a third intra-station signal frame (the intra-station signal generation means and the transmission path abnormality detection means include a frame synchronization section 210, an overhead termination section 220 and a demultiplexing section 23.
0), and the information carried in the third intra-station signal frame is transferred to the fourth intra-station signal frame synchronized with the in-device clock generated by the clock source of the own unit, and the contents of the pointer information are replaced. And one receiving unit including a receiving unit including a point changing unit 240 for performing the operation. Each of the working receiving units 330 includes a branching unit 61 that is a branching unit and a selecting unit 62 that is a selecting unit. The selection means 8 includes a selection control section 8, and this branching means gives one of the two branched intra-station signal frames to the selection means of its own unit so that the fourth intra-station signal frame from the standby receiving unit 200 or another currently used Receiver unit
The selection means includes means for giving the other second intra-station signal frame which is branched into two by the branching means included in one of the 100, and the selection means is the A means for switching the second intra-station signal frame from the one receiving means to the fourth intra-station signal frame passing through the branching means, and further as a feature of the present invention, is cascade-connected to the selecting means, With a point for transferring the signal frame passing through the selecting means to the fifth intra-station signal frame synchronized with the clock generated by the clock source of the own unit and also changing the contents of the pointer information carried on the signal frame passing through this selecting means The replacement unit 4b is provided. Here, point replacement unit 4
b is a means for detecting the start position of the data signal positioned after the pointer information position based on the content of the pointer information placed on the signal frame passing through the selecting means, and the selecting means. A memory unit 42, which is a clock / frame changing means for changing the contents of the signal frame passing through to the internal clock generated by the clock source of the own unit and the frame generated by the internal clock, and this memory unit Generate pointer information representing the starting position of the data signal for a predetermined pointer position in a new frame based on the clock and frame after the 42 crossing, and use this pointer information in the output signal of the clock frame crossing means. With point to be inserted as new pointer information A place means pointer calculator 43
And a pointer insertion unit 44.

Next, the operation of this embodiment will be described. In this embodiment, the M-system active receiving units 100-1 to 100-M and the standby receiving unit 200 are provided, and each unit is mounted on a separate device rack. Working receiver unit 100-1 to 100-M
Are CCITT Recommendations G. The STM-M signal 708 is input from each of the active transmission lines 300-1 to 300-M, demultiplexed, and then transmitted as N STM-1 signals to the N low-order group transmission lines. Low order group signal is STM-
Although it may be other than 1, it will be described as STM-1 here. The working receiving unit 100-1 is provided with a frame synchronization unit (SY
NC) 1 and overhead termination (OH TRM) 2
, A demultiplexing unit (DMUX) 3, a first point changing unit 4a, and a clock / frame pulse generating unit (CLK /
FP GEN) 5, a switching unit 6, a second point replacement unit 4b, an overhead insertion unit 7, and a selection control unit 8. The frame synchronization unit 1 detects a frame synchronization signal in a frame with respect to the STM-M signal input from the active transmission path 300-1 and divides the transmission path clock to synchronize with a frame pulse generated by the frame synchronization operation. Along with
Outputs information on an abnormality in the current transmission line such as the frame sync signal being undetectable or the input of the current transmission line signal being cut off.

FIG. 9 shows the frame format of the STM-1 signal. The signal rate of STM-1 signal is 155.52Mb /
s One frame length is 19440 bits (2430 bytes). In one frame, a cycle T of an overhead of 9 bytes and a payload (payload: a framed data string having substantial transmission information from a terminal station) is repeated 9 times. The 6-byte frame synchronization signal (A1, A1, A1, A
2, A2, A2), and C for other overheads.
CITT Recommendation G. The information defined in 708 is entered. In addition, a pointer (H
1 and 3 bytes each for H2) are inserted. The content of this pointer indicates the number of data bits from immediately after the last bit of the H3 byte of the third cycle T to the frame start position of the data string in the payload, and the receiving side interprets the pointer to Detect the frame start position. The overhead termination unit 2 terminates the overhead in the STM-M signal input from the current transmission path, monitors the transmission path for errors, and outputs the transmission path error information and the switching information in the overhead sent from the transmission side. To do. The demultiplexing unit 3 uses CCITT Recommendation G.264. According to the multiplexing side of 708, the STM-M signal is demultiplexed into N STM-1 signals.

The first and second point changing units 4a and 4b are pointer interpreting units (PTRINT) 41-1 to 4-4.
1-M and memory units (MEM) 42-1 to 42-M,
Pointer calculation unit (PTR PROC) 43-1 to 43-
M and pointer insertion unit (PTR INS) 44-1 to 4-4
4-M, and N parallel STM-1 signals, clocks and frame pulses are input from the demultiplexing unit 3 or the switching unit 6 in parallel, and each STM-1 signal has a circuit of the same configuration.
FIG. 10 shows a pointer interpretation unit 41-1 in the point replacement unit 4a or 4b, a memory unit 42-1, a pointer calculation unit 43-1 and a pointer insertion unit 44-1. Figure 1
1 to 13 are timing charts showing the operation.

Here, the first point changing section 4a is means for terminating the transmission line and changing the clock in the device, and the second point changing section 4b is switched by the switching section 6. It is a means as a buffer for sometimes absorbing the phase change of the low-order group signal outputs 1 to N and preventing the phase change. As shown in FIG. 10, the STM-1 signal, the clock and the frame pulse from the demultiplexing unit 3 or the switching unit 6 are converted into 24 parallel signals by the serial / parallel conversion (S / P) unit 411. At this time, the bit rate of each parallel signal is 15
The speed is reduced to 5.52 Mb / s / 24 = 6.48 Mb / s. FIG. 11 shows the input and output signals of the serial / parallel converter 411.
The serial-parallel conversion is started when the frame pulse is input. The pointer interpretation unit (PTR INT) 412 is
The positions of the pointers H1 and H2 are detected from the parallel signal of the TM-1 signal. In the STM-1 signal, the position of the pointer is determined in advance from the frame pulse A1. Therefore, the position of the pointer can be easily detected. The frame header generation unit (FH GEN) 413 detects the frame start position of the data string in the payload after H3 bytes based on the pointer information at the pointer position, and generates the frame header pulse FH in that time slot. .. The frame header pulse FH is stored in the memory unit 42-
It is read by the read clock immediately after being stored in the first memory unit (MEM) 421. The memory unit 421 has 24 parallel input / parallel output FIFO memories. Here, an 8-bit memory will be described as an example. The 24 parallel signals from the serial / parallel converter 411 are temporarily stored in the respective 8-bit parallel input / output memories by the write clocks WPLS1 to 8 shown in FIG. Although the memory input in FIG. 12 shows only one input of the 24 parallel signals, the 24 parallel signals are not shown in the write clock generator (WCLK).
It is written in 24 8-bit parallel input / output memories by write clocks WPLS1 to WPLS1 to GEN4. The write clocks WPLS1-8 have overhead (O
The generation is stopped in the period H), and is repeatedly generated in the payload period. Write clock WPLS1
One cycle of each of 8 is 8 bits and is generated by shifting by 1 bit. The memory unit 421 has a write clock WPLS1.
Write new data at every rising edge of ~ 8. The reading of the memory unit 421 is performed by the read clock generation unit (RCLK G
This is performed when the read clocks RPLS1 to 8 from EN) 423 are at the low level. Read clock RPLS1 to
8 is generated in synchronization with the clock from the clock / frame pulse generator 5. Further, the generation of the read clock is stopped during the overhead (OH) period, and the reading during this period is lengthened by the overhead. The pointer calculation unit (PTR PROC) 43-1 is a read frame (frame pulse from the clock / frame pulse generation unit 5).
"0" at the position immediately after H3 byte on 1 frame based on
It has a counter that is reset to (see FIG. 13). When the frame header pulse FH is supplied from the memory unit 421, in the case of FIG. 13, in response to the frame header pulse FH, the counter output as a value indicating the frame head of the payload immediately after the H3 byte of the previous frame. The value 778 is inserted by the pointer inserter (PTR INS) 44-1 at the pointer position of the new frame. The overhead in the output data string of the pointer insertion unit 44-1 is not present except for the pointer, but the position for inserting the other overhead is secured as shown in the memory output of FIG. That is, the counter of the pointer calculation unit 43 is
A read-out frame (READ OUT FRAME) from the memory unit 421 shown in FIG. 10 resets to "0" in one frame cycle. The phase of this read-out frame is the position immediately after the H3 byte after memory reading. That is, a pulse having such a phase is output as a lead-out frame. Since the reference point for indicating the frame start position in the payload (the frame start position in the payload when the pointer value is "0") is located immediately after the H3 byte, the counter value itself indicates the pointer value.
Frame header pulse (F
(H pulse) coincides with the frame head position in the payload. Therefore, if the counter value of the pointer calculation unit 43 is latched at the phase of the FH pulse, the latched counter value is stored in the clock and frame by the memory unit 421. Indicates the frame start position in the payload after the transfer of, ie, a new pointer value. After the pointer is replaced, the overhead is inserted in the overhead inserting section 7 shown in FIG. 5, and the overhead inserting position at this time is secured in the signal output from the memory section 421. That is, as shown in FIG. 12, it is ensured by stopping the generation of the memory read pulse (RPLS) at the portion where the overhead should be inserted.

The switching unit 6 includes branching units 61-1 to 61-M and selecting units 62-1 to 62-M. Branching part 61-1
61-M is N STs input from the standby receiving unit.
Each of the M-1 signals is branched into two. Selection units 62-1 to 6-6
2-M outputs one of the output of the branching unit and the output of the first point changing unit 4a under the control of the selection control unit 8. The overhead inserting section 7 has an N number corresponding to the N STM-1 signals output from the second point changing section 4b.
Each of the overhead insertion portions 70-1 to 70-M,
Each overhead other than the pointer in the frame shown in FIG. 9 is inserted and output to the low-order group transmission line. The selection control unit 8 inputs information on the working transmission path abnormality from the frame synchronization unit 1 and the overhead termination unit 2, and accordingly, the selection units 62-1 to 62-1.
The 62-M selection control signal is output. The branching units 61-1 to 61-M of each working receiving unit are provided to reduce the number of output signals of the standby receiving unit. If this is not present, the spare receiver unit 200 will be
The same signal must be branched and connected to 100-1 to 100-M, and the number of low-order group outputs of the standby receiving unit becomes enormous.

The preliminary reception unit 200 includes a frame synchronization unit 21.
0, the overhead termination unit 220, the demultiplexing unit 230,
The point replacement unit 240 and the clock / frame pulse generation unit 250 are included. The operation of each section is as follows: the frame synchronization section 1, the overhead termination section 2, the demultiplexing section 3,
Point replacement unit 4, clock / frame pulse generation unit 5
Is the same as.

According to the present invention, even when the low order group signal demultiplexed by the working receiving unit is sent to the low order group transmission line, the low order group signal demultiplexed by the spare receiving unit is transmitted to the low order group transmission line. In order to prevent the clock and the frame phase from changing even when they are sent to the device, the pointer value is changed according to the frame in the apparatus, instead of performing the phase adjustment in the buffer memory for one frame.

[0019]

According to the present invention, even when the low order group signal demultiplexed by the working receiving unit is sent to the low order group transmission line, the low order group signal demultiplexed by the standby receiving unit is reduced to the low order group signal. In order to prevent the clock and the frame phase from changing even when sending out to the transmission line, the pointer is changed when the low-order group signal of the working receiving unit is output. Therefore, it is necessary to store the signal for one frame in the buffer memory. Therefore, there is an effect that a small-capacity memory is sufficient and a circuit scale can be reduced without requiring a high-speed and large-capacity memory.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 4 is a block configuration diagram showing a configuration of a conventional example.

FIG. 5 is a block diagram showing the overall configuration of a second embodiment of the present invention.

FIG. 6 is a block configuration diagram showing a configuration of a point replacement unit included in FIG.

7 is a block configuration diagram showing a configuration of a switching unit included in FIG.

8 is a block configuration diagram showing a configuration of an overhead insertion unit included in FIG.

FIG. 9 is a frame format diagram of an STM-1 signal used in the embodiment of the present invention.

FIG. 10 is a block configuration diagram showing the configuration of each part of the point replacement unit shown in FIG.

11 is a timing chart showing the operation of the serial / parallel conversion section of the point changing section shown in FIG.

12 is a timing chart showing the operation of each unit of the point changing unit shown in FIG. 10 except for the serial / parallel conversion unit.

FIG. 13 is an explanatory diagram illustrating an operation of the point replacement unit shown in FIG. 6.

[Explanation of symbols]

1, 210 Frame synchronization unit (SYNC) 2, 220 Overhead termination unit (OH TRM) 3, 230 Demultiplexing unit (DMUX) 4, 240 Point replacement unit 5, 250 Clock / frame pulse generation unit (C
LK / FP GEN 6 switching unit 7 overhead insertion unit 8 selection control unit (SEL CONT) 41, 241 pointer interpretation unit (PTR INT) 42, 242 memory unit (MEM) 43, 243 pointer calculation unit (PTR PROC) 44, 244 pointer insertion unit (PTR INS) 61 branching unit (DIS) 62 selection unit (SEL) 70 overhead insertion unit (OH INS) 100, 330 active reception unit 101, 201 active reception unit 102, 202 branch circuit 103, 203 selection Units 104 and 204 Internal clock source 105 Pointer replacement unit 106, 109, 206, 209 Active system 107, 207 Spare system receiving unit 108, 208 Spare system 200 Spare receiving unit 205 Buffer memory 300 Active transmission line 400 Spare transmission line 411 Cereal par Rel- conversion section (S / P) 412 pointer interpretation unit (PTR INT) 413 frame header generator (FH GE
N) 421 memory unit (MEM) 422 write clock generation unit (WCLK G
EN) 423 Read clock generator (RCLK G
EN)

Claims (3)

[Claims] 1. A system comprising a plurality of working systems and one standby system, wherein the working system receives a signal input from a transmission line to generate an in-station signal, and the standby system or A branch circuit for branching an intra-station signal input from another active system and sending one of the branched intra-station signals to the device itself and the other to the other active system; an intra-station signal output from the receiving unit and the branch circuit. In a synchronous terminal device of a synchronous system having a selection unit for selecting one of the intra-station signal output by the device, a pointer for transferring the intra-station signal output by the selection unit to the in-device clock and changing the pointer. A synchronous terminal station device comprising a reassignment unit. 2. A first clock source for generating an in-device clock whose matching with a frequency of a clock generated by another clock source is restricted and whose matching with a phase is not restricted, and a plurality of multiplexed data signals. And a first out-of-office signal frame carrying pointer information indicating the start position of this data signal is received from the working transmission line, and the data signal on this first out-of-office signal frame is demultiplexed and The in-station signal generation means for generating the in-station signal frame, the transmission path abnormality detection means for detecting an abnormality occurring in the first out-of-station signal frame passing through this working transmission path, and the information carried in the first in-station signal frame With the first point to transfer to the second in-station signal frame synchronized with the in-device clock generated by the clock source of its own unit and to replace the contents of the above pointer information Generating an in-device clock whose matching with the frequencies of the clocks generated by other clock sources is constrained and whose phase matching is not constrained, and the plurality of active receiving units including the first receiving means including the replacement unit A second clock source and a second out-of-office signal frame carrying the same information as the information carried in the first out-of-office signal frame are received from the backup transmission line, and the second out-of-office signal frame on this second out-of-office signal frame is received. In-station signal generation means for demultiplexing a data signal to generate a third in-station signal frame, and a third means for synchronizing information carried in the third in-station signal frame with an in-device clock generated by a clock source of the own unit. And a receiving means including a second point changing section for changing the contents of the pointer information and changing the contents of the in-station signal frame. Each of the working receiving units includes a branching unit and a selecting unit, and this branching unit supplies one of the two second intra-station signal frames branched to the selecting unit of its own unit, and the fourth receiving unit from the standby receiving unit. The selecting means includes means for giving the other second intra-station signal frame which is bifurcated by the branch means included in the intra-station signal frame or one of the other active receiving units, wherein the selecting means is a transmission path abnormality detecting means of the own unit. In the synchronous terminal station device including means for switching the second in-station signal frame from the first receiving means to the fourth in-station signal frame via the branching means when an abnormality is detected, the connection is cascaded to the selecting means. , The signal frame passing through this selecting means may be replaced with the fifth intra-station signal frame synchronized with the clock generated by the clock source of the own unit. The synchronous terminal station device, further comprising a third point reassigning section for reassigning the contents of the pointer information placed on the signal frame passing through the selecting means. 3. The third point changing section detects the start position of a data signal positioned after the pointer information position based on the content of the pointer information put on the signal frame passing through the selecting means. And a clock / frame changing means for changing the contents carried in the signal frame passing through the selecting means to the internal clock generated by the clock source of the own unit and the frame generated by the internal clock, and the memory. Generating pointer information indicating the starting position of the data signal with respect to a predetermined pointer position in a new frame based on the clock and frame after the replacement by the unit 42, and outputting this pointer information to the output signal of the clock frame replacement means. Points to be inserted as new pointer information in the The synchronous terminal device according to claim 2, further comprising: