JP3408634B2 - Frame phase synchronization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame phase synchronization circuit, for example, an SDH (Synchronous D).
The present invention can be applied to a frame phase synchronization circuit of an in-device transmission frame of a digital hierarchy. [0004] In recent years, SDH has been internationally standardized as a multiplexing method that can be efficiently applied to various services including data and video, from services centered on telephones. In this synchronous digital hierarchy multiplexing apparatus, it is necessary to synchronize the frame phases of a plurality of pieces of multiplexed information input from a transmission line with a reference frame phase in the apparatus. As this method, a frame phase synchronization method using a pointer is adopted. [0004] This means that in synchronous multiplexing, 125 μs
When frame synchronization is performed for each ec, the difference between the time phase of the transmission frame and the frame time phase of the multiplexing information is displayed as the difference between the address positions of the time slots in order to minimize the multiplex processing delay time. In this way, the memory capacity can be reduced. As described above, a plurality of frames input from the transmission line are received by a plurality of boards, and transmitted to other boards in the apparatus in synchronization with a reference frame phase in the apparatus. A reference frame distributed to each board in the device has a delay difference due to a difference in a distribution circuit and a wiring length, and a phase difference has occurred in a transmission frame in the device. [0006] In addition, since the phase difference is enlarged even in the process of multiplexing the intra-device transmission frames and synchronizing the bits, a phase difference of several bits may eventually occur. Therefore, in intra-apparatus transmission, a circuit for absorbing a phase difference between frames of intra-apparatus transmission frames input from a plurality of boards and synchronizing the frame phase is required. The technology of such a circuit is disclosed in, for example, Japanese Patent Application Laid-Open Nos. 3-249830 and 4-728.
No. 34, JP-A-63-220629 and the like. Basic techniques are also described in "SDH Transmission System" published by Ohmsha, pages 46-56, and the role of 3.4 pointers. These techniques have a configuration (method) of detecting the latest timing from a frame pulse indicating the head of an input frame signal and generating a read reset signal for a memory. Further, the frame pulse is transferred through an elastic (elastic) circuit similarly to the frame signal. Incidentally, such an elastic store (e)
The "last store" circuit is, for example, a circuit that can perform writing and reading independently at different speeds. [0010] However, in the conventional configuration (method), the optimum phase is detected by a pulse signal such as a frame pulse or a write reset, so that a circuit for extending the pulse is required. . For this reason, "the circuit scale was large." For example, if a circuit for extending a pulse is constituted by a set / reset (RS) flip-flop and is released by a read / reset pulse, the circuit becomes small, but has the following problems. That is, a read reset pulse is output when all of the predetermined number of write reset pulses have been collected. Therefore, if all the write reset pulses are not collected within one frame, the remaining write reset pulses will be output until the next frame. , And a read reset pulse is output when the last write reset pulse arrives. Therefore, it is not possible to predict the phase of the predetermined number of write reset pulses, and there is no guarantee that the output phase of the read reset pulse is optimal. In order to solve such a problem, it is necessary to provide a means for extending the write reset pulse to a specific width of one frame or less and terminating the process of detecting the optimum phase within one frame. . For example, it is conceivable to use a mono-multi vibrator, etc.
There is a problem that "the circuit scale becomes large". In view of the above, there has been a demand for providing a mechanism capable of capturing a synchronous digital hierarchy signal with a simple circuit configuration and achieving accurate frame phase synchronization. Means for Solving the Problems To solve the above problems
In addition, the present invention can store and read signals independently.
Elastic store circuit (including SDH input circuit)
A frame signal synchronization circuit comprising a plurality of
The rustic store circuit (1) converts the input data to the first
First storage means for storing according to a storage timing signal
And (2) transferring the data of the first storage means to a first read time.
First reading means for reading in accordance with a signaling signal;
The power frame signal is recorded according to the second storage timing signal.
And (4) the memory of the second storage means.
A readout timing signal in accordance with a second readout timing signal
(5) each of the elastics
Frame signal supplied from the second storage means in the toer circuit
Comparison result to compare the signals and generate this comparison result signal
Generating means; and (6) the first reading from the comparison result signal.
Generating a first read timing signal of the output means;
Controlling the generation of the second read timing signal of the output means,
Control means for performing control for synchronizing the frame phases.
(7) Second storage in each elastic store circuit
Frame phase for the frame signal supplied by the means
It is characterized by synchronization . According to each elastic store circuit included in the frame phase synchronization circuit of the present invention, the input data and the input frame signal are stored in the first frame. The first storage timing signal and the second storage timing signal can be stored, and
The data and the frame signal stored in the first storage means and the second storage means can be read independently by the first read timing signal and the second read timing signal. Since the frame signal written in the second storage means is configured to be output, a circuit for expanding the frame signal as in the related art is not required, and the circuit can be downsized. be able to. Further, in the invention of the frame phase synchronizing circuit of the present invention using the elastic store circuit having the above-described configuration, a frame supplied from a plurality of elastic store circuits is provided.
To take the phase synchronization of the frame signals to perform signal comparison of each frame <br/> beam signals (e.g., comparison of the timing, etc.). The timing control for outputting the signal synchronized with the frame phase and the data from the comparison result signal obtained by this comparison is accurately and optimally performed. With such a configuration, since the frame signal stored in the second storage means is used, it is considered that the delay of the read reset pulse can be reduced. Next, a preferred embodiment of the present invention will be described with reference to the drawings. "Configuration of Frame Phase Synchronization Circuit" FIG. 1 is a functional block diagram of the frame phase synchronization circuit of this embodiment.
In FIG. 1, the frame phase synchronization circuit includes an elastic store circuit 100, an AND circuit 200, and a differentiating circuit 300. Further, the elastic store circuit 100
Is a write counter 110 and a first memory 120
A second memory 130, a read counter 140,
It comprises a first multiplexer 150 and a second multiplexer 160. The first memory 120 writes the input data A from the synchronous digital hierarchy and supplies the written data to the first multiplexer 150. The first multiplexer 150 selects this data by the read timing signal K and outputs it as output data N. The write counter 110 is initialized by an input frame pulse B from the SDH, generates a write timing synchronized with a write clock C, and gives it to the first memory 120. The second memory 130 writes the input frame pulse B, and supplies the written data F to the second multiplexer 160 and the AND circuit 200. The second multiplexer 160 selects the data F written in the second memory 130 according to the read timing L, and sets it as an output frame pulse M. The read counter 140 generates read timings K and L synchronized with the read clock I, and supplies them to the first multiplexer 150 and the second multiplexer 160, respectively. The AND circuit 200 gives the result of the logical product of the data F written in the second memory 130 and the output G of another elastic circuit to the differentiating circuit 300. The differentiating circuit 300 converts the signal supplied from the AND circuit 200 into a pulse having a width of one clock synchronized with the read clock I, and supplies it to the read counter 140 as a read reset signal J. In addition, the “first memory 12
The capacity of 0 is set to a divisor of the number of bits in one frame. " By setting in this way, "the bit address for writing the head of the frame is always the same, so that the phase of the frame to be read can be kept from changing". It is assumed that the write counter 110 and the read counter 140 can run independently. FIG. 2 shows the second memory 1 shown in FIG.
FIG. 3 is a specific functional configuration diagram of a second multiplexer 160 and a second multiplexer 160. In FIG. 2, the second memory 130 includes:
NAND circuits 131 to 134 and inverters 135, 1
36. And the NAND circuit 13
1 to 134 constitute an RS flip-flop circuit. Further, the second multiplexer 160 includes an AND circuit 161. The inverter 136 is connected to the second memory 130
, And a second multiplexer 160, and inverts the output value of the NAND circuit 134. The NAND circuit 131 gives a set pulse to the NAND circuit 133 by the logical product of the data B and the write timing signal E. The NAND circuit 132 gives a reset pulse to the NAND circuit 134 by ANDing the value obtained by inverting the data B by the inverter 135 and the write timing E. The second multiplexer 160 outputs
The logical AND between the output F of the inverter 136 and the read timing signal L is defined as an output frame pulse M. FIG. 3 is a specific configuration diagram of the differentiating circuit 300 described in FIG. In FIG. 3, an AND circuit 30
1, NAND circuits 302 and 303, and a D flip-flop circuit 304. And NAN
The D circuits 302 and 303 constitute an RS flip-flop circuit. This RS flip-flop circuit is set by the D flip-flop 304 and reset by the negative logic of the data H. Also, the NAND circuit 302
Is supplied to the AND circuit 301 to inhibit the input of the data H. The D flip-flop 304 latches the output of the AND circuit 301 at the timing of the clock I and generates a read reset pulse J. [Operation] FIG. 4 is an operation waveform diagram (operation timing chart) of one embodiment. Here, the input data DI is serial and the output data DO is four parallel,
The description will be made on the assumption that the capacity of the first memory 120 is 1 bit × 12 words. First, when an input frame pulse B indicating the head of the input data A is input to the write counter 110,
The write counter 110 is initialized, and the value of the write timing D becomes 2. The write timing signal D output from the write counter 110 indicates a bit address. The D1 bit of the input data A is written to the bit address 1 of the first memory 120, and the D2 bit is the bit address of the first memory 120. 2 is written. Further, the timing signal E of the bit address 1 is output from the write counter 110 to the second memory 130.
The frame pulse B is written to the second memory 130 at that timing. Accordingly, the input frame pulse B is extended by the depth (the number of words) of the capacity of the first memory 120. The output F of the second memory 130 is supplied to the second multiplexer 160 and the AND circuit 200. The outputs of a plurality of memories (typically F and G) are AND
It is input to the circuit 200 and detects that all timing signals are aligned. Therefore, the change point of the output H of the AND circuit 200 indicates the timing at which data is written to the head of the memory of all the elastic circuits. Differentiating circuit 30
At 0, the data H is input, a read reset pulse J synchronized with the read clock I is generated, and given to the read counter 140. The read counter 140 receives the read reset pulse J and initializes the count value. Thereby, "frame phase synchronization on the reading side is established". Further, the initialization of the read counter 140 is not repeated every frame, but is prohibited in a normal state after the frame phase synchronization, and is permitted again at the time of initial setting or abnormality detection. A signal K for selecting a bit for every four bits is supplied from the read counter 140 to the first multiplexer 150, and the first multiplexer 150 selects one of the bits written in the first memory 120 based on the signal K. Select the output data N. Also, the read counter 140
Outputs the selection signal L to the second multiplexer 160, the second multiplexer 160 outputs the data F written to the second memory 130 at the timing of the selection signal L.
Is selected to output the frame pulse M. (Effect of One Embodiment) According to the elastic store circuit 100 of the above embodiment, the input data and the input frame pulse can be stored by the write timing signals D and E, and The data stored in the first memory 120 and the second memory 130 and the frame pulse are independently read from the read timing signal K,
And L. The above-mentioned elastic store circuit 1
According to the frame phase synchronization circuit using 00, since the frame pulse written in the second memory 130 is output to the AND circuit 200, it is particularly necessary to add a circuit for extending the frame pulse as in the related art. Is eliminated, and the circuit can be downsized. Further, by using the frame pulse written in the second memory 130, the delay of the read reset pulse can be reduced. Furthermore, if the AND circuit 200 is incorporated into the elastic circuit 100, a plurality of elastic store circuits 100 can be easily cascaded to realize a plurality of frame phase synchronizations, so that the circuit is simple in configuration. it can. (Other Embodiments) (1) In addition to the operation shown in FIG.
FIG. 5 shows an operation waveform diagram when the output data N is serial and the capacity of the first memory 120 is 12 bits of 4 bits × 3 words. In FIG. 5, the first four bits of input data A are written to address 1 of first memory 120, and the next four bits are written to address 2. The selection signal K supplied from the read counter 140 to the first multiplexer 150 is a signal for selecting data written in the first memory 120 for each bit. Other operations are the same as those in FIG.
B is a timing signal of an input frame pulse, C is a write clock, D is a write timing signal, E is a write signal from the write counter 110 to the second memory 130,
F is the output signal of the second memory, G is the output of another elastic circuit, H is the output signal of the AND circuit 200, I is the read clock, J is the read reset pulse, and K is the read multiplexer 140 to the first multiplexer. L is a selection signal from the read counter 140 to the second multiplexer 160; M is a frame pulse;
Is output data. (2) The above-described frame phase synchronization circuit can be applied not only to a multiplex transmission apparatus but also to a transmission circuit inside the apparatus. In addition, it is considered that the present invention can be applied to various devices, such as a synchronous terminal device, a multiplex conversion device, a cross-connect device, a relay device, and a terminal relay device, which are interfaced with the synchronous digital hierarchy. (3) Further, the first memory 120 and the second memory 120
The memory 130 may be configured by a storage circuit such as a RAM, a flip-flop, a shift register, etc., in addition to being realized by the circuit illustrated in FIG. (4) In the above embodiment, the transmission level STM (Snyc
Hronous Transport Module:
Synchronous transmission module) -0 (51.84 Mbps), S
TM-1 (155.52 Mbps), STM-4 (62
2.08 Mbps), STM-16 (2488.32 M
bps) and STM-64 (9953.28 Mbps). [0054] [0055] [0056] frame phase synchronization circuit as described above the invention exhibits a comparison of the frame signal supplied from the second storing means of the plurality of elastic store circuit Do
A comparison result generation means for generating the comparison result signal; a generation of a first read timing signal of the first read means from the comparison result signal; and a generation of a second read timing signal of the second read means. And a control means for controlling the frame phase synchronization. With such a configuration, the phase synchronization of a plurality of frame signals can be accurately achieved with a simple configuration, and the output of data can be controlled. Therefore, according to the above-mentioned invention, the synchronous digital hierarchy signal can be taken in with a simple circuit configuration, and the frame phase can be accurately synchronized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional configuration diagram of a frame phase synchronization circuit according to an embodiment of the present invention. FIG. 2 is a specific functional configuration diagram of a second-rank memory and a second multiplexer according to one embodiment; FIG. 3 is a specific functional configuration diagram of a differentiating circuit according to one embodiment; FIG. 4 is an operation timing chart of one embodiment. FIG. 5 is an operation timing chart of another embodiment. [Description of Signs] 100 Elastic store circuit, 110 Write counter, 120 First memory, 130 Second memory, 140 Read counter, 150 First multiplexer, 160 Second multiplexer 200 ... AN
D circuit, 300 ... differentiation circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-157833 (JP, A) JP-A-3-249830 (JP, A) JP-A-4-72834 (JP, A) JP-A-63- 220629 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 7/00 H04J 3/06 H04L 13/08

Claims (1)

(57) [Claim 1] A frame signal provided with a plurality of elastic store circuits capable of independently storing and reading a signal
A synchronous circuit , wherein each of the elastic store circuits is configured to store input data in accordance with a first storage timing signal, and to store data in the first storage unit in accordance with a first read timing signal. a first reading means, second storage means for storing an input frame signal in accordance with a second memory timing signals, and a second reading means for the frame signal of the second storage means is read out in accordance with a second read timing signal Provided from the second storage means in each elastic store circuit.
The supplied frame signal is compared, and the comparison result signal
, And a first readout of the first readout unit from the comparison result signal.
Generation of timing signal and second reading by second reading means
Controls timing signal generation and frame phase synchronization
Control means for performing control that can be performed by the second storage means in each elastic store circuit.
A frame phase synchronization circuit for synchronizing a supplied frame signal with a frame phase .