JP3013767B2 - Frame timing phase adjustment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame timing phase adjusting circuit, and more particularly, to a frame timing phase adjusting circuit for changing a frame timing of received data to a reference frame timing in a receiving apparatus and outputting the same.

[0002]

2. Description of the Related Art When data is transmitted between devices or blocks by one-phase synchronization, the internal clock signal and frame signal of the device are determined based on the timing of a reference clock signal and a reference frame signal distributed to each device or each block. It is necessary to change the timing of the received data to each timing and determine the phase of the received data in the device so as to maintain a predetermined phase relationship between the received frame timing and the frame timing inside the device.

FIG. 4 shows an example of this type of conventional timing transfer circuit. The input serial data synchronized with each timing of the first clock signal and the first frame signal is:
The data is serial-parallel converted by the S / P converter 11 to be parallel data, and is input to the memory 12.

The write timing of the parallel data to the memory 12 is the write pulse timing by the write pulse generation circuit 5, and the write pulse generation circuit 5 operates in synchronization with the first frame signal and the second clock signal. is there.

[0005] The data written in the memory 12 is read by the read pulse timing generated from the read pulse generator 6 based on each timing of the second clock signal and the second frame signal, and is subjected to P / S conversion. The data is converted into serial data by the unit 13 and is derived as internal data of the apparatus.

In such a configuration, if the data is within the capacity of the memory 12, the data can be switched between the reception frame timing synchronized with the frequency and the frame timing in the apparatus. At this time, in order to perform the transfer properly, a necessary and sufficient memory capacity must be set in advance for a possible phase difference between the received (first) frame pulse and the internal (second) frame pulse. There is.

FIG. 5 shows another example of this type of conventional timing transfer circuit. The data transfer unit 1 transfers received input data from the timing of the first frame signal and the timing of the second clock signal to the timing of the second frame signal and the timing of the second clock signal.

The write reset generation section 7 generates a write reset pulse 71 for resetting a write pulse to a buffer in the data transfer section 1 based on the first frame signal and the first clock signal. The read reset generation section 8 generates a read reset pulse 81 for resetting a read pulse to a buffer in the data transfer section 1 based on the second frame signal and the second clock signal.

Power-on reset signal 10 at power-on
0 causes the load value selector 9 to write reset generator 7
By loading a value different from the load value of the write timing counter (for example, a value corresponding to the phase difference π), a certain phase difference (for example, between the received (first) frame timing and the internal (second) frame timing) (for example, π)
Are set between the write reset pulse 71 and the read reset pulse 81.

The phase difference detector 2 detects the phase difference between the write reset pulse 71 and the read reset pulse 81, and controls the load value selector 9 according to the phase difference.

With the configuration shown in FIG. 5, received data synchronized with the timing of the first frame signal is transferred to the data transfer unit 1.
In the above, serial / parallel conversion is internally performed according to the cycle of the write reset pulse 71, and the data is sequentially written to the buffer.

Reading from the buffer is performed by internally performing parallel / serial conversion in accordance with the period of the read pulse in synchronization with the timing of the second frame signal.

[0013]

In such a phase shift circuit, in order to absorb a phase difference between data between input and output and to determine a predetermined phase relationship, a memory having a capacity large enough to absorb the difference. And a buffer are required, resulting in a problem that the circuit scale becomes large.

On the other hand, in order not to use a memory or a buffer having a large capacity, there is a problem that it is necessary to strictly design data delay and timing between devices or blocks, and to perform phase matching by measurement. .

An object of the present invention is to provide a frame timing phase adjusting circuit which minimizes the capacity of a memory or a buffer and which does not require strict data delay and timing design.

[0016]

According to the present invention, a second clock signal having the same period as the first clock signal and a second clock signal having the same period from the first clock signal and the timing of the first frame signal synchronized with the clock signal are provided. A frame timing phase adjustment circuit having data transfer means for changing input data to a timing of a second frame signal synchronized with a second clock signal and having the same cycle as the first frame signal, wherein the second clock signal Phase difference detecting means for detecting a phase difference between the reference frame signal synchronized with the first frame signal and the first frame signal, and a period of the phase difference detected by the phase difference detecting means is standardized by a cycle of the second clock signal. Phase difference information generating means for generating the phase difference information, and the reference frame signal according to the standardized phase difference information. And a frame delay means that performs a delay control, frame timing phase adjustment circuit is obtained, characterized in that the timing of the delayed output to the second frame signal of said data transfer means.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention will be described. The phase difference between the received (first) frame signal and the internal reference frame signal is detected, and the period of this phase difference is normalized by the period of the internal (second) clock signal to obtain phase difference information. The amount of delay of the reference frame signal is determined according to the phase difference information, and the delayed reference frame signal is used as a second frame signal (a second frame signal for timing change).

Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing the principle of the present invention. The data transfer unit 1 is equivalent to the example of FIG.
The received serial data having the respective timings of the first clock signal and the first frame signal synchronized with the first clock signal is converted into data having the respective timings of the second clock signal and the second frame signal in the device and output. It is derived as serial data.

The second clock signal has the same period as the first clock signal but is asynchronous, and the second frame signal has the same period as the first frame signal and is synchronized with the second clock signal. .

The phase difference detecting section 2 includes a first frame signal a and a reference frame signal in the apparatus (one having the same period as the first and second frame signals and being synchronized with the second clock signal). B) detect the phase difference with b. The detected phase difference signal c is input to the normalized phase difference information generation unit 3, and the period of the phase difference is normalized to the cycle of the second clock signal and output as normalized phase information.

The normalized phase information e standardized and displayed at the cycle of the second clock signal is input to the timing delay unit 4. The timing delay unit 4 delays the reference frame signal “b” by a time corresponding to the normalized phase information “e”, and
It is derived as a frame signal f, and this second frame signal f is used as a frame signal in the apparatus.

FIG. 2 is a block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. FIG. 3 shows an example of a timing waveform of each signal in FIG.
An embodiment of the present invention will be described in detail with reference to FIGS.

First, the frame timing delay section 4 selects a shifter 41 for sequentially shifting the reference frame signal b in synchronization with the second clock signal, and selects each shift output of the shifter 41 in accordance with the normalized phase difference information e. And a selector 42 which is derived as a second frame signal f.

The phase difference detector 2 detects a phase difference c between the first frame signal a and the reference frame signal b, and supplies the phase difference c to a normalized phase difference information generator 3. In the timing chart of FIG. 3, the partial time axes of these frame signals a and b are enlarged and shown as a ′ and b ′, and each of the timing signals indicated by the broken lines b ′ is the second clock of the shifter 41. This is an output waveform obtained by sequentially shifting the frame signal b by a signal.

The normalized phase difference information generating section 3 uses a phase difference c as a window for normalization, and passes a second clock signal within the normalized window to the next stage counter 32 to form a phase difference pulsing section (gate). 3), so that the gate output d by the phase difference pulsing section 31 has a waveform as shown in FIG. The counter 32 counts the gate output pulse d,
A value obtained by adding +1 to this count value is output to the latch unit 32 of the next stage.

The latch section 32 latches the output (count value + 1) of the counter 32 at the end of the phase difference c (rising section in FIG. 3). Accordingly, the period of the phase difference c is the phase difference information expressed by being normalized by the cycle of the second clock signal. In the example of the timing of FIG. 3, the period of the phase difference c is the cycle of the second clock signal. Using T, T × (8+
1) = 9 × T.

The normalized phase difference information e (9 × T) is a selection control signal for the selector 42, and
The reference frame signal delayed by 9 × T by 1 is selected by the selector 42 and used as the second frame signal f.

By doing so, the frame signal closest to the timing of the first frame signal within one to two clock delays among the frame signals shifted by the shifter 41 is selected, and the second frame signal of the data transfer circuit 1 is selected. Since the timing is f, the buffer in the data transfer unit 1 may have a bit capacity of up to two clocks.

The reset circuit 10 resets the counter 32 in synchronization with the first frame signal and the second clock signal.

[0031]

As described above, according to the present invention, the phase difference between the reference frame timing and the reception frame timing is normalized by the clock cycle in the device, and the timing difference between the reference frame and the reception frame is set accordingly. An extremely small value of 1 to 2 clocks of the internal clock can be settled, so that there is an effect that it is possible to reliably switch the frame timing with a small circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart of each unit showing the operation of the block in FIG. 2;

FIG. 4 is a block diagram showing an example of a conventional frame timing transfer circuit.

FIG. 5 is a block diagram showing another example of a conventional frame timing transfer circuit.

[Description of Signs] 1 Data transfer unit 2 Phase difference detection unit 3 Normalized phase difference information generation unit 4 Frame timing delay unit 10 Reset circuit 31 Phase difference pulsation unit 32 Counter 33 Latch 41 Shifter 42 Selector

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04J 7/00 H04J 3/06

Claims (4)

(57) [Claims] 1. A first clock signal and a second clock signal having the same period as the first clock signal and a second clock signal having the same period as the first clock signal are synchronized with the timing of the first frame signal and the first frame signal synchronized with the first clock signal. A frame timing phase adjusting circuit having data transfer means for changing input data to a timing of a second frame signal having the same cycle as one frame signal, wherein the frame timing phase adjustment circuit comprises: a reference frame signal synchronized with the second clock signal; Phase difference detecting means for detecting a phase difference from the frame signal, and phase difference information for generating a period of the phase difference detected by the phase difference detecting means as phase difference information standardized by the cycle of the second clock signal. Generating means for controlling a delay of the reference frame signal in accordance with the standardized phase difference information; And a stage wherein the timing of the delayed output is used as the second frame signal of the data transfer means. 2. The phase difference information generating means outputs a counter that counts the second clock signal during the phase difference and a value corresponding to a count value of the counter as the normalized phase difference information. 2. The frame timing phase adjusting circuit according to claim 1, further comprising: 3. The phase difference information generating means according to claim 2, wherein said phase difference information generating means adds 1 to the count value of said counter and sets the added value as said normalized phase difference information. Frame timing phase adjustment circuit. 4. The apparatus according to claim 1, wherein the frame delay means shifts the reference frame signal sequentially in synchronization with the second clock signal, and selectively shifts the plurality of shift outputs in accordance with the standardized phase difference information. 4. The frame timing phase adjustment circuit according to claim 1, further comprising a selection unit for deriving the frame timing phase.