JPS63136814A - Digital delay circuit - Google Patents

Abstract

PURPOSE:To easily obtain a large quantity of delay without expanding the scale of a circuit by converting input series data into that at one-(n)th speed and optionally setting the delay quantity according to delay quantity setting information so as to store in a storage circuit. CONSTITUTION:The input series data is converted into that at one-(n)th speed by a one-(n)th counting circuit 3 and the delay quantity is made to be optionally set according to the delay quantity setting information so as to be stored in the storage circuit 8. Therefore, the large delay quantity can be easily obtained without expanding the scale of the circuit. Since the storage circuit 8 acutates at one-(n)th speed of an input clock signal, the actionenabled range of the stor age circuit 8 is expanded and the speedup of the input/output series data is enhanced. Moreover, since the storage circuit 8 needs to be constituted with a thing that actuates at low speed, it is obtained at low price, so that the cost- down can be enhanced. And by adding slight adjustment means 10 and 11 slight adjustment can be executed within the range of (i) clocks.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital delay circuit that delays a digital signal by an appropriate amount.

(Prior Art) As a conventional digital delay circuit, one shown in FIG. 3, for example, is known. What is shown in FIG. 3(A) is n
Stage shift register (200-1゜200-2.-.2
00-n), a data selection circuit 204, and a flip-flop circuit (F/F) 205. n
Stage shift register (200-1, 200-2,...
, 200-n), the first stage shift register 200-1
Input serial data 207 to be input to input clock signal 2
06, the subsequent shift registers (200-2,
.

The data selection circuit 204 selects parallel data with a delay amount specified by externally set delay amount setting information 210, converts it into serial data, and outputs the serial data via a timing F/F 205. 20
9 is sent to the outside.

This output serial data 209 is the output clock signal 208 (
The input clock signal 206 is the same as the input clock signal 206).

Moreover, the one shown in FIG. 3(B) is an n-stage FIFO (
It basically consists of a memory (300-1゜300-2.-.300-n) and an F/F 304 for retiming.

In this digital delay circuit, input serial data 306 is sent to the previous FIFO memory 300 according to the input clock signal.
-1 and sequentially to the subsequent FIFO memory.
1-'J (300-2, . . . , 300-n), and the serial data is read out from the final stage FIFO memory 300-n according to an output clock signal 307 that is different from the input clock signal 305. Output serial data 308 is sent to the outside via F/F 304.

(Problems to be Solved by the Invention) The conventional digital delay circuit described above has the following problems.

That is, a digital delay circuit using several stages of shift registers is effective for high-speed serial data processing and systems that require a small amount of delay. However, when trying to obtain a large amount of delay, the circuit scale becomes large.

Furthermore, in a digital delay circuit using FIFO memories, a large amount of delay can be obtained by connecting several stages of FIFO memories with large storage capacities in series. However, F.I.
Since the FO memory is a type of asynchronous buffer memory in which input and output are completely independent, the amount of delay cannot be set arbitrarily.

Furthermore, although FIFO memories that operate at high speed have become relatively easily available in recent years, they are still expensive, which increases costs.

The present invention was developed in view of these conventional problems, and its purpose is to obtain a large amount of delay without increasing the circuit scale, and to provide high-speed data processing without using expensive memory elements. An object of the present invention is to provide a digital delay circuit that enables delay processing.

(Means for Solving the Problems) In order to achieve the above object, the digital delay circuit of the present invention has the following configuration.

That is, the digital delay circuit of the present invention includes a serial-to-parallel conversion circuit that converts input serial data into n pieces of parallel data with different phases per clock according to an input clock signal synchronized with the input serial data; a 1/n counting circuit that divides the frequency by n; a latch circuit that latches and outputs the nu parallel data in the same phase using a 1/n latch signal based on the 1/n clock signal output from the 1/n counting circuit; a memory circuit; the n
An address signal for storing and reading out the n parallel data in one address of the storage circuit is generated in accordance with the 1/n clock signal, and the n address signal generating means for appropriately providing a time difference between write timing and read timing for the parallel data;
Converting the n pieces of parallel data read from the storage circuit into serial data having the same bit arrangement as the input serial data according to the input clock signal, and sending it to a fine adjustment means or outputting it. A digital delay circuit characterized by comprising: a parallel-to-serial conversion circuit that performs either one of outputting directly as serial data; and;

Further, the fine adjustment means includes a shift register circuit having n tap outputs having different phases per clock and sequentially shifting the output of the parallel-to-serial converter circuit per bit according to the input clock signal; and the delay amount. and a data selection circuit that selects one of the n tap outputs as output serial data based on setting information.

(Function) Next, we will explain the function of the digital delay circuit of the present invention having the above configuration.The serial/parallel conversion circuit converts input serial data into l clocks with different phases according to an input clock signal synchronized with the input serial data. It converts it into parallel data and sends it to the latch circuit.

The latch circuit latches the n pieces of parallel data in phase using a 1/n latch signal based on the 1/n clock signal output from the 1/n counting circuit, and sends it to the storage circuit.

The address signal generating means generates an address signal for storing the n pieces of parallel data related to the latch output of the latch circuit in one address of the storage circuit and reading it therefrom in accordance with the 1/n clock signal. However, at this time, an address signal is generated by giving an appropriate time difference between the write timing and the read timing for the n parallel data based on the delay amount setting information related to external settings6. Assuming that there are addresses up to #10, the write address signal starts from address #6 and the read address signal starts from address #9. Then,
The amount of delay given in the memory circuit is equivalent to 7 addresses.

Specifically, the amount of delay per address is 07017
Furthermore, among n pieces of parallel data, the first parallel data is written with a delay of n clocks, and the last n-th parallel data is written without delay, so for each parallel data As you can see, the first parallel data shows the maximum delay (the amount of delay is (7n+n) clocks), and the
This means that the parallel data of indicates the minimum delay (the amount of delay is 7n clocks).

Next, the parallel-to-serial conversion circuit converts the n pieces of parallel data read from the storage circuit into serial data having the same bit arrangement as the input serial data according to the input clock signal, and sends the serial data.

Specifically, the first parallel data is converted to first serial data without delay, the second parallel data is converted to second serial data with a delay of one clock, and so on. The n parallel data is delayed by n clocks and converted into n-th serial data, and these are sequentially sent out serially. Then, the output serial data has the same bit arrangement as the input serial data, and the amount of delay with respect to the input serial data is 7n+n=8n clocks in the above example.

In other words, when the output of the parallel-to-serial conversion circuit is used as output serial data, the amount of delay obtained is a discrete value in units of 07017 minutes. Therefore, when adjusting the delay amount within the range of 07017 minutes, the fine adjustment means is used as follows.

First, the shift register circuit sequentially shifts the output of the parallel-to-serial conversion circuit by 1 bit in accordance with the input clock signal, and at this time provides n tap outputs with different phases per clock to the data selection circuit. . In other words,
In addition to the delay amount of 8n clocks, a delay can be added within the range of 1 clock to 02077 minutes, and fine adjustment can be made within the range of 8n to 9n.

Next, the data selection circuit selects one of the n tap outputs as output serial data based on the delay amount setting information. As a result, the output series data obtained is 8
An arbitrary delay within the range of n clock minutes to 9n clock minutes is added.

As described above, according to the digital delay circuit of the present invention,
Input serial data is converted to a speed of 1/n, and the delay amount is arbitrarily set according to the delay amount setting information and stored in the memory circuit, so a large delay amount can be easily set without increasing the circuit size. Obtainable. Further, since the memory circuit only needs to operate at a speed of 1/n of the input clock signal, the operable range of the memory circuit is expanded, and the speed of input/output serial data can be increased. Furthermore, since the memory circuit only needs to operate at low speed, it can be obtained at low cost and the cost can be reduced. In addition, according to the present invention, there is an advantage that by adding a fine adjustment means, fine adjustment can be made within a range of 02077 minutes.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
The figure shows a digital delay circuit according to an embodiment of the present invention, and FIG. 2 shows the operation of each part.

This digital delay circuit includes a serial-to-parallel conversion circuit 1, a latch circuit 2, a 1/n counting circuit 3, a timing decoder circuit 4, an address counting circuit 5 and an adder circuit 6, which are address signal generating means, and an address selection circuit. Circuit 7 and
A memory circuit 8, a parallel-to-serial conversion circuit 9, a shift register circuit 10 serving as fine adjustment means, and a data selection circuit 11,
Flip-flop circuit (F/F) 12 for retiming
and a flip-flop circuit (F
/F) 13 and a power-on detection circuit 14 as an example of forming an initial state of operation.

Input serial data 20 (FIG. 2(A)) is input to the serial/parallel conversion circuit 1 and the data selection circuit 11. In addition, the input clock signal 21 (Figure 2 (b)) is the input serial data 2
Synchronized with 0, serial-to-parallel conversion circuit 1.1/n counting circuit 3, parallel-to-serial conversion circuit 9, shift register circuit 10
, are input to the data selection circuit 11 and the F/F 12, and are sent to the outside as an output clock signal 28.

The 1/n counting circuit 3 divides the frequency of the input clock signal 21 by n and supplies the resulting 1/n clock signal 22 (FIG. 2 (C) shows the case where n=8) to the address counting circuit 5. Various 1/n clock signals having different phases, including the 1/n clock signal 22, are sent to the timing decoder circuit 4.

The timing decoder circuit 4 receives the output of the 1/n counting circuit 3, forms various control signals for timing control, and performs read/write (R/W>timing signal 23).
(See Figure 2) for the latch circuit 2 and address selection circuit 7.
The write permission signal 24 (FIG. 2 (g)) is sent to the memory circuit 8, the 1/n latch signal 25 (FIG. 2 (d)) is sent to the latch circuit 2, and the 1/n latch signal 26 (second Figure (d))
are supplied to the parallel-to-serial conversion circuit 9, respectively.

The serial-to-parallel conversion circuit 1 operates according to the input clock signal 21, and converts the input serial data 20 into n pieces of parallel data 33a.
For example, as shown in Figure 2 (a) and (b), one bit corresponds to one clock, and if n = 8, the data is sequentially converted to 0 and sent to the latch circuit 2. The 7th bit to the 14th bit is the first parallel data, the 1st bit to the 8th bit is the 2nd parallel data, and the 7th bit to the 14th bit is the 8th parallel data.
parallel data are formed with a delay of one clock.

The latch circuit 2 has a 1/n latch signal 25 (see Fig. 2).
D) The n pieces of parallel data 33a are each latched at the timing of (2)), that is, the n pieces of parallel data 33a are made in phase, and then the R/W timing signal 23 (FIG. 2 (f))
n pieces of parallel data 33b having the same phase are output to the storage circuit 8 during the period in which the data 33b indicates "write". FIG. 2(E) shows eight pieces of parallel data that are written in the memory circuit 8 and read out after an appropriate amount of time, ignoring the time difference. For example, in the first parallel data, the data is written at 8-bit intervals. # (0-8), data #0, data #8
Data # (0-8) is based on the 8 bits from bits 0-8 to bits 0-1 before the first bit, and data #0 is based on bits 0 to 7. Based on 8 bits. Similarly, in the eighth parallel data, data #(0-1), data #7, data #1
5, and data #(0-1>) is based on 8 bits from 0-1st bit to 6th bit, and data #7
is based on 8 bits from the 7th bit to the 14th bit. Then, data # (0-8) ~ data # (0
-1) are the 1/n latch signal 25 at the timing position of the 7th bit, and the eight parallel data of data #0 to data #7 are the 1/n latch signal 25 at the timing position of the 15th bit. /n latch signal 25, respectively, and output to the memory circuit 8.

The address counting circuit 5 receives a 1/n clock signal 22 (
The required counting operation is performed according to FIG. 2 (b)), and each address signal from the first address to the last address of the memory circuit 8 is repeatedly generated, and the output 34 (in this embodiment, it is a read address signal) is output to the address selection circuit 7 and the addition circuit 6. Further, the adder circuit 6 adds the read address signal 34 and delay amount setting information 29 that is externally set, for example, by a digital switch, and forms an address signal indicating an address different from the address indicated by the read address signal 34. Then, it outputs it as a write address signal 35 to the address selection circuit 7. For example, as the address of the memory circuit 8, address #1 to address #
If there are up to 20 addresses, and if the read address signal 34 sequentially specifies each address starting from address #1 and ending with address #20 and repeating this, then the write address signal 35 is generated starting from address #10. .

In short, this address signal generating means writes the n pieces of parallel data into the storage circuit 8.

When reading, an appropriate time difference is given between the write timing and the read timing for the n pieces of parallel data based on the delay amount setting information 29 related to external settings. Therefore, in the above example, the output 34 of the address counting circuit 5 may be used as a write address signal, and the output 35 of the adder circuit 6 may be used as a read address signal, and the adder circuit 6 can be replaced with a subtracter circuit.

The address selection circuit 7 selects, for example, the output 35 of the adder circuit 6 as the write/read address signal 36 to be output to the memory circuit 8 when the R/W timing signal 23 indicates "write"; Further, when indicating "read", the output 34 of the address counting circuit 7 is selected as the read address signal. As a result, the address signal 36 becomes a write address signal in the first half cycle of the 1/n clock signal, becomes a read address signal in the second half cycle, and this process is repeated, as shown in FIG. 2 (H), for example. .

In the memory circuit 8, writing is performed using the write enable signal 24 (FIG. 2(G)) provided from the timing decoder circuit 24 during the generation period of the write address signal 35, and this writing and reading are performed alternately. In the above example, if the write address signal 35 specifies address #10, the read address specified by the read address signal 34 that follows the write address signal 35 specifying address #10 will be address #1. . Therefore, for example, the amount of delay until 8 pieces of parallel data (for example, data #0 to data #7) written to address #10 are read is 80 clocks because the delay per address is 8 clocks. This means the amount of delay in minutes. By the way, as mentioned above, the first parallel data (i.e., data #0) is written with a delay of 8 clocks, and the eighth parallel data (i.e., data #0) is written with a delay of 8 clocks.
7) is written without delay, the eight parallel data 33 (Fig. 2 (e)) read from the storage circuit 8 and sent to the parallel-to-serial conversion circuit 9 are divided into eight steps from 88 clocks to 80 clocks. The delay will be added.

In the serial/parallel conversion circuit 9, eight pieces of parallel data 33 (Fig. 2 (D)) are converted by the 1/n latch signal 26 (Fig. 2 (D)).
e))), converts the first parallel data (for example, data #o) into first serial data (0th bit to 7th bit) without delay, and then
parallel data (for example, data #1) is converted into second serial data (from the first bit to the eighth bit) with a delay of one clock, and then the eighth parallel data (for example, data #7) is converted into second serial data (from the first bit to the eighth bit). ) as the eighth serial data (from the 7th bit to the 1st
4 bits) with a delay of 8 clocks, and sequentially sends them serially to the shift register circuit 10. As a result, the serial data input to the shift register circuit 10 has the same bit arrangement as the input serial data 20 (FIG. 2 (a)), and is delayed by 88 clocks in the above example with respect to the input serial data 20. Become.

The shift register circuit 10 is provided with n types of taps, such as a first tap that takes out a delayed output of one clock, a second tap that takes out a delayed output of two clocks, and a second tap that takes out a delayed output of two clocks.
Similarly, there is an 8th tap that takes out the delayed output for 8 clocks, and each tap output 33c (these are also 8 clocks).
parallel data) is sent to the data selection circuit 11.

Therefore, the output mode of this shift register circuit 10 is similar to the output mode of the serial-to-parallel conversion circuit 1. In other words,
Considering that the amount of delay added by the memory circuit 8 is 72 n clocks per address, this shift register circuit 10 attempts to further add a delay amount of 2 minutes or less by n clocks.
It can be said that this is a circuit for the purpose of fine adjustment.

In addition to the eight tap outputs 33c on the signal input side, the data selection circuit 11 directly receives the input serial data 20 in this embodiment, and selects one of the nine tap outputs on the control input side. The data is selected according to the content of the delay amount setting information 29 given to the delay amount setting information 29, and is sent to the outside as output serial data 27 via the retiming F/F 12. Here, in this data selection circuit 11, when selecting the input serial data 20 to be directly input as the output serial data 27, the input serial data 20 is immediately outputted without delay.

Note that a delay of one clock is expected in the retiming F/F 12, but the main function of this F/F 12 is timing control and the like.

By the way, the address signal generating means (consisting of an address counting circuit 5 and an adder circuit 6 in this embodiment) generates an address signal for accessing all addresses in the memory circuit 8, and writes written data according to its write timing. Since the data is read out at a timing different from that, it is conceivable that undesired arbitrary data may be output from the storage circuit 8 in the initial stage of operation after reset.

Therefore, in this embodiment, a power-on detection circuit 14 is provided as a reset signal generating means, and the address counting circuit 5 and F/F 13 are reset by the power-on detection signal 32, and the address counting circuit 5 is set to an initial value. While starting the counting operation from
The output inhibit signal 30 sent to the shift register circuit 10 and F/F 12 is set to "1" to inhibit the operation of these circuits. Then, the address counting circuit 5 is connected to the memory circuit 8.
The F/F 13 is set with a count-up signal 31 indicating that the count up to the final address has been counted, and the output prohibition signal 30 is set to "0" to permit each circuit to start its circuit operation. It is. Since only the count-up signal 31 is then input to the F/F 13, the output prohibition signal 30 never becomes "1".

(Effects of the Invention) As detailed above, according to the digital delay circuit of the present invention, input serial data is converted to a speed of 1/n, and the delay amount can be arbitrarily set and stored according to the delay amount setting information. Since it is stored in the circuit, a large amount of delay can be easily obtained without increasing the circuit scale. In addition, since the memory circuit only needs to operate at a speed of 1/n of the input clock signal, the operable range of the memory circuit is expanded.
The speed of input/output serial data can be increased. Furthermore, since the memory circuit only needs to operate at low speed, it can be obtained at low cost and the cost can be reduced. Additionally, according to the invention:
By adding a fine adjustment means, there is an advantage that fine adjustment can be made within the range of 12 minutes per n chrome.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a digital delay circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the circuit shown in FIG. 1, and FIG. 3 is a configuration example of a conventional digital delay circuit. It is a block diagram. 1...Serial-to-parallel conversion circuit, 2...Latch circuit, 3...1/n counting circuit, 4...
...Timing decoder circuit, 5...Address counting circuit, 6...Addition circuit, 7...
...address selection circuit, 8...memory circuit,
9...Parallel-serial conversion circuit, 10...Shift register circuit, 11...Data selection circuit, 12.13...Flip-flop circuit,
20... Input serial data, 21...
・Input clock signal, 22...1/n clock signal, 23...R/W timing signal,
24...Writing permission signal, 25.26...
...1/n latch signal, 27... Output serial data, 28... Output clock signal, 2
9... Delay amount setting information, 30... Output prohibition signal, 31... Count up signal,
32...Power-on detection signal, 33a, 33b
. 33c...n parallel data, 34...
...Read address signal, 35...Write address signal, 36...Write/read address signal, 200-1 to 200-n...
...Shift register circuit, 204...Data selection circuit, 205...Flip-flop circuit,
206... Input clock signal, 207...
...Input serial data, 208...Output clock signal, 209...Output serial data, 2
10...Delay amount setting information, 300-1 to 300
-n...---FIFO memory, 304...
Flip-flop circuit, 305... Input clock signal, 306... Input serial data, 307
...Output clock signal, 308...
Output serial data.

Claims (4)

[Claims] (1) A serial-to-parallel conversion circuit that converts input serial data into n pieces of parallel data with different phases per clock according to an input clock signal synchronized with the input serial data; 1/n that divides the input clock signal by n; Counting circuit; said 1/n
1/n based on the 1/n clock signal output by the counting circuit
a latch circuit that latches and outputs the n parallel data in phase using a latch signal; a memory circuit;
An address signal for storing and reading out the n parallel data in one address of the storage circuit is generated according to the 1/n clock signal, and the n parallel data is generated based on delay amount setting information related to external setting. address signal generating means for appropriately providing a time difference between write timing and read timing for the parallel data;
Converting the n pieces of parallel data read from the storage circuit into serial data having the same bit arrangement as the input serial data according to the input clock signal, and sending it to a fine adjustment means or outputting it. 1. A digital delay circuit comprising: a parallel-to-serial conversion circuit that performs either one of outputting directly as serial data; and; (2) The fine adjustment means has n different phases for one clock.
a shift register circuit having n tap outputs and sequentially shifting the output of the parallel-to-serial conversion circuit by 1 bit according to the input clock signal; one of the n tap outputs based on the delay amount setting information; 2. The digital delay circuit according to claim 1, further comprising: a data selection circuit for selecting output serial data. (3) The output operation of at least the parallel-to-serial conversion circuit is prohibited during a predetermined period until the final address of the memory circuit is accessed in the initial stage of operation. A digital delay circuit according to range (1). (4) The data selection circuit receives the input serial data directly in addition to the n tap outputs, and delays the input serial data when the input serial data is selected based on the delay amount setting information. 2. The digital delay circuit according to claim 2, wherein the digital delay circuit outputs as output serial data without any delay.