JP3381284B2 - Parameter writing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parameter writing device suitable for use in electronic musical instruments. 2. Description of the Related Art FIGS. 3 and 4 show a conventional parameter writing device. The parameter writing device shown in FIG.
It is mainly used as an interface between sound sources of electronic musical instruments. In the figure, 32 is a memory system,
It comprises a ROM (Read Only Memory) and a RAM (Random Access Memory). A program for operating the parameter writing device is stored in the ROM of the memory system 32, and various calculation results are readable and writable in the RAM of the memory system 32. A CPU (Central Processing Unit) 31 reads a program from a ROM (Read Only Memory) of a memory system 32 and sends the program to various parts of the device via a data bus BUS4 which is a transmission path for various signals. Send an operation command. Reference numeral 33 denotes an operator group, which includes a keyboard and various switches (a tone setting switch, a volume setting switch, a portamento bar, and the like). [0004] Next, a control unit 34 outputs a channel clock C34 of a predetermined cycle to the musical tone waveform generating unit 36, and based on a data value of a control signal C33 supplied from the CPU 31 via the data bus BUS4. , A control signal C32 of “1” or “0” is output to the parameter register 35. For example, when the control signal C33 is
When a write command to the parameter register 35 is indicated, “1” is output to the parameter register 35 as a control signal C32. Next, a parameter register 35 temporarily holds a signal C31 (a parameter representing tone color data and volume data of an electronic musical instrument) supplied via the bus BUS4 in accordance with the value of the above-mentioned control signal C32. I do. The parameter register 35 can individually hold data for the number of sounding channels of the musical tone waveform generator 36, which will be described later, for each parameter type (for tone data for tone data, for volume data for volume data). ) Are provided. FIG. 4 shows a detailed configuration of the parameter register 35. In the figure, reference numeral 41 denotes a selector, which outputs the signal value of the signal C31 as the signal C41 when the value of the signal C32 supplied to the S control terminal is "1".
When the value of 32 is "0", an output signal C35 of the shift register 42 composed of N stages of registers (N: the number of sounding channels of the musical tone waveform generator 36) is output as a signal C41. The shift register 42 delays the signal C41 supplied to the DI input terminal by N stages and then outputs the signal C35 from the DO output terminal.
Is output to the musical tone waveform generator 36 (see FIG. 3).
In this case, the delay operation in the shift register 42 is performed by the shift clock φ generated in synchronization with the channel clock C34.
Performed at the rise of ch. Thereby, for example, when the tone waveform generator 36 performs the processing of the n-th channel, the data to be used in the n-th channel is output from the shift register 42, and the shift register 42 and the tone waveform generator The unit 36 operates synchronously. The tone waveform generator 36 has a plurality of tone generation channels, and the control signal C35 supplied as described above.
The tone waveform data is synthesized in a time-division manner by a digital signal processor (DSP) or the like built in the tone waveform generator 36 in accordance with the signal value of the tone signal and the timing of the channel clock C34 (pulse signal similar to the shift clock φch). Then, the musical tone waveform data thus synthesized is output as a signal C36 to a musical tone generating unit (not shown). In the conventional parameter writing apparatus described above, since parameter data is circulated in the shift register 42 via the selector 41, a general RAM (random access memory) is used. )
As described above, it is impossible to write the data immediately by specifying the address where the above-described parameter data is to be written. Therefore, in order to change the parameters used in the n-th channel of the musical tone waveform generator 36, the data to be used in the n-th channel among the N-stage shift registers of the parameter register 35 are stored. If new parameter data is to be written to the shift register of the second stage, the following situation occurs in the worst case. That is, the k-th stage (k ≦ N−) is connected to the DI input terminal.
1), the data of the (k + 1) th stage comes to the DI input terminal if the stage is shifted by one stage by the shift clock φch immediately before the parameter data is to be written. Therefore, the timing of the k-th stage is missed. In such a case, the CPU 1 has to wait for the parameter data making one round in the shift register 42 by shifting the registers constituting the shift register 42 by N stages. In such a case, the CPU 1 eventually wastes time not performing the processing, and as a result, the speed at which the parameters are written becomes slow. Instead of using the above-described configuration using the shift register, the timing of the read / write control signal is further divided into the read / write timing for each channel using a RAM, and the address is directly specified. Some sound sources perform writing of parameters by time-division processing. However, in such a case, the structure becomes considerably complicated and a large area is required. SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and an object of the present invention is to provide a parameter writing device capable of improving a parameter writing speed without complicating a hardware structure. . According to the present invention, there is provided a parameter writing apparatus suitable for use in an electronic musical instrument, which is used for generating a musical tone waveform of the electronic musical instrument. To temporarily store various parameters
Given a cyclic shift register stages (n is an integer), and writing means for writing the various parameters in the shift register, the cyclic shift register when there is an instruction for writing the various parameters in the shift register
Circulating shift register by circulating at high speed over time
Control means for writing the various parameters to the data . According to the present invention, since the above configuration is adopted, n
The cyclic shift register of the stage (n is an integer) temporarily stores various parameters used for generating a musical tone waveform of the electronic musical instrument. The writing means writes the various parameters to the shift register. The control means causes the cyclic shift register to circulate at high speed when there is an instruction to write the various parameters to the shift register. An embodiment of the present invention will be described below with reference to the drawings. A: Configuration of Embodiment FIG. 1 is a diagram showing the configuration of a parameter writing device according to the present invention, in which the number of sound channels of the musical tone waveform generator 36 is "8". In the figure, 1 is a CPU
And a memory system 2 composed of a ROM (Read Only Memory) and a RAM (Random Access Memory)
An operation command is sent to each unit of the device according to the program read from the device. The operator 3 is composed of a keyboard, a tone switch, and the like. Reference numeral 4a denotes a shift clock (.phi.s) generating unit which generates a shift clock (.phi.s) based on a master clock signal .phi.m supplied to a DI input terminal and outputs a shift clock (.phi.s) from a DO output terminal. In technical terms, it is output to the A input terminal of the shift clock generator 4 and the tone waveform generator 36 as a channel clock C34). Reference numeral 4b denotes a high-speed shift clock (9φs) generator which generates a high-speed shift clock (9φs) based on the master clock signal φm supplied to the DI input terminal.
The O output terminal outputs the clock signal 9φs to the B input terminal of the shift clock generator 4. The shift clock generator 4 has a control terminal CONT
, The clock signal 9φs supplied to the B input terminal is output from the C output terminal as the signal SHIFTCK, and when the signal value is “0”,
The clock signal φs supplied to the A input terminal is changed to the signal SHIF
Output from the C output terminal as TCK. Reference numeral 9 denotes a timing generator, which is a control terminal CK.
, A write signal WRT, a data latch 5 described later, and a channel latch 10 described later supplied to an A input terminal and a B input terminal, respectively.
Operates based on an address signal ADD indicating which of the latch circuits is to be written. The result of this operation is represented by a signal DLCK (which becomes "1" when the write signal WRT is "1" and the address signal ADD indicates an address corresponding to the data latch 5), a signal DWRT (the above-described address signal). Only when the write parameter DATA is stored in the data latch 5 as determined from ADD, the control signal SHIFTCONT (when the write parameter DATA is stored in the data latch 5 as determined from the address signal ADD described above). Only if "1"
) And a signal CHLCK (which becomes “1” when the write signal WRT is “1” and the address signal ADD indicates an address corresponding to the channel latch 10), respectively, as output terminals O1, O2, Output from O3 and O4. Next, when the value of the signal DLCK supplied to the control terminal CK is "1", the data latch 5 outputs the input terminal DI.
, And outputs the value from the DO output terminal. Reference numeral 6 denotes a selector, and the output value of the AND gate 13 supplied to the control terminal S is "1".
In the case of (1), the signal value supplied to the A input terminal is output to the shift register 7, and when the output value is “0”, the signal value supplied to the B input terminal is output to the shift register 7. The shift register 7 holds data for eight channels (write parameter DATA) and operates based on the above-mentioned clock signal SHIFTCK. This shift register 7 has registers SR0 to S
R7, the signal value supplied from the DO output terminal of the selector 6 is first stored in the register SR7 as stored data, and the stored data is stored in the registers SR6, SR5,..., In response to the rise of the signal SHIFTCK.
Shift to the register SR0 in order. The signal output from the register SR0 is output to a data latch 8 described later, and when the signal value supplied to the control terminal S of the selector 6 is "0", the signal is output to the register 6 via the selector 6. Returned to SR7. The data latch 8 stores the signal value supplied from the shift register 7 at the timing of the rise of the clock signal φs and outputs the signal value to the musical tone waveform generator 36. Numeral 10 is a channel latch, and the value of the signal CHLCK supplied from the timing generator 9 is "1".
, The channel data CHD of the data bus BUS1
ATA is held, and the value of the channel data CHDATA is output to the comparator 11. The comparator 11 compares the signal values supplied to the input terminal A and the input terminal B, and outputs “1” to the AND gate 13 when the comparison results are equal. , And outputs “0” to the AND gate 13. Reference numeral 12 denotes a 3-bit channel counter, which is a signal SHI supplied from the shift clock generator 4.
By counting the number of rising pulses of FTCK, which channel is being processed is counted. In this case, the channel number to be counted is the number of the channel of the data stored in the register SR0.
"7" is counted. This is because the parameter writing device shown in FIG. 1 performs 8-channel time division processing. B: Operation of Embodiment Next, the operation of the above-described embodiment will be described with reference to FIG. First, it is assumed that the output value or signal value of each logic element at time t0 is as follows (see FIG. 2). Channel counter 12 = 1 (channel number of data stored in register SR0) Data latch 10 = 6 Register SR0 = Selector 6 = Data register SR7 of first channel = Data latch 8 = 0Data of channel 0 , Data latch 10 has address signal ADD =
It is assumed that "6" is stored in advance before time t0 by transmitting the "address corresponding to the data latch 10", the channel data CHDATA = "6", and the write signal WRT from the CPU 1. Next, at time t1, the shift clock generator 4 outputs the clock signal φs as the signal SHIFTCK. As a result, the channel counter 12 increments the above-mentioned set value “1” and outputs “2”. The data in the loop formed by the shift register 7 and the selector 6 is shifted by one clock, and the output values of the register SR0 and the selector 6 become the data values of the second channel.
Becomes the data value of the first channel newly stored in the register SR7. Next, after the time t2 has elapsed, the CPU 1 sends a write command. As a result, the write signal WRT included in the control bus BUS3 becomes “1”. Then, the timing generator 9 outputs the write signal WR
When T is supplied to the A input terminal, at time t3 (see FIG. 2) based on the master clock φm, "1" is output from the O1 output terminal as a signal DLCK. At the same time as the value of the signal DLCK supplied to the CK control terminal of the data latch 5 becomes “1”, the data latch 5
, The new write parameter DATA of the sixth channel supplied to the selector 6 is latched, and A of the selector 6 is
Output to input terminal. Note that the signal DLCK becomes "1" for one cycle of the clock signal 9 [phi] s, and becomes "0" at time t4. The timing generator 9 outputs "1" from the O4 output terminal as a channel lock signal CHLCK based on the above-mentioned write signal WRT. As a result, the channel latch 10 sets “channel data CHD
ATA = 6 ”is input from the DI input terminal, and this signal value“ 6 ”is output to the comparator 11 from the DO output terminal. Next, at time t5, the timing generator 9 outputs "1" from the O2 output terminal and the O3 output terminal to the signal DW.
Output as RT and signal SHIFTCONT. The signal DWRT and the signal SHIFTCONT have a time "1" for one cycle of the clock signal φs. By the way, at time t5, the CON of the shift clock
When the signal value supplied to the T control terminal becomes "1", the shift clock generation unit 4 outputs the clock signal 9φs supplied to the B input terminal as a signal SHIFTCK from the C output terminal to the channel counter 12 and the shift register 7. . The output value of the channel counter 12 becomes "3" based on the rise of the clock signal 9φs. In addition, since the data is shifted by one clock in the loop constituted by the shift register 7 and the selector 6, the output values of the register SR0 and the selector 6 become the data values of the third channel. Stores the data of the second channel stored in the register SR0. Next, at time t6, the shift clock generator 4 again outputs the clock signal 9φs to the signal SHIFTCK.
Output as Thereby, the channel counter 12
Is "4". Further, since the data is shifted by one clock in the loop constituted by the shift register 7 and the selector 6, the output values of the register SR0 and the selector 6 become the data values of the fourth channel, and the register SR7 has the third channel. Is stored. On the other hand, since the data latch 8 operates based on the clock signal φs, the output value of the data latch 8 does not change with the data value of the second channel. The comparator 11 compares the value “6” supplied to the A input terminal with the signal value “4” supplied to the B input terminal. As a result, since these signal values are not equal, the output value of the comparator 11 is “0”. Next, at time t7, the shift clock generator 4 outputs the clock signal 9φs as the signal SHIFTCK. As a result, the output value of the channel counter 12 becomes “5”. Further, since data shifts by one clock in the loop constituted by the shift register 7 and the selector 6, the output values of the register SR0 and the selector 6 become the data values of the fifth channel, and
The data of the fourth channel is stored in R7. Next, at time t8, the shift clock generator 4 outputs the clock signal 9φs as the signal SHIFTCK. As a result, the output value of the channel counter 12 becomes “6”. Further, since the signal value supplied to the B input terminal of the comparator 11 becomes equal to the signal value “6” supplied to the A input terminal, the comparator 11 outputs “1” to the AND gate 13 from the DO output terminal. . Since the signal value of the signal DWRT supplied from the O2 output terminal of the timing generator 9 to the AND gate 13 is “1”, the output value of the comparator 11 and the value of the signal DWRT are “1”. The logical product “1” of “1” is output to the S control terminal of the selector 6. The signal value “1” output from the AND gate 13 becomes a time “1” for one cycle of the clock signal 9φs. The clock signal 9φs at time t8
, The data is shifted by one clock in the loop composed of the shift register 7 and the selector 6. As a result, the output value of the register SR0 becomes the data value of the sixth channel, and the data of the fifth channel is stored in the register SR7. Since the S control terminal is "1" as described above, the selector 6 transfers the new data of the sixth channel supplied to the A input terminal, that is, the write parameter DATA from the DO output terminal to the shift register. 7 is output. As described above, at time t9, the shift clock generator 4 outputs the clock signal 9φs to the signal SHI.
Output as FTCK. As a result, the write parameter DATA is written to the register SR7 as new data of the sixth channel. At the same time, the data in the loop constituted by the shift register 7 and the selector 6 is shifted by one clock, and the output values of the register SR0 and the selector 6 become the data values of the seventh channel.
The value of the new write parameter DATA of the sixth channel written as described above is stored in the register SR7. The output value of the channel counter 12 is "7". The output value of the comparator 11 becomes “0”, and the signal value supplied to the S control terminal of the selector 6 becomes “0”.
become. Therefore, the selector 6 outputs the signal value supplied to the B input terminal. Thereafter, from time t10 to time t13, the clock generator 4 outputs the clock signal 9φs to the signal SHIFTTC.
When K is repeatedly output four times, data in the loop composed of the selector 6 and the shift register 7 is shifted in order by one clock in synchronization with the rise of the clock signal 9φs. The output value of the channel counter 12 becomes "3" after "0" reset. Next, at time t14, the control signal SHIFTCONT supplied from the timing generator 9 changes from "1" to "0". This is because one cycle of the clock signal φs has elapsed from time t5. For this reason, the shift clock generator 4 again outputs the clock signal φs supplied to the A input terminal to the signal SHIFTCK.
From the C output terminal. Then, the channel counter 12 outputs “4”, and the data is shifted by one clock in the loop constituted by the shift register 7 and the shift register 6, so that the register SR0 and the selector 6
Becomes the data value of the fourth channel, and the register SR7 stores the data value of the third channel. As described above, in this embodiment, the CPU
Musical tone waveform generator 3 for updating parameter data from 1
When the channel data indicating the tone generation channel No. 6 is transmitted and new parameter data is transmitted, the shift register 7 circulates at a high speed and the new parameter data is written into the shift register 7, so that the waiting time of the CPU 1 is shortened. be able to. In the above description, the case where data is written to the sixth channel has been described. However, even when the write parameter DATA of another channel number is written to the other channel number, the signal WRT which is a write command from the CPU 1 is transmitted. A circuit operation is performed based on the value, and the write parameter DATA is written to a desired channel. In the high-speed clock generator 4b, in order to shorten the cycle of the clock signal φs (to increase the frequency, that is, to shorten the interval for generating the pulse signal), the cycle of the clock signal φs is The shift register 7 outputs a pulse signal having a cycle obtained by dividing the number of delay stages “8” by “9” obtained by adding “1” to the number of delay stages. However, the present invention is not limited to this.
The period of s may be a value shown in the equation. The cycle of the clock signal 9φs = the cycle of the clock signal φs / {the number of delay stages of the shift register 7 × k) +1} (where k is a natural number). 1
Writing can be performed while the channel time elapses. Also, since “+1” is used in the denominator of the equation,
At the rise of the normal clock at the next timing, the operation of each part of the circuit can be matched. In the above description, the clock signal is generated at the cycle described in the equation. However, it is sufficient that the channels have the same value within the cycle of the clock signal φs. And when the clock signal is generated (kn + 1) times,
The clock signal may be returned to the normal clock signal φs. In this embodiment, one type of parameter is stored in the shift register 7. However, in other words, a plurality of parameter writing devices having the configuration shown in FIG. 1 are provided in one device. May be. As described above, according to the present invention, an n-stage (n is an integer) cyclic shift register for temporarily storing various parameters used for generating a musical tone waveform of an electronic musical instrument. And write means for writing various parameters to the shift register, and control means for circulating the cyclic shift register at high speed when there is an instruction to write the various parameters to the shift register. The speed at which parameters are written can be improved without requiring

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a configuration of a parameter writing device according to an embodiment of the present invention. FIG. 2 is a timing chart of the parameter writing device according to one embodiment of the present invention. FIG. 3 is a diagram showing a configuration of a conventional parameter writing device. FIG. 4 is a diagram showing a configuration of a conventional parameter register 35; [Description of Signs] 1... CPU (control means), 4... Shift clock generator (control means, writing means), 5... Data latch (writing means), 6.
7: Shift register (circular shift register), SR
0 to SR7 register (circular shift register), φ
m: master clock, φs, 9φs: clock signal,
DATA: Write parameter, WRT: Write signal, SHIFTCONT: Control signal, CHDATA
... channel data, SHIFTCK ... signal.

Claims (1)

(57) Claims 1. A parameter writing apparatus suitable for use in an electronic musical instrument, comprising: an n-stage (n: n) for temporarily storing various parameters used for generating a musical tone waveform of the electronic musical instrument; a circulation shift register integer), said writing means for writing various parameters to the shift register, the circulating shift register for a predetermined time when there is a command for writing the various parameters in the shift register
High-speed circulation over the cyclic shift register
Control means for writing the various parameters; and a parameter writing device.