JPH07209389A - High-speed pattern generator - Google Patents

Abstract

PURPOSE:To provide a high-speed pattern generator wherein the generation of a test pattern is made high-speed. CONSTITUTION:A plurality of buffer memories 611 to 614 are provided at the rear stage of a pattern generator 2. An output pattern 610 of the pattern generator 2 is input to each input end. A control circuit 641 for controlling an address signal and a writing/reading signal of each buffer memory 611 to 614 provided. A counter 642 for counting a pattern number is provided. A multiplexer 62 for multiplexing and taking out each output of the buffer memories 611 to 614 is provided. In addition, a plurality of banks are provided in accordance with the above constitution and another multiplexer for selecting each output is set. A bank control circuit is provided. As the result, the high-speed pattern generator is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed pattern generator which speeds up test pattern generation in a test pattern generator mounted on a semiconductor test apparatus.

[0002]

2. Description of the Related Art Test patterns used in semiconductor test equipment are generally high speed. In recent years, with the development of devices under test and memory devices, it has been required to speed up pattern generators.

FIG. 3 shows a configuration example of a conventional memory test device. The memory test apparatus for testing the memory under test 4 is composed of a timing generator 1, a pattern generator 2, a waveform shaper 3 and a logical comparator 5. According to the reference clock generated by the timing generator 1, the pattern generator 2 outputs an address signal, a test data signal and a control signal to be given to the memory under test 4. Each of these signals is applied to the waveform shaper 3, where it is shaped into a waveform required for the test and applied to the memory under test 4. The memory under test 4 writes the test data to the address and controls the reading by the control signal. The read data read from the memory under test 4 is given to the logical comparator 5, where it is compared with the expected value data output from the pattern generator 2, and the result of the match or mismatch results in the memory under test. Pass / fail judgment is performed.

FIG. 4 shows an example of the internal structure of the pattern generator 2. The pattern generator 2 includes an address generator 22, an address converter 25 that divides an address into X and Y, and extracts the divided address.
It is composed of a test pattern data generator 23, a control signal generator 24, and a sequence controller 21 for controlling them.

The sequence control unit 21 controls an instruction memory 201 in which a series of instructions for generating a pattern is stored, a program counter 203 for designating its address, and the program counter 203 based on the instruction from the instruction memory 201. The program counter control 202 is configured to operate. The memory area of each address of the instruction memory 201 includes a sequence control instruction area, an address operation instruction area, a data operation instruction area, and a control signal generation instruction area.

With this configuration, the program counter 20
The instruction memory 201 is accessed by the address output from the memory 3, and the contents of the instruction memory 201 are accessed by the program counter control 202 and the address generator 2, respectively.
2, test pattern data generator 23, control signal generator 2
Given to 4. The program counter control 202 decodes the read sequence control instruction, increments and holds the program counter 203, or loads the read address, and generates a new address to generate a sequence. .

As described above, in the conventional pattern generator,
The instruction memory 201 is accessed by the address output from the program counter 203, and the content of the instruction memory 201 determines the next pattern to be generated.
The program counter 203 is controlled by the program counter control 202. The program counter control 202 is the instruction memory 20.
Decode the sequence control instruction read from 1,
It controls the operation of the next program counter. Since it is difficult to increase the operation speed such as instruction memory access and sequence control instruction decoding from the memory during one cycle from the output of the address of the program counter to the determination of the operation of the next program counter, a high-speed pattern Difficult to occur.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional technique, in which the generation of a test pattern in a test pattern generator is accelerated. A high speed pattern generator is provided.

[0009]

[Means for Solving the Problems]

(Solution of Claim 1) A plurality of buffer memories (611, 612, 613, 61) are provided at the subsequent stage of the pattern generator 2.
4) is provided. Then, the output pattern 601 of the pattern generator 2 is input to each input terminal of the buffer memory. Then, the control circuit 6 for controlling the address signal and the write / read signal of each buffer memory.
41 is provided. Then, a counter 642 for counting the number of patterns for writing and reading is provided. Then, a multiplexer 62 that multiplexes and takes out each output of the buffer memories (611, 612, 613, 614) is provided. The bank 60 having the above structure is provided to form a high speed pattern generator.

(Solution of Claim 2) Pattern generator 2
In the subsequent stage, a plurality of buffer memories (611, 612,
613, 614) are provided. Then, the output pattern 601 of the pattern generator 2 is input to each input terminal of the buffer memory. Then, a control circuit 641 for controlling the address signal and the write / read signal of each buffer memory is provided. Then, a counter 642 for counting the number of patterns for writing and reading is provided. Then, the buffer memory (611, 612, 61
A multiplexer 62 for multiplexing and taking out the respective outputs (3, 614) is provided. The bank (71, 7) having the above configuration
2) are provided in plural. And the bank (71, 72)
A multiplexer 74 is provided to select each of the outputs. Then, a bank control circuit 73 for controlling writing / reading of the bank (71, 72) and controlling selection of the multiplexer 74 is provided. A high-speed pattern generator is configured with the above configuration.

[0011]

According to the present invention, when a high speed pattern is generated,
The pattern generator 2 is not operated, but the counter 642 and the control circuit 641 are operated. Therefore, in this case, since the pattern generation unit is not operated when the high-speed pattern is generated, the operation speed of the program counter control 202 unit does not affect the pattern generation speed. Therefore, high-speed pattern generation is possible. This is one of the reasons why the speed can be increased. The second reason that the speed can be increased is n-fold multiplication by the multiplex operation. The multiplexer 62 and the counter 643 form a multiplexing circuit. Therefore, the data can be extracted at a speed n times faster than the change in each data. The third reason why the speed can be increased is that after the writing of the buffer memory of one bank is completed, the pattern writing to the buffer memory of the other bank is immediately started, so that the output of the buffer memory is completed. The waiting time can be shortened as compared with the case where a new pattern is written later. Therefore, when continuously performing high-speed patterns, each waiting time is shortened, and thus the test time can be shortened.

[0012]

Embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, a buffer memory unit 6 is provided between the pattern generator 2 and the waveform shaper 3. The buffer memory unit 6 is composed of a bank 60 and a multiplexer 63.

A plurality of (n) buffer memories, a multiplexer 62, and a controller 64 are provided in the bank 60. In this example, the case of n = 4 is shown. The output pattern 60 of the pattern generator 2 is commonly input to the input ends of the buffer memories (611, 612, 613, 614).
The control circuit 64 is provided at the address end of the buffer memory.
Input an address signal from 1. Each write / read (W / R) end of the buffer memory is connected to the control circuit 64.
Connect to 1.

As a preparation before starting the test, first, a pattern to be generated at a high speed is generated in advance by the pattern generator 2 at a normal speed, and this generation pattern 601 is written in each buffer memory (611, 612, 613, 614). Also, the number of patterns written in the buffer memory is counted by the counter 642 and stored.

Next, when a high speed pattern is generated, the pattern generating section 2 is not operated and the counter 642 and the control circuit 64 are operated.
1 and operate. Therefore, in this case, since the pattern generation unit is not operated when the high-speed pattern is generated, the operation speed of the program counter control 202 unit does not affect the pattern generation speed. Therefore, high-speed pattern generation is possible. This is one of the reasons why the speed can be increased.

The second reason that the speed can be increased is n-fold multiplication by the multiplex operation. The multiplexer 62 and the counter 643 form a multiplexing circuit. As shown in FIG. 5, the quadruple multiplexing circuit extracts the operation clock from the counter 643 as 2 bits and outputs the operation clock to the multiplexer 62.
Selection signal 605. The select signal multiplexes the input signals (X ₀ , X ₁ , X ₂ , X ₃ ). FIG. 6 shows an operation example of the multiplexing circuit. Input signal X
₀ data is a, input signal X ₁ data is b, input signal X
_{Assuming that} the data of ₂ is c and the data of the input signal X ₃ is d, the data can be extracted at a speed four times (generally n times) as fast as the change of each data.

FIG. 7 is a time chart showing one operation example according to the present invention. In FIG. 7, the same address signal is commonly applied to each address terminal of the buffer memories (X0, X1, X2, X3) at the time of writing. In addition, the same data signal is given to each data terminal in common. That is, in the buffer memory X0, the data a is written to the address A0, and the data a is written to the address A1.
Write data b. After that, the data is continuously written in the same manner.
Next, at the time of reading, first, the address A0 is given to the buffer memory X0. Then, A1 is given to X1, A2 is given to X2, and A3 is given to X3. Then, these data are multiplexed and taken out as the output X. In this case, as shown in FIG. 7, the data a, b, c, d are continuously extracted within one cycle. In the next cycle, the buffer memory X
For 0, an address that is "4" (generally n) ahead of the last time is given. That is, the address A4 is given. Then, A5 is given to X1, A6 is given to X2, and A7 is given to X3. And
These data are multiplexed and taken out as the output X.
In this case, the data e, f, ... Are continuously extracted as shown in FIG.

FIG. 8 is a time chart showing another operation example according to the present invention. In FIG. 8, at the time of writing, the same address signal is commonly applied to each address terminal of the buffer memories (X0, X1, X2, X3). In addition, the same data signal is given to each data terminal in common. As for the W / R terminal, writing (W) is performed in the first cycle to the buffer memory X0, and X1
Is written in the second cycle, X2 is written in the third cycle, and X3 is written in the fourth cycle. That is, as shown in FIG. 8, for the buffer memory X0, the data a is written to the address A0, for the buffer memory X1, the data b is written to the address A0, and for the buffer memory X2, the address is written. The data c is written to A0, and the data d is written to the address A0 in the buffer memory X3. Next, at the time when writing for four cycles (generally n cycles) is completed, each buffer memory (X
0, X1, X2, X3) advance to A1. After that, the data is continuously written in the same manner. Next, at the time of reading,
An address signal A0 is commonly applied to the address terminals of the buffer memories (X0, X1, X2, X3). And
These data are multiplexed and taken out as the output X.
In this case, as shown in FIG. 8, the data a, b, c, d are continuously extracted within one cycle. In the next cycle, the address is advanced by 1 to A1, and similarly, these data are multiplexed and taken out as the output X. In this case, the data e, f, ... Are continuously extracted. In this way, the data to be multiplexed may be allocated as in the example of FIG. 7 or as in the example of FIG.

A high-speed pattern which is a synergistic effect of the above-mentioned two types of speed-up is given to the waveform shaper 3 and the logical comparator 5. The counter 642 increments the number of patterns stored before the start of the test and ends the operation. A multiplexer 6 is provided between the bank 60 and the waveform shaper 3.
3 is provided to select the output pattern 601 of the conventional pattern generator 2 and the output of the multiplexer 62 from the selection signal 6
It is possible to switch and take out by 03.
This is a buffer memory (611, 612, 613,
The number of patterns that can be generated is limited by the capacity of 614), but by making it possible to select the pattern from the buffer memory and the pattern from the pattern generator, it is possible to generate the same pattern as the conventional one.

(Embodiment 2) FIG. 2 shows another embodiment according to the present invention. In this embodiment, a plurality of banks (71, 72) made up of a buffer memory are provided to shorten the waiting time required for transferring the pattern from the pattern generator 2 to the buffer memory, thereby shortening the test time. This is because in the configuration of the buffer memory unit 6 according to the first embodiment, the test is temporarily stopped, patterns are written in the buffer memory, and after writing of all patterns is completed,
The test has to be started again, which overcomes the drawback of increasing the test time due to the waiting time during the pattern transfer from the pattern generator to the buffer memory.

As shown in FIG. 2, instead of the buffer memory unit 6 in the first embodiment, a buffer memory group 7 is provided.
Are provided between the pattern generator 2 and the waveform shaper 3.
The buffer memory group 7 has a plurality of banks (generally m) similar to the bank 60 in the first embodiment.
They are provided as banks 71 and 72. Then, a bank control circuit 7 for controlling these banks (71, 72)
3 is provided. Then, a multiplexer 74 for selectively outputting the output of the bank (71, 72) is provided.

The control circuits of the banks 71 and 72 are provided with signals (Full 1, Full 2) meaning "all patterns have been written in the buffer memory". In addition, a signal (Emp1, which means that all the patterns in the buffer memory have been output) or that "the pattern has not been written yet"
Emp2) is provided.

First, a pattern is written on the bank 71 side as in the first embodiment. When all the patterns are written, the control circuit of the bank 71 outputs the Full1 signal to the bank control circuit 73. Upon receiving Full1, the bank control circuit 73 causes the bank 71 to output a pattern. After that, the presence or absence of the Emp2 signal from the bank 72 side is checked, and if there is Emp2,
The pattern to be generated next is started to be written in the bank 72.
When all the patterns in bank 71 have been output, bank 7
1 outputs the Emp1 signal to the bank control circuit 73.
When the bank control circuit 73 receives Emp1, the bank control circuit 73
It is in a standby state until the Full2 signal is output from 2. When the Full2 signal is output from the bank 72, the bank control circuit 73 causes the bank 72 to output a pattern, and starts writing the pattern to be generated next to the bank 71. The same operation is performed after all the patterns in the bank 72 have been output.

The output of the bank 71 and the output of the bank 72 are switched by outputting a select signal 701 from the bank control circuit 73 to the multiplexer 74. Also,
A multiplexer 63 is provided between the multiplexer 74 and the waveform shaper 3 as in the first embodiment, and the output pattern 601 of the conventional pattern generator 2 and the output of the multiplexer 74 are switched by the selection signal 603. It is possible to take it out.

In the configuration of the second embodiment, after the writing of the buffer memory of one bank (for example, bank 71) is completed, the pattern writing to the buffer memory of another bank (for example, bank 72) is started immediately. The waiting time can be shortened as compared with the case where a new pattern is written after the output of the buffer memory is completed. Therefore, when a high-speed pattern is continuously performed, each waiting time is shortened, and thus the test time can be shortened.

[0027]

Since the present invention is configured as described above, it has the following effects. It was possible to provide a high-speed pattern generator that speeds up the generation of test patterns in the test pattern generator.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a high speed pattern generator of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the high speed pattern generator of the present invention.

FIG. 3 is a block diagram showing an example of a conventional memory test device.

FIG. 4 is a block diagram showing an example of a conventional pattern generator.

FIG. 5 is a block diagram showing an example of a multiplexing circuit.

FIG. 6 is a time chart showing the operation of the multiplexing circuit.

FIG. 7 is a time chart showing an operation example according to the present invention.

FIG. 8 is a time chart showing another operation example according to the present invention.

[Explanation of symbols]

1 timing generator 2 pattern generator 3 waveform shaper 4 memory under test 5 logical comparator 6 buffer memory unit 7 buffer memory group 21 sequence controller 22 address generator 23 test pattern data generator 24 control signal generator 25 address conversion 60, 71, 72 Banks 62, 63, 74 Multiplexer 64 Control unit 73 Bank control circuit 201 Instruction memory 202 Program counter control 203 Program counter 611, 612, 613, 614 Buffer memory 641 Control circuit 642, 643 Counter

Claims (2)

[Claims] 1. A plurality of buffer memories (611, 612, 613, 6) are provided after the pattern generator (2).
14) is provided, the output pattern (601) of the pattern generator (2) is input to each input terminal of the buffer memory, and control is performed to control the address signal and the write / read signal of each buffer memory. A circuit (641) is provided, a counter (642) for counting the number of patterns for writing and reading is provided, and buffer memories (611, 612, 613, 614)
(62) that multiplexes and extracts each output of
And a bank (60) having the above structure is provided. 2. A plurality of buffer memories (611, 612, 613, 6) are provided after the pattern generator (2).
14) is provided, the output pattern (601) of the pattern generator (2) is input to each input terminal of the buffer memory, and control is performed to control the address signal and the write / read signal of each buffer memory. A circuit (641) is provided, a counter (642) for counting the number of patterns for writing and reading is provided, and buffer memories (611, 612, 613, 614)
(62) that multiplexes and extracts each output of
Is provided, a plurality of banks (71, 72) having the above configuration are provided, a multiplexer (74) for selecting each output of the bank (71, 72) is provided, and writing / reading of the bank (71, 72) is performed. A high-speed pattern generator characterized by comprising a bank control circuit (73) for controlling and controlling selection of the multiplexer (74), and having the above configuration.