SU993266A2 - Device for test check of electronic computer digital units - Google Patents

Description

(54) DEVICE FOR TEST CONTROL OF DIGITAL KNOTS OF ELECTRON COMPUTING MACHINES

one

The invention relates to electronic computing and can be used in the agro-equipment of automatic control and diagnosis of digital nodes.

According to the main author. St. No. 694863, a device for test control of digital computer nodes is known, comprising a serially connected storage unit for storing 51 tests, an information recording unit, a test register, a switch, a control unit, a comparison unit, a shift register, and a verifiable SO block.

A disadvantage of this device is that the load on the output elements of the tested product for all channels and for all products is the same and is determined by the size of the output value)) and the laziness of the element is NOT. Meanwhile, for a more complete inspection of the product, it is necessary to be able to control it. 2o simulate the most severe modes of operation of a product when its output is & . The cops have a maximum load, in this case, since the weekend can be

loaded on one or several elements of the product inside the tested product (feedback), it is clear that the value of the load current imitated during the test should be able to change from minimum to maximum value with a resolution equal to the current generated by one element.

The purpose of the invention is to increase the reliability of the device operation by controlling the output elements of the tested product by imitating the most severe work.

The delivered circuit is achieved by introducing into the device for testing control of digital nodes of electronic computer control machines a group of registers of load load cells and a group of drivers of load signal parameters, and the group of test register outputs are connected to the inputs of each p & gist of pear load codes, group of output terminals of which pochipvEk to the group of inputs of the corresponding forms "

The parameters of the load signal group, the output of each of which is connected and: the first input of the corresponding element AND switch, the third group & control unit of the control unit is connected to the control inputs of the load code registers of the load.

In addition, the control unit contains two AND elements, a decoder, a register, the inputs of the first and second AND elements, and the first register input are a group of inputs of the control unit, the outputs of the first and second AND elements are connected to the first and second inputs of the decoder. the first output of which is connected to the Bjopoi register input, the two groups of outputs of which are, respectively, the first and second group of outputs of the control unit, the second output of the decoder is the third group of outputs of the control unit. FIG. 1 presented the structural scheme of the proposed device; in fig. 2 is a control circuit. The device contains a storage unit 1 for storing tests, a block 2 for protecting information, a test register 3, a switch 4, a control block 5, a comparison block 6, a shift register 7, a check block 8, a group of AND-HE, two groups of AND elements 10 /) - 1Op and, a group of elements OR 12, a group of registers of load codes, rpyitp of drivers of parameters of load signals, two elements AND 15 and 16, decoder 17, register 18 of switch. The device works as follows. Checked block 8 has n contacts, each of which can be input or output. At the beginning of each test, information is stored in memory unit 1, which specifies the distribution of the input and output contacts of the tested product and the amount of load that must be provided separately for each output contact in order to test the operation of the output element in the worst mode. The information from the storage unit 1 through the recording unit 2 is recorded in the test register 3. At the beginning of the work information on the distribution of input and. the output contacts of the tested product from the register 3; the theota enters the switch control unit 5 in order to generate in the vapor-phase code the signals of the ordering by the switch, and the information defining the maximum number of elements to which the output of the test product in the binary code can be loaded comes from register 3 test registers.

The binary code of the load from the outputs of the registers enters and inputs to form lei, at the outputs of which currents are formed, the values of which depend on the binary code recorded in the corresponding. registers (note that if the contact of the tested product is input, then zero information is recorded in the corresponding registers and the currents of the drivers are not generated). These currents are essentially the maximum permissible output for the corresponding output element of the tested product. In the initial state, on the unit outputs of block 5, the signals O are maintained, i.e. elements AND-NOT p are closed, and elements AND 1O ,, - 1O, and 11-1-11,. At the beginning of the device operation, the switch control commands and information about the size of the output capacity of the output product to be tested are put to the test register 3. Control unit 5 accepts control commands, deshi (IDs, generates enable signals for reception and load capacity forwards from test register 3 to registers, sets the IHa signal to unit outputs of block 5, which correspond to the input contacts of the tested block 8, and O signals corresponding to the output contacts of the tested block 8. The control block 5 maintains the generated signals until the end of the test and prohibits the reception of subsequent signals from the test register 3 in control block 5 AND registers 13-j-13n. The operation of the device, assuming, for example, that the first contact npt of the product to be moved is input, the control unit 5, after receiving the control command and decrypting it, opens element 9 and closes elements 1O and 11 / |, thereby ensuring the passage of information from register 3 of the test for the first contact, check 0.4 of the block 8 and block the passage of information on the block 6 of comparison (in register 13, zeros are written and the current does not pass through the shaper 14).

If the first contact of the tested block is an output, then block 5 ui-isleeven provides covering of the element It-HE Q and opening the elements I lOyj and I 11. In this case, the driver 14, TO1Sh forms toK, the value of which is determined by the code written in register 13, which {{ley} flows through the Ei-output element with the maximum permissible load. Information from the output contact of the tested block 8 through the elements AND 10, OR 12, j enters the comparison unit 6, the reference value of the output of the tested block from the register of the test through the elements 11 and OR 12, is also received for comparison. In order to ensure normal function ionization, the AND-HE element 9 has Rgj., In a reciprocal state. Comparison Shock 6 generates O or 1 signals on each test set. Envy of the equality of output signals checks the block and the reference values of the signals coming from the test register. In case of equality, the signal O is generated, in the inequality at least on one of the contacts.

The signal from comparison unit 6 is fed to the single-register register 7, where a malfunction syndrome is formed. The synchronization of the entire device is provided by the clock pulses from the test register. At the beginning of the testing program of each product, information about the distribution is written} 1 & niv of the input and contact contacts of the tested parts. In the testing test program, information is also written, which determines the maximum juicy number of elements into which the output elements can be loaded into the binary code of the output of the product. In the structure of the word, besides this information, the number of the subscriber who should receive this information is also indicated. In the structure of the word, one bit is allocated for the follow signal.

The information part of the word block 1 of memory via block 2 of the record and block 3 of the test cuts 19 enters the I.1FER inputs of the register 18 of the switch and the load registers reg, and the address portion of the word indicating the subscriber number is fed through bus 19 to the first the inputs of the elements And 15 and 16.

If there is a tracking signal at input 19 a; the red part of the word is through. the elements arrive at the inputs of the decoder 16. According to the subscriber number recorded in the address part of the program, the PIR information is received by register 18 kok {mutator or registers, loads using the selected output from the decoder outputs 2O.

In the absence of an informational signal and the address part of the information, the first one is a register of 3 tests as test information.

The control of the test piece is executed in two modes. First, a test check of the products is carried out, at which at the start of operation the register 18 is set to the state corresponding to the input {for the input contacts is one, for the output contacts - zero). All the registers of all registers are set to the zero state, therefore, no current is formed on the output bus of the formers 14-14. The operation of the proposed device during the test check. In no way differs from the operation of the device of the prototype.

If the tested item has passed a test check, the test of the output elements of the product for load capacity begins. The most par parbots mode of an element happens when the output level is low. Therefore, the test program for testing the product for workload with the capacity was set so that all output elements are set to a low level. Suppose that, at the output of the output element of the first contact, ustash) is connected to the level. In penEicrpe 13), the binary code of the maximum load is written down. The corresponding keys of the driver 14 and having formed the 1st one on the common bus are opened by the ramified key. The first drive flows through the output switch of the output element. On the output healthy (in terms of load capacity); microcircuits, the zero level does not change. At the output of the first-chip microcircuit, there are failures that go through the elements 1O and 12 to the comparison unit 6, and from there to the shift register 7. Even with one failure on, the output of the shift register 7 can form a non-operating syndrome.

Claims (2)

Invention Formula . 1. Device for test control of digital nodes of electronic computers according to the author. Ev. No. 694863, characterized in that, in order to increase reliability, A lot of load code registers and groups. pa drivers of parameters of load signals, the group of outputs of the test register is connected respectively to the inputs of each register of load codes of the group, the output group of each of which is connected to the group of inputs of the corresponding generator of parameters of load signals of the group, the output of each of which is connected to the first input of the corresponding element AND switch The third group of outputs of the control unit is connected to the control inputs of the load code registers of the group. 2. The device according to p; 1, that the control unit contains two AND elements, a decoder, a register, the inputs of the first and second AND elements, and the first register input are a group of inputs of the control unit, the outputs of the first and second AND elements connected to the first and second inputs of the decoder, the first output of which is connected to the second input of the register, two groups of outputs of which are respectively the first and second group of outputs of the control unit, the second output of the decoder is the third group of outputs of the control unit. Sources of information taken into account in the examination 1. USSR author's certificate number 694863 ,, class. Q 06 F 11/12, 1979 (prototype). fug. fug. I