JPS6011398B2 - Memory test pattern writing device - Google Patents

Description

[Detailed Description of the Invention] The present invention is used for semiconductor memory testing, and generates an expected value when comparing the expected value with the output of the memory under test during the test, or eliminates unnecessary comparisons. The present invention relates to a pattern writing device for writing a pattern to a storage unit that stores a pattern for generating a mask pattern for the purpose of printing, etc.

In a semiconductor testing device, for example, as shown in FIG. 1, an address pattern is generated from the terminal 12 of a pattern generator 11, the memory under test 13 is accessed, and the write data at that time from the terminal 14 of the pattern generator 11 is accessed. It is written into the test memory 13.

Further, the memory under test 13 is read by the address from the terminal 12, and the read output is supplied to the comparison circuit 15. On the other hand, the address from the terminal 12 also accesses the mask pattern storage section 16 and the expected value pattern storage section 17 at the same time, and the mask pattern and expected value pattern are respectively read out. The read expected value pattern and the data read from the memory under test 3 are compared by the comparison unit 15. At this time, unnecessary items being compared may be masked, and the masking control is performed by the output of the mask pattern storage section 16. In that case, if the - times readout output from the memory under test 13 is a plurality of bits, a specific one of them, that is, one specified by the mask pattern read from the mask pattern storage section 16, is masked to form the expected value pattern. By not generating a comparison output with the mask pattern and only outputting what is not masked from the comparison unit 15, or by not generating any output from the comparison unit 15 for the address specified by the read mask pattern. Efforts are being made to shorten test time and facilitate failure analysis. Memory under test 1
The output of 3 and the expected value from the storage section 17 are compared in the comparison section 16, and a mismatch is outputted to the output terminal 18. In other words, a signal indicating that the part of the address accessed at that time is defective is outputted to the output terminal 18. You will get it. In this way, in the memory test device, the mask pattern storage section 16
and an expected value pattern storage section 17.

Therefore, it is necessary to store the necessary patterns in the storage units 16 and 17 in advance. These storage units 16,1
In writing patterns to the memory 7, mask patterns and expected value patterns generated by a pattern generator such as a central processing unit are sequentially transferred to the storage section and written. However, in writing, conventionally a pattern has been sent from the central processing unit for each bit or for each address. One cycle is relatively long, about 1 microsecond, for writing a pattern from the pattern generation section of the central processing unit to the external storage section via the input/output data bus.
This was slow compared to the operable cycle of about 20 nanoseconds. Therefore, when there are a large number of addresses in the memory under test 13, there is a problem in that it takes a long time to write the mask pattern and the expected value pattern into the corresponding storage section in advance. An object of the present invention is to provide a pattern writing device that can write patterns necessary for a memory test, such as mask patterns and expected value patterns, into a storage section in a relatively short time, that is, at high speed.

According to this invention, when a write command is given to the control section from the pattern generation section, the control section generates an address set signal, a clock pulse, and a data set signal, and the write start address is set in the address counter by the address set signal, Furthermore, parallel data from the pattern generation section is set in the data string conversion section by the data set signal.

This data string conversion section converts input parallel data shifted into serial data by a clock pulse.
At the same time, the address counter increments in a certain direction.
Furthermore, a write pulse is generated from the clock pulse in the write pulse generating section, and the pattern storage section performs a write operation using this pulse, that is, the output of the data string conversion section is written according to the content of the address counter at that time. In this way, patterns are generated under the control of, for example, a central processing unit, and mask patterns, expected value patterns, etc. generated from the pattern generator are applied in parallel to the input/output bus, so each of them is Compared to outputting bits to the bus bit by bit, the transmission speed can be made sufficiently slower, and even if the transmission speed is slowed down, the parallel data is converted to serial data and stored in the pattern storage unit, so overall Can operate at high speed.

Next, an embodiment of the memory test pattern writing device according to the present invention will be described with reference to FIG.

In FIG. 2, 19 is a pattern storage section, which is the mask pattern storage section or the expected value pattern storage section in FIG. 1. The generated pattern from the pattern generation section 21 is written into the pattern storage section 19. For this purpose, a control section 22 is provided. When the control section 22 receives a write command from the pattern generation section 21 through a terminal 23, it generates an address set signal at a terminal 24, a clock pulse at a terminal 25, and a data set signal at a terminal 26. Further, the control section 22 operates based on a reference clock supplied from the terminal 27 of the pattern generation section 21, that is, the pattern generation section 21 and the control section 22 operate in synchronization. The address at which writing begins is set in the address counter 28 by the address set signal at the terminal 24, and is set to address 0, for example.

From this set write start address, the address counter 28 is incremented, for example, by one, in response to the clock at the terminal 25. The count contents of this address counter 28 are given to the pattern storage section 19 as an address, and this storage section 19 is accessed. Furthermore, a data set command is given to the data string converter 29 from the terminal 26, and the data
Parallel data, for example, 16-bit data, from the pattern generation section 21 is taken in in parallel through the input/output bus 31 of the data string conversion section 29 . This data string converter 29 converts parallel data into serial data and is constituted by, for example, a shift register, and the shift pulse is sent to the terminal 29.
This is the clock. In this embodiment, the serial data converted by the data string converter 29 or the pattern generator 2
This is a case in which any of the direct data generated from 1 is selected and written into the pattern storage section 19 one bit at a time, and a data selector 32 is provided.

The data selector 32 selects the output of the data string converter 29 or the input/output bus 3 based on the command from the pattern generator 21.
One of the predetermined 1 bits is selected and supplied to the write data terminal of the pattern storage section 19. Further, the clock pulse from the control section 22 is also supplied to a write pulse generation section 33, and the write pulse generation section 33 generates a write pulse.

When this pulse is applied to the pattern storage section 19, the address is designated by the contents of the address counter 28, and the output data of the data selector 32 is written. For example, as shown in FIG. 3, when a write command as shown in FIG. 3A is generated from the pattern generating section 21, a clock pulse as shown in FIG. 3B is generated at the terminal 25 based on the reference clock from the terminal 27.

Furthermore, a write pulse shown in FIG. 3, which is slightly advanced with respect to this pulse, is generated by the write pulse generator 33, and a write operation to the pattern storage section 19 is performed at the falling edge of this pulse. The address counter 28 changes its contents to 0, 1, 1, etc. as shown in FIG.
For example, it increases by 2, 3, . . . . Therefore, when the content of the counter 28 is 0, the data selected by the selector 32 at that time is
In the evening, for example, the data shown in FIG.
The data is written to the portion specified by the address counter 28 of. For example, 16-bit parallel data on the input/output bus 31 is set in the data string converter 29 every time a data set signal is generated at the terminal 26 as shown in FIG.

This set data is driven by a clock pulse and is sequentially supplied bit by bit to the pattern storage section 19 through the data selector 32. Therefore, pattern generation section 2
The pattern data supplied to the input/output bus 31 by 1 may be supplied once every 16 periods of the clock pulse of the terminal 25.
In other words, data can be written into the pattern storage section 19 at the speed of one stitch, which is the speed at which pattern data is sent from the pattern generation section 21 to the input/output bus 31. In other words, the speed of the address counter 28 and the pattern storage section 19 can generally be as high as about 20 nanoseconds, but the pattern generation section 21, so-called central processing unit, generates a pattern and supplies the pattern to the input/output bus 31. The speed is about 1 microsecond, and therefore the address counter 28, pattern storage section 19, etc. can be operated at high speed.

In this way, compared to the case where each pattern data is directly written into the pattern storage section 19 from the pattern generation section 21 one bit at a time, the present invention can write data at a higher speed. Note that, if necessary, the data selector 32 can be switched to write the pattern of the pattern generating section 21 bit by bit into the pattern storage section 19 in the same way as in the conventional machine. If the input/output bus 31 used is 32 bits, 32 bits of pattern data can be simultaneously generated from the pattern generator 21 and set in the data string converter 29 via the input/output bus, thereby achieving even higher writing speed. It can be carried out. When a plurality of bits, for example 4 bits, are stored in one address part of the storage unit 19, the 16-bit data input to the data string conversion unit 29 is stored in the 0th stage, 4th stage, and 8th stage of the shift register. It is sufficient to simultaneously write the outputs of the stage and the first disguise into the storage section 19, and input new data to the data string conversion section 29 from the input/output bus 31 every four times.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a memory test device, FIG. 2 is a block diagram showing an example of a memory test pattern writing device according to the present invention, and FIG. 3 is a time chart for explaining its operation. 19...Pattern storage unit, 21...Pattern generation unit, 22...Control unit, 23...
...Write command signal terminal, 24...Address set signal terminal, 25...Clock terminal, 26...
... Data set signal terminal, 27 ... Clock terminal, 28 ... Address counter, 29.
...Data string converter, 31...I/O bus, 32...Selector section, 33...Write pulse generator. Car diagram 2 diagram outside 3 diagram

Claims (1)

[Claims] 1. A pattern generator that sends parallel pattern data to the input/output bus, and an address set signal given a write command from the pattern generator, which is faster than the speed at which the parallel pattern data is sent from the pattern generator to the input/output bus. a control section that generates a clock pulse and a data set signal; and an address counter whose write start address is set by the address set signal, which increments in one direction by the clock pulse, generates an address, and which accesses the pattern storage section with the address. Then, the parallel pattern data output from the pattern generator to the input/output bus is inputted by the data set signal, and operated by the clock pulse, converts the parallel pattern data into serial pattern data and writes it into the pattern storage section. a data string converter that supplies the data as data; and a write pulse generator that generates a write pulse for each clock pulse and divides the serial pattern data from the data string converter into a plurality of addresses and writes them into the pattern storage section. A memory test pattern writing device comprising: