JPH1031899A - Semiconductor memory testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time required for the analysis of results with the capacity of a semiconductor memory kept unchanged for the purpose of increasing capacity in a semiconductor memory represented by DRAMs etc. SOLUTION: Such constitution is used that a new address is generated every time fail data is inputted into a sequence controller 8; an outputting data pointer 17 and the address storing memory 16 in which the address outputted from the data pointer 17 is stored with the address of fail data are installed; and the sequence controller 8 outputs the address of fail data to a tester processor 9 after the address of fail data of predetermined volume is stored into the address storing memory 16. And every time the address of fail data is retrieved, the address of fail data is outputted no longer to a tester processor 9 and thereby the processing time in the tester processor is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory test apparatus for testing a semiconductor memory.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of an entire device showing an example of the configuration of a conventional memory test device.

In this conventional example, as shown in FIG. 3, a timing generator 40 for generating a reference clock, and an address signal, a test data signal and a control signal applied to a memory under test 70 in accordance with the reference clock generated by the timing generator 40. A pattern generator 50 for generating and outputting a signal; a waveform shaper 6 for shaping the signal output from the pattern generator 50 into a waveform required for a test and writing the waveform into a memory under test 70
0, the test data is read from the memory under test 70, and the read test data is compared with the expected value output from the pattern generator 50.
And a failure analysis memory 30 that stores fail information when the memory under test 70 is determined to be defective by the logical comparator 80.

[0004] The operation of the memory test apparatus configured as described above will be described below.

First, in the pattern generator 50, an address signal, a test data signal, and a control signal to be supplied to the memory under test 70 are generated and output in accordance with the reference clock generated in the timing generator 40. An expected value for the test data read from the memory under test 70 is also generated and output by the pattern generator 50 at the same time.

Next, in the waveform shaper 60, the address signal, the test data signal, and the control signal generated in the pattern generator 50 are shaped into waveforms required for the test, and written into the memory under test 70.

Thereafter, the test data is read from the memory under test 70 by the logical comparator 80, and the read test data and the expected value output from the pattern generator 50 are compared with each other. Is determined.

In the logical comparator 80, the memory under test 70
Is determined to be defective, the fail information is stored in the failure analysis memory 30. Here, the failure analysis memory 30
, The address signal generated by the pattern generator 50 is also input.

Hereinafter, the above-described failure analysis memory 30 will be described in detail.

FIG. 4 shows the failure analysis memory 30 shown in FIG.
FIG. 3 is a block diagram showing an example of the configuration of FIG.

As shown in FIG. 4, the failure analysis memory 30 according to the prior art includes an address selection unit 31 to which an address signal generated by a pattern generator 50 is input, a failure information output from a logical comparator 80, and An upper address of the addresses input to the address selection unit 31 is input, and a memory control unit 32 that outputs a write signal, and a write signal output from the memory control unit 32 and the address of the address input to the address selection unit 31 The memory section 33 receives the lower address, and stores the fail information in the cell designated by the memory control section 32.

Hereinafter, the operation of the failure analysis memory 30 configured as described above will be described.

When an address signal is sent from the pattern generator 50, the sent address signal is divided into an upper address and a lower address in an address selector 31, and the upper address is sent to the memory controller 32.
The lower address is sent to the memory unit 33, respectively.

At the same time, the memory under test 7
When the fail information of “0” is sent, the sent fail information is input to the memory control unit 32.

Then, the memory control unit 32 outputs a write signal based on the input upper address and the fail information, and the fail information is stored in the memory unit 3.
3 is stored in a cell corresponding to the address signal sent from the pattern generator 50 on a one-to-one basis.

Thereafter, by reading out the failure analysis memory, "1" is read out only from the address where the failure has occurred, so that the failure information stored in the memory section 33 is read out, and the failure address of the memory under test 70 is read out. Is analyzed.

Hereinafter, a fail address search function for analyzing the above-described defective address of the memory under test 70 will be described.

As one of the functions of analyzing a defective address,
There is a fail address search function for searching for an address of a defective cell. This means that the memory section 33 of the memory under test 70 in which the fail information is stored is accessed using a pointer for generating an address for reading and writing the fail information, and the fail data (data = "1") is obtained.
Is read, the pointer is held, the reading operation is stopped, and the value of the pointer is read to search for a failed address.

FIG. 5 is a block diagram for explaining a conventional fail address search function.

When performing a fail address search, first, in a test plan program in which a procedure for failure analysis is described, a search start address and an end address of the fail data storage memory 25 storing the fail data, Specify the number of failures to be performed.

The test plan program is translated and used in the tester processor 9.

Generating an address at the pointer 22;
Fail data storage memory 2 according to the generated address
5 is accessed.

If the data read from the fail data storage memory 25 is "1", that is, a fail, a control signal for holding the pointer value is output from the sequencer 28 and a fail flag is set.

Here, the flag reading check is performed at regular intervals in the tester processor 9 which manages the entire memory test apparatus via a tester bus through which signals exchanged between the units in the memory test apparatus. If the flag is set, the transfer instruction from the tester processor 9 is
, And the pointer value is transferred to the tester processor 9. After the transfer is completed, a start command is output from the tester processor 9 again, and the same operation is repeated.

Thereafter, when the number of failed searches reaches the number of searches specified in the program, or when the value of the pointer reaches the end address specified in the program, the operation ends.

FIG. 6 is a circuit block diagram showing one configuration example of a circuit for realizing a conventional fail address search function.

In this conventional example, as shown in FIG. 6, an STA register 1 storing a search start address, an SPA register 10 storing an end address, and a search address S
An address pointer 2 which is stored in the same manner as the TA register 1 and outputs a search address in synchronization with a clock signal, and a storage memory 5 which stores fail information.
A sequence controller 8 for controlling a fail address search function, and a tester processor 9 connected to the sequence controller 8 via a tester bus and controlling the entire circuit.
Between the storage memory 5 and the storage memory 5, there are provided functional blocks f1 and f2 for converting an address output from the address pointer 2 into a corresponding address in the storage memory 5. A function block f3 for converting fail data output from the storage memory 5 into a predetermined data format is provided between the controller 8 and the controller 8. Further, a function block f3 is provided between the function block f1 and the function block f2. f2 and the storage memory 5, between the storage memory 5 and the functional block f3, and between the functional block f3 and the sequence controller 8.
Are provided with flip-flops 3, 4, 6, and 7, respectively, to form a pipeline.

The operation of the circuit configured as described above will be described below.

The STA register 1 stores a search start address, and the SPA register 10 stores an end address.

When the tester processor 9 instructs the sequence controller 8 to start a fail address search operation, first, the sequence controller 8 outputs a clear signal to the flip-flops 3, 4, 6, and 7, The flip-flops 3, 4, 6, and 7 are initialized.

Then, a clock signal is externally input to the address pointer 2 and the flip-flops 3, 4, 6, and 7, a search start address is output from the address pointer 2, and input to the flip-flop 3 via the functional block f1. You.

Next, when the clock signal is again input to the address pointer 2 and the flip-flops 3, 4, 6, and 7, the search start address input to the flip-flop 3 is output from the flip-flop 3 and The signal is input to the flip-flop 4 via the block f2.

Thereafter, when a clock signal is again input to the address pointer 2 and the flip-flops 3, 4, 6, and 7, the address input to the flip-flop 4 is output from the flip-flop 4 and stored in the storage memory 5. Is entered.

Here, when the fail data is stored at the address input to the storage memory 5, that is,
If the address is a fail address, the output data "1" is output from the storage memory 5, and when this is input to the sequence controller, the value of the address pointer 2 is held and the fail flag is set. If the address input to the storage memory 5 is not a fail address,
Output data “0” is output from the storage memory 5.

As described above, this circuit operates in a pipeline manner, and the fail data output from the storage memory 5 is
Each time a clock signal is input, flip-flops 6, 7
Are sequentially output and input to the sequence controller 8.

Here, as described above, the read check of the fail flag is performed at regular intervals in the tester processor 9, and when the fail flag is "1", the sequence controller 8 sends the address pointer 2
, And the pointer value is held until the tester processor 9 checks the readout of the fail data.

When the reading of the address pointer value by the tester processor 9 is completed, the above operation is repeated again.

When the fail flag is "0", a control signal is sent from the sequence controller 8 to the address pointer 2, the address is incremented, and the above operation is repeated.

Thereafter, when the address output from the address pointer 2 matches the end address stored in the SPA register 10, the operation ends.

[0040]

FIGS. 7A and 7B are time charts showing the operation of the circuit shown in FIG. 6. FIG. 7A is a diagram showing the processing time, and FIG. 7B is an enlarged view of a part of FIG. FIG.

As shown in FIG. 7A, in the circuit shown in FIG. 6, since the tester processor 9 monitors the state of the search operation, the operation of reading the fail flag of the sequence controller 8 is performed by the failure analysis. It is performed in a very long cycle as compared with the operation of the memory. Therefore, even if a fail address is found and the fail flag is set, the operation must be interrupted and waited until the fail flag is read by the tester processor 9.

After the fail flag is read, the address pointer value is transferred to the tester processor 9, and the tester processor 9 performs a restart process for the sequence controller 8. This operation is also performed by the tester processor 9. Since the operation is performed in the operation cycle, it takes time.

As shown in FIG. 7 (b), in the circuit shown in FIG. 6, each of the functional blocks f1 to f3 is connected to a flip-flop 3,
Since the circuit is divided by 4, 6, and 7, and the circuit is configured in a pipeline, five clock signals are required to search one address.

Here, in a semiconductor memory represented by a DRAM or the like, the capacity will continue to increase in the future. Therefore, when searching the entire address space of the memory under test, the time required for the search increases, and as a result, the analysis becomes difficult. Such time also increases. Therefore, it is required to reduce the time required for analyzing results in semiconductor memories having the same capacity.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and is directed to a semiconductor memory test apparatus capable of reading out an address at which a defective cell in a semiconductor memory exists at a high speed. The purpose is to provide.

[0046]

In order to achieve the above object, the present invention provides a storage memory in which fail data "1" is written at a fail address, and a search address for retrieving the fail address. Stored
An address pointer that increments and outputs the search address in synchronization with a clock signal; a sequence controller that controls the operation of the address pointer based on the fail data searched by the search address; and a flag data in the sequence controller. A tester processor that reads and transfers data at a constant cycle; and a plurality of flip-flops provided between the address pointer and the storage memory and between the storage memory and the sequence processor. In the semiconductor memory test apparatus in which the search address and the fail data are sent to the sequence controller side in synchronization with the clock signal, the fail data is stored in the sequence controller. A new address is generated each time it is input to the roller, a data pointer to be output, and an address storage memory in which the address of the fail data is stored in the address output from the data pointer, the sequence controller After an address of the fail data of a predetermined capacity is stored in the address storage memory, all the addresses in the address storage memory are output to the tester processor.

When the address storage memory is filled with the address of the fail data, the address pointer indicates a search address next to the search address obtained by searching the last fail data address among the addresses of the fail data. It is characterized by loading and outputting the loaded address at the next start of the fail address search.

(Function) In the present invention configured as described above, the fail information stored in the storage memory is output to the sequence controller by the search address output from the address pointer, and the search is performed by the search address. The address of the failed data is temporarily stored in the address storage memory at the address output from the data pointer, and after the amount of the stored fail data address reaches a predetermined amount,
Since the data is output to the tester processor via the sequence controller, the wait time for waiting for an instruction from the tester processor is reduced without stopping the operation of searching for the fail address every time the address of the fail data is searched. .

When the search is performed again after all the addresses of the fail data from the address storage memory are output to the tester processor, the address of the last fail data among the addresses of the output fail data is searched. Since the search is performed from the next search address after the search address, one address is searched in one cycle.

[0050]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of a circuit for realizing a fail address search function in a semiconductor memory test device of the present invention.

In this embodiment, as shown in FIG. 1, an STA register 1 for storing a search start address, an SPA register 10 for storing an end address, and a search address are initially stored similarly to the STA register 1. At the same time, an address pointer 2 for outputting a search address in synchronization with a clock signal, a storage memory 5 for storing fail information, a sequence controller 8 for controlling a fail address search function, and a sequence controller 8 via a tester bus A tester processor 9 for controlling the entire circuit, an address storage memory 16 in which an address where a failure has occurred is written, a data pointer 17 for generating an address for writing a fail address in the address storage memory 16, and a data pointer 17 outputs and cash register It compares the output of the motor 19, the address detector 18 for outputting a "stop" signal to the sequence controller 8 if they match, the address pointer 2
A functional block for converting an address output from the address pointer 2 into a corresponding address in the storage memory 5 between the address pointer 2 and the storage memory 5. f1 and f2 are provided, and the storage memory 5
Between the storage controller 5 and the sequence controller 8
A function block f3 for converting data relating to the failure output from the address pointer 2 into corresponding data at the address pointer 2;
1 and the function block f2, between the function block f2 and the storage memory 5, between the storage memory 5 and the function block f3, and between the function block f3 and the sequence controller 8, 6 and 7 are provided, respectively, and flip-flops 11 to 14 are connected in series between the address pointer 2 and the address storage memory 16 to form a pipeline.

The operation of the circuit configured as described above will be described below.

The STA register 1 stores a start search address, and the SPA register 10 stores an end address.

When the tester processor 9 instructs the sequence controller 8 to start a fail address search operation, first, the sequence controller 8 sends the data to the flip-flops 3, 4, 6, 7, 11 to 14 and the data pointer 17. On the other hand, a clear signal is output, the flip-flops 3, 4, 6, 7, 11 to 14 and the data pointer 17 are initialized, and the "operating" flag is set in the sequence controller 8.

Then, a clock signal is externally input to the address pointer 2 and the flip-flops 3, 4, 6, 7, 11 to 14, a search start address is output from the address pointer 2, and the flip-flop is output via the functional block f1. 3 is input.

Thereafter, the address output from the address pointer 2 is incremented each time a clock signal is input. This circuit operates in a pipeline manner. If the address value output from the address pointer 2 is (n + 4), the outputs of the flip-flops 3 and 11 are (n + 3), and the outputs of the flip-flops 4 and 12 are (n + 4).
2), the output of the flip-flop 6 is (n +
Data at address 1), flip-flop 13
Is the address value of (n + 1), flip-flop 7
Is the data of address n, and the output of flip-flop 14 is the address value of n.

As described above, the address information of the address pointer 2 changes every time a clock having a fixed period is input.
The data "0" and "1" relating to the fail which are sequentially appearing in the output of the address pointer 2, the output of the flip-flop 3, and the output of the flip-flop 4 are stored every time the clock is input. At the output of the flip-flop 6 and the output of the flip-flop 7 sequentially, and input to the sequence controller 8.

The address value of the address pointer 2 indicates the output of the flip-flop 11, the output of the flip-flop 12,
The output of the flip-flop 13 and the output of the flip-flop 14 sequentially appear and are input to the address storage memory 16.

When the data relating to the failure input to the sequence controller 8 is “0”, the address value output from the flip-flop 14 is not stored in the address storage memory 16, and the data pointer 17 stores the address value in the address storage memory 16. The address value output to store the address value in the register does not change from the initial value.

When the data relating to the fail input to the sequence controller 8 becomes fail data “1”, the address value output from the flip-flop 14 from the sequence controller 8 is stored in the address storage memory 1.
6 is output, and the flip-flop 1
4 is stored in the address storage memory 16
And at the same time, the address value output to store the address value in the address storage memory 16 in the data pointer 17 is incremented by one. The storage of the address value output from the flip-flop 14 in the address storage memory 16 is performed at the address output from the data pointer 17.

In the following, two cases will be described focusing on the relationship between the address storage memory 16 and the number of failures to be searched.

(1) When the number of fail searches is smaller than the memory capacity In this case, the number of fail to be searched is set in the register 19 in advance.

When the output value from the data pointer 17 does not match the number of failures in the register, that is, the address value output from the data pointer 17 exceeds the number of failures set in the register 19 in advance. If the "stop" flag output from the address detector 18 is "0", a count instruction is output from the sequence controller 8 and the data pointer 17
Is incremented by 1, and the same operation is repeated.

On the other hand, when the output value from the data pointer 17 matches the number of failures in the register, that is, the address value output from the data pointer 17 becomes the number of failures set in the register 19 in advance. When the "stop" flag output from the address detector 18 becomes "1", a hold command is output from the sequence controller 8 and the value of the data pointer 17 is held. At the same time, in the sequence controller 8, the "in operation" flag is reset, and the "complete" flag and the "fail" flag are set.

Thereafter, the tester processor 9 in which the reading operation of the sequence controller 8 is performed at a constant cycle.
, The “completed” in the sequence controller 8
When the flag and the “fail” flag are confirmed, a transfer instruction is sent to the sequence controller 8, and the fail address stored in the address storage memory 16 is transferred using the data pointer 17.

(2) When the number of fail searches is larger than the memory capacity In this case, the register 19 stores the address storage memory 16
Indicating the capacity in the depth direction of the data, in which "1" is set by the number of bits of the address (for example, in the case of 1 Mword #
FFFFF) is set before the start of the search operation.

When the output value from the data pointer 17 does not match the number of failures in the register, that is, the number of addresses output from the data pointer 17 does not exceed the capacity of the address storage memory 16, When the "stop" flag output from the address detector 18 is "0", a count command is output from the sequence controller 8, the address value output from the data pointer 17 is incremented by 1, and the same operation as described above is repeated. Done.

On the other hand, when the output value from the data pointer 17 matches the number of failures in the register, that is, the number of addresses output from the data pointer 17 becomes equal to the capacity of the address storage memory 16, When the “stop” flag output from the address detector 18 becomes “1”, a hold command is output from the sequence controller 8 and the value of the data pointer 17 is held. At the same time, in the sequence controller 8, the "in operation" flag is reset, and the "complete" flag and the "fail" flag are set.

Thereafter, the tester processor 9 in which the reading operation of the sequence controller 8 is performed at a constant cycle.
, The “completed” in the sequence controller 8
When the flag and the “fail” flag are confirmed, a transfer instruction is sent to the sequence controller 8, and the fail address stored in the address storage memory 16 is transferred using the data pointer 17.

When all of the fail addresses stored in the address storage memory 16 are transferred by the tester processor 9, a load instruction is output from the sequence controller 8 to the address pointer 2. Here, the address pointer 2 must hold the address value next to the address where the fail exists in preparation for the restart operation.
Since the output signal of the STA register 1 and the flip-flop 13 are connected via the selector 15 and the “fail” flag controlling the selector 15 is set, the output signal of the STA register 1 is not the flip-flop. Thirteen outputs will be applied.

The flip-flop 13 is one stage before the flip-flop whose fail data is output to the sequence controller 8. Data pointer 1
In FIG. 7, since the address value in the address storage memory 16 has been increased by 1, the output signal of the flip-flop 13 is the one in which the address value in which the fail exists is increased by 1.

After the end of the transfer operation, an instruction to start a fail search operation is sent from the tester processor 9 to the sequence controller 8 again. The operation is switched from the load instruction to the count instruction, and the above-described operation is continued from the held address. Since the held address is the fail address + 1, the search operation is started from the address following the failed address.

Thereafter, when counting is performed in the address pointer 2 up to the address where reading is completed,
The "complete" flag is set and the process ends.

FIG. 2 is a time chart showing the operation of the circuit shown in FIG. 1, (a) is a diagram showing the processing time,
(B) is the figure which expanded a part of (a).

As described above, in this embodiment, the flip-flops 11 to 14, the address storage memory 16, the data pointer 17, and the address detector 18 are provided, and the search operation is performed until the capacity of the address storage memory 16 is satisfied. Since the data transfer processing by the tester processor 9 is not performed, the processing time of the processor excluding the transfer time of the fail address can be reduced,
Higher speed can be realized.

Further, by using the flip-flops 11 to 13 and the selector 15, the specification is such that the pointer is continuously incremented while the storage memory 5 is being accessed.
When the search operation stops after the capacity exceeds 6, the data of the flip-flop 13 is loaded, so that the search from the fail address + 1 can be performed again. Therefore, one address can be searched in one cycle. Therefore, the cycle time can be reduced.

[0078]

Since the present invention is constructed as described above, it has the following effects.

According to the first aspect, each time fail data is input to the sequence controller, a new address is generated, and a fail address is stored in a data pointer to be output and an address output from the data pointer. And the sequence controller outputs a fail address to the tester processor after a predetermined number of fail addresses are stored in the address storage memory, so that the fail address is searched. A fail address is not output to the tester processor each time, and the processing time in the tester processor can be reduced.

According to the second aspect of the present invention, the address pointer outputs a search address next to the search address obtained by searching for the last fail address among the fail addresses after all the fail addresses have been output to the tester processor. With this configuration, one address can be searched in one cycle, and the test can be speeded up.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a circuit for realizing a fail address search function in a semiconductor memory test device of the present invention.

FIGS. 2A and 2B are time charts showing the operation of the circuit shown in FIG. 1, wherein FIG. 2A is a diagram showing a processing time, and FIG. 2B is a diagram in which a part of FIG.

FIG. 3 is a block diagram of the entire device showing one configuration example of a conventional memory test device.

4 is a block diagram illustrating a configuration example of a failure analysis memory illustrated in FIG. 3;

FIG. 5 is a block diagram for explaining a conventional fail address search function.

FIG. 6 is a circuit block diagram showing a configuration example of a conventional circuit for realizing a fail address search function.

7A and 7B are time charts showing the operation of the circuit shown in FIG. 6, wherein FIG. 7A is a diagram showing a processing time, and FIG. 7B is a diagram in which a part of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 STA register 2 Address pointer 3, 4, 6, 7, 11-14 Flip-flop 5 Storage memory 8 Sequence controller 9 Tester processor 10 SPA register 15 Selector 16 Address storage memory 17 Data pointer 18 Address detector 19 Register

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[Procedure amendment]

[Submission date] August 12, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction contents]

[0046]

In order to achieve the above object, the present invention provides a storage memory in which fail data "1" is written at a fail address, and a search address for retrieving the fail address. Stored
An address pointer that increments and outputs the search address in synchronization with a clock signal; a sequence controller that controls the operation of the address pointer based on the fail data searched by the search address; and a flag data in the sequence controller. A tester processor that reads and transfers data at a constant cycle, and a plurality of flip-flops provided between the address pointer and the storage memory and between the storage memory and the sequence controller ; In the semiconductor memory test device in which the search address and the fail data are sent to the sequence controller side in synchronization with the clock signal, the fail data is stored in the sequence code. It generates a new address each time it is input to the controller has a data pointer to be output, and an address storage memory addresses of the fail data in the address outputted from the data pointer is stored,
The sequence controller outputs all the addresses in the address storage memory to the tester processor after an address of the fail data of a predetermined capacity is stored in the address storage memory.

Claims (2)

[Claims] 1. A storage memory in which fail data “1” is written at a fail address, and a search address for searching for the fail address are stored, and the search address is incremented in synchronization with a clock signal. An address pointer to output the data, a sequence controller that controls the operation of the address pointer by the fail data searched by the search address, and a tester processor that reads and transfers the flag data in the sequence controller at a fixed cycle. A plurality of flip-flops provided between the address pointer and the storage memory and between the storage memory and the sequence processor, wherein the plurality of flip-flops have a pipeline configuration; Synchronized with clock signal A semiconductor memory test apparatus in which the search address and the fail data are sent to the sequence controller side, wherein each time the fail data is input to the sequence controller, a new address is generated and output; An address storage memory in which an address of the fail data is stored at an address output from the pointer, wherein the sequence controller stores the fail data address of a predetermined capacity in the address storage memory. A semiconductor memory test apparatus for outputting all the addresses in the address storage memory to the tester processor later. 2. The semiconductor memory test apparatus according to claim 1, wherein said address pointer is used to store the last fail data among said fail data addresses when said address storage memory is filled with said fail data address. A semiconductor memory test apparatus, which loads a search address next to a search address from which an address has been searched, and outputs the loaded address at the next start of a fail address search.