JP2006039843A - Ram test circuit, information processing apparatus, and ram testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct a RAM test during operation through the addition of few hardware resources without affecting memory-access performance by providing a save buffer for the RAM (memory), and conducting a test for each (or every two or four, etc.) word. <P>SOLUTION: A RAM test circuit includes a save register 16 for saving and retaining data in the RAM 13 during tests; an address comparison part 15 that detects if a requested address 32 and an address for use during the execution of the test match; and a data comparison part 18 for making comparisons to see if the test data written in the RAM is correct. First the RAM 13 is read and stored in the save register 16. Next, the test data is written into the RAM 13, the RAM is read, and the data comparison part 18 determines whether or not the data is normal. Then the data in the save register 16 is written back into the RAM 13. A series of these procedures is repeated if there is no RAM request or if the addresses match. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a RAM test circuit, an information processing apparatus, and a RAM test method, and more particularly to a technique for efficiently testing a running RAM.

  Conventionally, BIST (Built In Self Test) is known as one of RAM (Random Access Memory) tests. The BIST executes a RAM test by incorporating a RAM test circuit in the chip or in the device in advance.

  In the conventional BIST, since a test is performed using a relatively low-speed clock, the test may not be performed with the actual clock, and the environment may differ from the actual operating state. Even when a test is performed with the same clock as in operation, the BIST is executed in an environment in which only the BIST operates at a predetermined timing interval in a predetermined address order in a predetermined address order. The state in which noise occurs may differ from the operating environment in which application programs other than BIST are operating. For this reason, errors due to noise that occurs only in the operating environment and does not occur in the BIST may not be detected by the BIST.

  Further, BIST is usually diagnosed by being incorporated in an initialization process at the time of start-up such as power-on, and is not executed during actual operation. The invention disclosed in Japanese Patent Application Laid-Open No. 4-125575 is an example for solving this, and is a technique for performing online diagnosis by setting a diagnosis mode during operation of the system. In this environment, a buffer register is provided to save memory data before diagnosis of the diagnosis target memory, and when the diagnosis target memory is accessed during diagnosis, the buffer register is accessed in an environment close to the operating state. The test has been realized.

  By enabling the RAM test during operation, it is possible to execute the RAM test while operating the software in the inspection process before shipment, and it is possible to detect in advance RAM errors that occur only after shipment. It becomes.

Japanese Patent Laid-Open No. 4-125575

  In the invention of Japanese Patent Laid-Open No. 4-125575, the diagnosis is executed in units of blocks by dividing a memory diagnosis target in units of blocks and providing a save memory block in which the size of the save buffer is one block. There is a problem in that a large-capacity save buffer must be prepared as the save memory block.

  If the save memory block is provided exclusively for diagnosis, a large hardware resource is dedicated for diagnosis. Even if the saved memory block is secured on the memory at the time of diagnosis, the memory capacity that can be used for normal operation during the diagnosis is reduced.

  The object of the present invention is to provide a buffer corresponding to the memory access width for saving and execute the test in units of memory access width, so that the memory access performance is not affected by the input of a small amount of hardware resources. It is an object of the present invention to provide a RAM test circuit, an information processing apparatus, and a RAM test method that can execute a memory (RAM) test.

A first RAM test circuit of the present invention is a RAM test circuit for testing a plurality of words in a RAM,
A save register that saves and holds RAM data during a test, an address comparison unit that compares an address of a RAM request for accessing the RAM with a test execution address that is an address of the RAM for executing the test, and a test A data comparison unit for comparing test data prepared for use with test data written in the RAM;
Procedure A for reading 1 word of RAM data at the test execution address and storing it in the save register;
Procedure B for writing one word of test data to the test execution address of the RAM;
A procedure C for reading one word of data from the test execution address in the RAM and determining whether the data comparison unit is normal;
And a procedure D for writing back one word data of the save register to the RAM.

  In the second RAM test circuit of the present invention, in the first RAM test circuit of the present invention, the procedure A is executed at a timing without the RAM request, and the procedures B, C, and D have no RAM request. Alternatively, it is executed at a timing when the address comparison unit detects a match.

A third RAM test circuit according to the present invention is a RAM test circuit that executes a test for M words (M is an integer not less than 2 and not more than the total number of words in the RAM) of RAM.
A save register that saves and holds data for N words (N is an integer equal to or greater than 2 and greater than or equal to 2) words in the RAM, an address of the RAM request for accessing the RAM, and an address during the test execution are represented by N An address comparison unit for comparing in word units, a data comparison unit for comparing test data prepared for testing and test data written in the RAM,
Procedure A for reading N words of RAM data of a test execution address and storing them in a save register at a timing when there is no RAM request;
Step B for writing N words of test data into the RAM one word at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure C for reading out the RAM and determining whether the data comparison unit is normal or not by N words at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure D for writing back N words of data in the save register to the RAM at the timing when the RAM request is not present or the address comparison unit detects a match,
The procedures A, B, C, and D are repeatedly executed for M words.

  A fourth RAM test circuit according to the present invention has a save flag indicating that the save register is saving the RAM data in the first, second, or third RAM test circuit according to the present invention, When the RAM request is present and the save flag is valid at the timing when the address comparison unit detects a match, the RAM request accesses the save register instead of the RAM.

A first information processing apparatus of the present invention is an information processing apparatus that tests a partial area of a RAM that stores data and a program while the program is running,
An address comparison unit that compares a save register that saves and holds RAM data during a test, and an address of a RAM request for the program to access the RAM and a test execution address that is an RAM address for executing the test A data comparison unit that compares the test data prepared for the test with the test data written in the RAM;
Procedure A for reading 1 word of RAM data at the test execution address and storing it in the save register;
Procedure B for writing one word of test data to the test execution address of the RAM;
A procedure C for reading one word of data from the test execution address in the RAM and determining whether the data comparison unit is normal;
And a procedure D for writing back one word data of the save register to the RAM.

  In the second information processing apparatus of the present invention, in the first information processing apparatus of the present invention, the procedure A is executed at a timing without the RAM request, and the procedures B, C, and D have no RAM request. Alternatively, it is executed at a timing when the address comparison unit detects a match.

A third information processing apparatus of the present invention is an information processing apparatus that tests a partial area of a RAM that stores data and programs during the operation of the program,
A save register that saves and holds data for N words (N is an integer equal to or greater than 2 and greater than or equal to 2) in RAM, a RAM request address for accessing the RAM by the program, and an address during test execution An address comparison unit that compares the data in units of N words, a data comparison unit that compares test data prepared for testing and test data written in the RAM,
Procedure A for reading N words of RAM data of a test execution address and storing them in a save register at a timing when there is no RAM request;
Step B for writing N words of test data into the RAM one word at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure C for reading out the RAM and determining whether the data comparison unit is normal or not by N words at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure D for writing back N words of data in the save register to the RAM at the timing when the RAM request is not present or the address comparison unit detects a match,
The procedures A, B, C, and D are repeatedly executed for M words.

  According to a fourth information processing apparatus of the present invention, in the first, second, or third information processing apparatus of the present invention, the fourth information processing apparatus has a save flag indicating that the save register is saving data in the RAM, When the RAM request is present and the save flag is valid at the timing when the address comparison unit detects a match, the RAM request accesses the save register instead of the RAM.

A first RAM test method of the present invention is a RAM test method for testing a partial area of a RAM for storing data and programs during the operation of the program,
An address comparison unit that compares a save register that saves and holds RAM data during a test, and an address of a RAM request for the program to access the RAM and a test execution address that is an RAM address for executing the test And a data comparison unit that compares the test data prepared for the test and the test data written in the RAM,
Procedure A for reading 1 word of RAM data at the test execution address and storing it in the save register;
Procedure B for writing one word of test data to the test execution address of the RAM;
A procedure C for reading one word of data from the test execution address in the RAM and determining whether the data comparison unit is normal;
It is characterized in that the procedure D of writing back one word data of the save register to the RAM is repeatedly executed in order.

  According to a second RAM test method of the present invention, in the first RAM test method of the present invention, the procedure A is executed at a timing without the RAM request, and the procedures B, C, and D have no RAM request. Alternatively, it is executed at a timing when the address comparison unit detects a match.

A third RAM test method of the present invention is a RAM test method for testing a partial area of a RAM for storing data and programs during the operation of the program,
A save register that saves and holds data for N words (N is an integer equal to or greater than 2 and greater than or equal to 2) in RAM, a RAM request address for accessing the RAM by the program, and an address during test execution And an address comparison unit that compares the data in units of N words, and a data comparison unit that compares the test data prepared for the test and the test data written in the RAM,
Procedure A for reading N words of RAM data of a test execution address and storing them in a save register at a timing when there is no RAM request;
Step B for writing N words of test data into the RAM one word at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure C for reading out the RAM and determining whether the data comparison unit is normal or not by N words at a time when there is no RAM request or when the address comparison unit detects a match,
At the timing when there is no RAM request or when the address comparison unit detects a match, the procedure D for rewriting the data of N words in the save register to the RAM is sequentially repeated for M words.

  According to a fourth RAM test method of the present invention, in the first, second, or third RAM test method of the present invention, the save register includes a save flag indicating that the save register is saving the RAM data, When the RAM request is present and the save flag is valid at the timing when the address comparison unit detects a match, the RAM request accesses the save register instead of the RAM.

  The present invention has an effect that a RAM test can be executed during operation, so that it is easy to detect a failure of the RAM that occurs only in an actual operating environment, and it can be realized with less hardware resources.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the overall configuration. FIG. 1 shows a configuration of an information processing apparatus 10 including a RAM test circuit and a RAM. A circuit that accesses the RAM during operation is not shown in the figure, but the RAM 13 is configured as a main storage device. In this case, the RAM is accessed from a CPU (Central Processing Unit), an input / output control unit, or a communication control unit. FIG. 1 is a diagram prepared for explaining the function, and does not show an actual mounting position.

  Referring to FIG. 1, in the information processing apparatus 10, the RAM 13 is, for example, a RAM provided as a general-purpose register provided in the CPU, a RAM mounted on an IO board, or a plurality of RAMs. RAM.

  The RAM request signal 31 is a RAM access request sent from an access source circuit such as a CPU, and includes a read request for reading data from the RAM 13 and a write request for writing data to the RAM 13. . The request address 32 is address information sent along with the RAM request, the write data 33 is write data to the RAM 13 sent along with the RAM request when the RAM request is a write request, and the read data 34 is the RAM request. Is the data read from the RAM 13 at the time of the read request.

  In FIG. 1, the RAM request signal 31, the request address 32, and the write data 33 are each directly supplied to the selector or the like. However, the address and data are received when the RAM request signal is received in the interface with the request source or in the access processing of the RAM 13. If it is necessary to hold the register, a register may be inserted and held. Here, in order to simplify the description, it is assumed that there is no need for holding.

  The RAM 13, the RAM request signal 31, the request address 32, the write data 33, and the read data 34 described above are necessary for normal operation. The following is provided for executing the RAM test during normal program operation. It is a configuration.

  The test unit 20 is a circuit that controls execution of the RAM test, and includes an address counter 21, a data generation unit 22, and a control unit 23. The address counter 21 is a counter that holds the address of the RAM 13 when the RAM test is executed, and is updated to the next word address every time the test of the word that is the access unit of the RAM 13 is advanced.

  The data generation unit 22 has a function of generating test write data. The test data to be generated is not particularly limited. For example, data of a predetermined pattern may be selected and output by an instruction from the control unit 23, or a special pattern may be generated by another method. You may do it.

  The control unit 23 is a circuit that controls the RAM test, and is usually realized by a hardware circuit, but may be entirely or partially controlled by a microprogram. FIG. 2 is a diagram for explaining the control unit 23.

  The control unit 23 starts a RAM test in response to a test start signal 35, and thereafter divides the RAM request into a read request or a write request, receives an address match signal data match signal, and receives an address selector 11, a write selector 12, and a read selector 14. Then, the RAM selector is executed by controlling the save selector 16 and the save register 17.

  Further, the control unit 23 has a testing flag 25 and a saving flag 24. The in-test flag 25 is set by a test start signal 35 and reset at the end of the test. The save flag 24 is a flag indicating that there is data being saved in the save register 17. When the request address 32 and the address counter 21 match, the access destination of the RAM request is switched from the RAM 13 to the save register and the test is performed. And normal access are executed in parallel.

  The address selector 11 is a circuit that selects an address to be supplied to the RAM 13 from the request address 32 and the address counter 21 in accordance with an instruction from the control unit 23. The write selector 12 is a circuit that selects write data to be supplied to the RAM 13 from the write data 33 and the data generation unit 22 in accordance with an instruction from the control unit 23. The read selector 14 is a circuit that selects read data to be returned to the access source from the RAM 13 and the save register 17 in accordance with an instruction from the control unit 23.

  The save register 17 is a register having a width corresponding to the access width of the RAM 13, and temporarily saves data in the RAM 13 during the test in accordance with an instruction from the control unit 23. The save selector 16 selects data to be supplied to the save register from the RAM 13 and the write data in accordance with an instruction from the control unit 23.

  The address comparison unit 15 compares whether the request address matches the address of the address counter 21 and transmits the result to the control unit 23 as an address match signal. The data comparison unit 18 compares whether the data in the RAM 13 matches the data in the data generation unit 22 and transmits the result to the control unit 23 as a data match signal.

  Next, the operation of the best mode for carrying out the present invention will be described with reference to the drawings. In the following description of the operation, for convenience of explanation, the RAM 13 has a 256 word configuration, and the save register has a 1 word width. However, a word indicates a unit data width for accessing the RAM 13, and an access for a test or a RAM request is executed in units of words.

FIG. 3 is a flowchart showing the operation of the present invention. However, when the operation shown in this flowchart is executed by a hardware circuit, the steps in FIG. 3 are simultaneously executed in parallel as much as possible.
Referring to FIG. 3, when a test start signal 35 is input at the start of the RAM test, the control unit 23 resets the address counter 21 to an initial value 000 # (# indicates hexadecimal display) and the test is in progress. The flag 25 is set (S51). The test start signal is usually sent from a CPU or a diagnostic device. The RAM test is started from the word at address = 000 # and executed until address = 0FF #.

  When the test-in-progress flag 25 is set, the control unit 23 proceeds with the test using a time when there is no RAM request. In the RAM test, four operations of saving RAM data, writing test data, comparing written data, and returning the saved data to the RAM are sequentially executed for each word under the control of the control unit 23, and this operation is performed on all words. It ends by repeatedly executing for. Each of the above operations is executed so as not to conflict with the RAM request.

  First, the RAM data saving operation confirms that there is no RAM request (S52). If there is a RAM request, the processing of the RAM request is finished and it waits for the RAM request to disappear. If there is no RAM request, proceed to the next.

  Next, data is read from the RAM 13, stored in the save register 17, and the save flag 24 is set (S53). At this time, the control unit 23 operates to instruct the save selector 16 to select the RAM 13 and to instruct the save register 17 to update data. Since the address counter 21 initially has an initial value 000 #, the data at address 0 in the RAM 13 is saved. The save-in-progress flag 24 is valid until data is saved in the save register 17 and then returned to the RAM 13. S51 and S52 are executed in the same cycle when the control unit 23 is realized by a hardware circuit. A cycle is a period in which a hardware circuit is defined and repeated with reference to a clock.

  Here, the operation of the RAM request will be described. FIG. 4 shows the logic of the RAM request operation. The RAM request operation indicates an operation when the RAM request 31 is valid. When the saving flag 24 is invalid, the RAM request is executed to the RAM 13 as usual. The address selector 11 selects the request address 32, the write selector 12 selects the write data 33, the read selector 14 selects the RAM 13, and the save register 17 is held. For example, in the read request, the data in the RAM 13 addressed by the request address 32 is returned from the read selector 14, and in the write request, the write data 33 is written in the word addressed by the request address 32 in the RAM 13.

  When the saving flag 24 is valid and the address match 36 is invalid, the same operation as when invalid is performed, and the RAM request is executed to the RAM 13.

  When the save flag 24 is valid and the address match 36 is valid, the RAM data is being saved in the save register 17, so that the RAM request is executed to the save register 17 instead of the RAM 13. The read selector 14 selects the save register 17 and the save selector 16 selects the write data 33. For example, the RAM data saved in the save register 17 is returned from the read selector 14 in the read request, and the write data 33 is written in the save register 17 in the write request. At this time, the RAM test also operates simultaneously, and the address selector 11 and the write selector 12 are controlled by the control unit 23 in accordance with the contents of each operation as will be described later.

  Next, the test data write operation proceeds to the next if there is no RAM request 31 (S54) or it is confirmed that the address match 36 is valid (S55). If the RAM request 31 is valid and the address match 36 is invalid, the processing of the RAM request 31 is completed and the RAM request 31 is awaited to become invalid.

  Next, the control unit 23 instructs the address selector 11 to select the address counter 21, instructs the data selector 12 to select the data generation unit 22, and instructs the RAM 13 to write. The test data (A) created by the data generator 22 is written into the word of the RAM 13 addressed by the address counter 21 via the write selector 12 (S56). S54, S55, and S56 are executed in the same cycle when the control unit 23 is realized by a hardware circuit.

  Next, the data comparison operation proceeds to the next if there is no RAM request 31 (S57) or it can be confirmed that the address match 36 is valid (S58). If the RAM request 31 is valid and the address match 36 is invalid, the processing of the RAM request 31 is completed and the RAM request 31 is awaited to become invalid.

  Next, the control unit 23 instructs the address selector 11 to select the address counter 21 and compares the data in the RAM 13 addressed by the address counter 21 with the test data (A) created by the data generation unit 22. The data is supplied to the unit 18 for comparison to check whether they match (S59). S57, S58, and S59 are executed in the same cycle when the control unit 23 is realized by a hardware circuit.

  If the data in the RAM 13 matches the test data (A), the data comparison unit 18 validates the data match signal 37. The control unit 23 proceeds to the next when the data match signal 37 is valid, and determines that the RAM 13 is abnormal when it is invalid.

  The operation after determining the abnormality is not particularly limited, but the test may be stopped immediately to notify the CPU or the diagnostic device that there is an abnormality, or the saved data can be written back to the RAM 13 and continued. The test may be stopped and the CPU or diagnostic device may be notified after returning to step 1, or the RAM 13 or the storage means that receives the data separately from the RAM 13 in advance is determined in advance. It is also possible to store the data in a region not shown in the figure and notify the CPU and the diagnostic device when all the words have been tested.

  Next, the operation for returning the saved data to the RAM proceeds if there is no RAM request 31 (S60) or it can be confirmed that the address match 36 is valid (S61). If the RAM request 31 is valid and the address match 36 is invalid, the processing of the RAM request 31 is completed and the RAM request 31 is awaited to become invalid.

  Next, the control unit 23 instructs the address selector 11 to select the address counter 21, instructs the write data selector 12 to select the save register 17, and instructs the RAM 13 to write, The RAM data saved in the save register 17 is written back to the original location, and at the same time as the write back, the saving flag is reset and invalidated (S62).

  Subsequently, the control unit 23 updates the address counter 21 (S63). Initially, the address counter 21 is updated from 000 # to 001 #. S60, S61, S62, and S63 are executed in the same cycle when the control unit 23 is realized by a hardware circuit.

  The control unit 23 determines whether the process has been completed based on the value of the address counter 21 (S64). In this example, when the value of the address counter 21 is 100 #, the control unit 23 determines that the process has ended.

  If the RAM test has not ended, the test target word is moved to the next address, and the operation from step S52 is repeated. In this example, the test is executed for words whose address counter 21 has a value from 000 # to 0FF #. When the RAM test is finished, the testing flag 25 is reset and the control unit 23 finishes the RAM test (S65).

  As described above, according to the present invention, a part of the RAM test target area is tested while being sequentially saved, so that the amount of hardware required for saving can be reduced. In addition, the execution of the RAM test is divided into four operations of saving, test writing, comparison, and returning, and the processing is advanced in parallel so as not to compete with normal RAM access for each operation. It can be executed without affecting normal access. Therefore, as in the prior preparation before the test, the data in the test target area is moved to the save area or the save buffer all at once, so that it affects the JOB (unit of work of the program) in operation. Can be avoided.

  For example, even if the RAM test conflicts with normal RAM access, not only normal access is prioritized but also the normal access is delayed because the test interrupt is only one cycle per operation. Can be avoided. If the request address matches the test address during data saving, the normal access and the RAM test can be executed simultaneously, so that the RAM test can be executed more efficiently.

  In the above description, the save register 17 has been described as having one word width. However, the present invention can be applied to, for example, a two word width and a four word width. For example, a RAM test circuit whose save register 17 has a 2-word width performs a RAM data save operation continuously for two words, performs a test data write operation in two words one by one, and performs a data comparison operation. This can be realized by dividing each word into two times and performing the operation of returning the saved data to the RAM continuously for two words.

  When a plurality of words are held in the save register 17, the address comparison unit 15 needs to be configured to compare in units of the number of consecutive words. For example, when 2 words are saved in the save register 17, by comparing the least significant bit of the address from the comparison target, it is possible to compare the even address and the following odd address in units of 2 words, which is easily realized. be able to.

It is the block diagram which showed the structure of this invention. It is the figure which showed the detail of the control part 23 of this invention. It is the flowchart which showed the operation | movement of this invention. It is the figure which showed the operation logic of the normal access of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Information processing apparatus 11 Address selector 12 Write selector 13 RAM
14 Read selector 15 Address comparison unit 16 Save selector 17 Save register 18 Data comparison unit 20 Test unit 21 Address counter 22 Data generation unit 23 Control unit 24 Saving flag 25 Testing flag

Claims (12)

A RAM test circuit for testing a plurality of RAM words,
A save register that saves and holds RAM data during a test, an address comparison unit that compares an address of a RAM request for accessing the RAM with a test execution address that is an address of the RAM for executing the test, and a test A data comparison unit for comparing test data prepared for use with test data written in the RAM;
Procedure A for reading 1 word of RAM data at the test execution address and storing it in the save register;
Procedure B for writing one word of test data to the test execution address of the RAM;
A procedure C for reading one word of data from the test execution address in the RAM and determining whether the data comparison unit is normal;
A RAM test circuit comprising a procedure D for writing back one word of data in the save register to the RAM. The procedure A is executed when there is no RAM request, and the procedures B, C, and D are executed when there is no RAM request or when the address comparison unit detects a match. 1 RAM test circuit. A RAM test circuit that executes a test for M words of RAM (M is an integer not less than 2 and not more than the total number of words of RAM).
A save register that saves and holds data for N words (N is an integer equal to or greater than 2 and greater than or equal to 2) words in the RAM, an address of the RAM request for accessing the RAM, and an address during the test execution are represented by N An address comparison unit for comparing in word units, a data comparison unit for comparing test data prepared for testing and test data written in the RAM,
Procedure A for reading N words of RAM data of a test execution address and storing them in a save register at a timing when there is no RAM request;
Step B for writing N words of test data into the RAM one word at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure C for reading out the RAM and determining whether the data comparison unit is normal or not by N words at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure D for writing back N words of data in the save register to the RAM at the timing when the RAM request is not present or the address comparison unit detects a match,
A RAM test circuit, wherein the steps A, B, C, and D are repeated for M words. If the save register has a save flag indicating that the RAM data is being saved, and the RAM request is present and the save flag is valid at the timing when the address comparison unit detects a match, the RAM request is stored in the RAM request. 4. The RAM test circuit according to claim 1, wherein the save register is accessed instead of the RAM test circuit. An information processing apparatus that tests a partial area of a RAM for storing data and programs while the program is running,
An address comparison unit that compares a save register that saves and holds RAM data during a test, and an address of a RAM request for the program to access the RAM and a test execution address that is an RAM address for executing the test A data comparison unit that compares the test data prepared for the test with the test data written in the RAM;
Procedure A for reading 1 word of RAM data at the test execution address and storing it in the save register;
Procedure B for writing one word of test data to the test execution address of the RAM;
A procedure C for reading one word of data from the test execution address in the RAM and determining whether the data comparison unit is normal;
An information processing apparatus comprising: a procedure D for writing back one word data of a save register to a RAM. The procedure A is executed when there is no RAM request, and the procedures B, C, and D are executed when there is no RAM request or when the address comparison unit detects a match. 5. Information processing apparatus. An information processing apparatus that tests a partial area of a RAM for storing data and programs while the program is running,
A save register that saves and holds data for N words (N is an integer equal to or greater than 2 and greater than or equal to 2) in RAM, a RAM request address for accessing the RAM by the program, and an address during test execution An address comparison unit that compares the data in units of N words, a data comparison unit that compares test data prepared for testing and test data written in the RAM,
Procedure A for reading N words of RAM data of a test execution address and storing them in a save register at a timing when there is no RAM request;
Step B for writing N words of test data into the RAM one word at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure C for reading out the RAM and determining whether the data comparison unit is normal or not by N words at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure D for writing back N words of data in the save register to the RAM at the timing when the RAM request is not present or the address comparison unit detects a match,
An information processing apparatus characterized by repeatedly executing the procedures A, B, C, and D for M words. If the save register has a save flag indicating that the RAM data is being saved, and the RAM request is present and the save flag is valid at the timing when the address comparison unit detects a match, the RAM request is stored in the RAM request. 8. The information processing apparatus according to claim 5, wherein the save register is accessed instead of the information processing apparatus. A RAM test method for testing a partial area of a RAM for storing data and programs while the program is running,
An address comparison unit that compares a save register that saves and holds RAM data during a test, and an address of a RAM request for the program to access the RAM and a test execution address that is an RAM address for executing the test And a data comparison unit that compares the test data prepared for the test and the test data written in the RAM,
Procedure A for reading 1 word of RAM data at the test execution address and storing it in the save register;
Procedure B for writing one word of test data to the test execution address of the RAM;
A procedure C for reading one word of data from the test execution address in the RAM and determining whether the data comparison unit is normal;
A RAM test method, wherein a procedure D for writing back one word data of a save register to a RAM is repeatedly executed in order. The procedure A is executed when there is no RAM request, and the procedures B, C, and D are executed when there is no RAM request or when the address comparison unit detects a match. 9. RAM test method. A RAM test method for testing a partial area of a RAM for storing data and programs while the program is running,
A save register that saves and holds data for N words (N is an integer equal to or greater than 2 and greater than or equal to 2) in RAM, a RAM request address for accessing the RAM by the program, and an address during test execution And an address comparison unit that compares the data in units of N words, and a data comparison unit that compares the test data prepared for the test and the test data written in the RAM,
Procedure A for reading N words of RAM data of a test execution address and storing them in a save register at a timing when there is no RAM request;
Step B for writing N words of test data into the RAM one word at a time when there is no RAM request or when the address comparison unit detects a match,
A procedure C for reading out the RAM and determining whether the data comparison unit is normal or not by N words at a time when there is no RAM request or when the address comparison unit detects a match,
A RAM test characterized in that, when there is no RAM request or when the address comparison unit detects a match, the procedure D for rewriting the data of N words in the save register to the RAM is sequentially repeated for M words. Method. If the save register has a save flag indicating that the RAM data is being saved, and the RAM request is present and the save flag is valid at the timing when the address comparison unit detects a match, the RAM request is stored in the RAM request. 12. The RAM test method according to claim 9, wherein the save register is accessed instead.

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