JPH1125006A - Memory tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory tester capable of checking a memory during practical processing without including a specific check mode. SOLUTION: A register table 14 has an address storage area for storing addresses corresponding to respective registers. At the occurrence of writing operation from an image processing circuit 3 to a memory 9, memory data 7 are simultaneously written in a register of a register table 14 which corresponds to a writing address in the memory 9. At the occurrence of reading operation from the memory 9, a data comparing circuit 17 compares data read out from the memory 9 with data stored in the table 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test device which uses a rewritable memory as a storage means in arithmetic processing and can check the operation of the memory during execution of the processing.

[0002]

2. Description of the Related Art Conventional memory checking methods include:
JP-A-6-12339 discloses that a microcomputer writes test data to a target memory area, reads data from the memory again by the microcomputer, compares the written data with the read data, There has been proposed a memory check method for notifying an external address of a mismatch when an error occurs.

Japanese Patent Application Laid-Open No. Hei 6-231051, Japanese Patent Application Laid-Open No. 6-231051, discloses a banked memory check device which includes test means for writing test data for each bank of the memory, reading the written test data, and comparing the data. A memory check device has been proposed.

Further, in Japanese Patent Application Laid-Open No. Hei 6-282500,
A memory check method for writing test data to a first area and sequentially transferring i-th data to an (i + 1) -th area in a memory divided into a plurality of areas, and comparing read data from the last area with test data Has been proposed.

[0005]

However, the above prior art has the following disadvantages. JP-A-6-12
In the memory check method disclosed in No. 339, a memory check is sequentially performed for each address by the CPU, and thus a test time proportional to the memory capacity is required. In addition, the memory check device disclosed in Japanese Patent Application Laid-Open No. 6-231051 requires a device for writing, reading, and comparing for each bank individually for a memory check, which increases the circuit scale. Further, in the memory check method disclosed in Japanese Patent Application Laid-Open No. 6-282500, since data read from the last area is compared with test data, it is not possible to specify at which address an error has occurred.

Further, in any of the above methods,
It is necessary to enter a special mode for memory check at the time of power-on or reboot, and perform a memory check. Therefore, the memory check cannot be performed when an actual memory is used. Further, it is necessary to separately generate a test pattern for a memory test.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a memory test apparatus capable of checking a memory during actual processing without having a special check mode. Aim.

[0008]

According to the present invention, there is provided a test address storing means for storing a predetermined address of a memory under test as a test address.
When data is written to the test address of the memory under test, test data register means for storing the same test data as the written data in association with the test address; When data is read from the test address in the memory, a corresponding means for reading corresponding data from the test data register means and comparing the two; and a test address change for changing the test address. Means.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory test apparatus according to an embodiment of the present invention will be described with reference to the drawings.
In the embodiment, an image processing apparatus in which a memory check is performed during execution of a process will be described as an example, but the present invention is not limited to this.

[0010] 1. 1. First Embodiment (1) Configuration of First Embodiment FIG. 1 is a block diagram showing a configuration of a first embodiment.
As shown in the figure, the image processing circuit 3 includes a memory 9, a memory check circuit 100, and a processing stop unit 101.

The memory 9 is a memory under test on which a memory check is performed. In this image processing apparatus, predetermined processing is performed after the input image data 1 is once written in the memory 9 via the image processing circuit 3 and read out to the image processing circuit 3 again. The processed data is output as output image data 2.

The memory check circuit 100 operates when data is written to or read from the memory 9.
This is a circuit for checking whether or not an error has occurred at an address in the memory 9, and the processing stopping means 101 is for stopping the processing being executed when an error has occurred.

In the figure, reference numeral 4 denotes a chip select signal, reference numeral 5 denotes a write permission signal, and reference numeral 6 denotes a read permission signal. These read and write data to and from the memory 9 and operate the memory check circuit 100. Is a signal for controlling The memory data 7 is image data for one address to be written, and the memory address 8 is data indicating addresses at which writing and reading are performed.

Next, each part of the memory check circuit 100 will be described. As shown in the dotted line in FIG. 1, the memory check circuit 100 includes an address update circuit 11, a register table 14, and a data comparison circuit 17. The address update circuit 11 stores the register table 1
4 is a circuit for updating a predetermined address stored in the memory 4. Here, the predetermined address indicates a specific address existing in the memory 9 as a test address. That is, an address in the memory 9 to be checked for an error is specified. The register table 14 is a circuit for storing the same data as the data to be written to the address to be checked in the memory 9 and will be described later in detail. The data comparison circuit 17 is a circuit that performs a memory check by comparing data read from the memory 9 with data stored in the register table 14.

Here, the register table 14 will be described. FIG. 2 is a block diagram illustrating a configuration example of the register table 14. The address storage area 19 is an area for storing a test address. In the present embodiment, the memory check is performed when the address written to the memory 9 matches the test address. In this embodiment, as shown in FIG. 2, the address storage area 19 can store eight test addresses. Reference numerals 22a to 22h are registers, and store the memory data 7 by register write signals 20a to 20h output in correspondence with the respective test addresses stored in the address storage area 19. That is, the register write signal 20a is input to the register 22a, the register write signal 20b is input to the register 22b, and similarly, the register write signal 20h is input to the register 22h. Memory data 7 is stored. The multiplexer 24 selects and outputs the register outputs 23a to 23h from the registers 22a to 22h according to the register selection signal 21 output from the address storage area 19.

(2) Operation of First Embodiment Next, the operation of the image processing apparatus having the above configuration will be described with reference to FIGS. When the input image data 1 is input, the image processing circuit 3 first stores the input image data 1 in the memory 9 and then reads out the image data from the memory 9 again to perform processing. The memory check is performed simultaneously with the write and read operations.

First, a write operation to the memory 9 is performed by controlling the chip select signal 4, the write enable signal 5, and the memory address 8. That is, when a write operation is detected by the chip select signal 4 and the write enable signal 5, the value of the memory data 7 is written to the address indicated by the memory address 8. The read operation from the memory 9 is performed by controlling the chip select signal 4, the read enable signal 6, and the memory address 8. That is, when a read operation is detected by the chip select signal 4 and the read enable signal 6, the data stored at the address indicated by the memory address 8 is output to the memory data 7.

Here, the writing to the register table 14 will be described in detail with reference to FIG. When the chip select signal 4, the write enable signal 5, the memory address 8, and the memory data 7 are output from the image processing circuit 3 to the memory 9, a write operation of the memory data 7 occurs.
The chip select signal 4, the write enable signal 5, the memory address 8, and the memory data 7 are input to the address storage area 19 at the same time.
When a write operation to the memory 9 is detected, the stored test address and the memory address 8 are compared. If the address indicated by the memory address 8 matches any of the stored test addresses, the register write signals 20a to 20 corresponding to the test address are stored.
h is output.

The memory data 7 includes a register 22a to which any one of the register write signals 20a to 20h is input.
２２22h. Register data 23a to 23h are output from the registers 22a to 22h to the multiplexer 24, respectively.

Next, comparison in the data comparison circuit 17 will be described. When the chip select signal 4, the read permission signal 6, and the memory address 8 are output from the image processing circuit 3 to the memory 9, the operation of reading the memory data 7 from the address indicated by the memory address 8 in the memory 9 to the image processing circuit 3 Occurs. The chip select signal 4, the read enable signal 6, and the memory address 8 are simultaneously input to the address storage area 19, and the address storage area 1
When detecting the read operation from the memory 9, the memory 9 compares the stored test address with the memory address 8. Then, when the address indicated by the memory address 8 matches any of the stored test addresses, a comparison enable signal 16 is output to the data comparison circuit 17, and
The register selection signal 21 is output to the multiplexer 24. The register selection signal 21 is a signal for instructing the multiplexer 24 which of the registers 22a to 22h is to read the data written therein. The multiplexer 24 outputs the register data 23a to 23h in accordance with the register selection signal 21. One of them is selected and output to the data comparison circuit 17 as comparison data 15.

The chip select signal 4, the read enable signal 6, and the memory data 7 are input to the data comparison circuit 17 at the same time. The data comparison circuit 17 converts the chip select signal 4 and the read enable signal 6 from the memory 9
When a read operation from the memory is detected, the comparison enable signal 1
When 6 is detected, the memory data 7 read from the memory 9 is compared with the comparison data 15 and a data comparison result 18 is output. The data comparison result 18 indicates true if the data matches, and false if the data does not match.

Here, the memory address 8 is 0x1000
The case of (1) will be described as an example. Since the address indicated by the memory address 8 when writing to the memory 9 matches one of the stored test addresses, the address storage area 19 outputs the register write signal 20b to the register 22b. Then, the memory data 7 is written to the register 22b. When data is read from the address 0x1000 in the memory 9, the address storage area 19 sends the comparison enable signal 16 to the data comparison circuit 1.
7 to output the register selection signal 21 to the multiplexer 2
4 is output. The multiplexer 24 selects the register data 23 b according to the register selection signal 21 and outputs the same as the comparison data 15. The data comparison circuit 17 compares the read memory data 7 with the comparison data 15, that is, the data written in the register 22 b at the same time as being written to the address 0x1000 in the memory 9.
If these data do not match, the data written at address 0x1000 of the memory 9 does not match the read data, and it can be determined that an error has occurred at address 0x1000. As described above, it can be detected from the value of the data comparison result 18 whether an error has occurred at the address of the memory 9 where the reading operation has been performed, and if an error has occurred, the process being executed is interrupted. It has become.

The address set in the address storage area 19 is updated as follows. When updating the test address for performing the memory check, the image processing circuit 3 sends a processing end signal 1 to the address updating circuit 11.
Outputs 0. When the processing end signal 10 is input, the address update circuit 11 outputs an update address 12 and an address write signal 13 so as to update the address set in the address storage area 19. The test address is updated when the memory check is completed for the test address stored in advance, for example, every time one process in the image processing circuit 3 is completed.
Is incremented (increased) or decremented (decreased) by one. In this way, by updating the addresses to be checked sequentially,
It is possible to sequentially check the addresses of the memory with a limited number of register areas.

2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, when an error occurs at a certain address in the memory 9, the error is repaired by substituting the data of the register existing in the register table 14.

(1) Configuration of the Second Embodiment FIG. 3 is a block diagram showing the configuration of the second embodiment.
As shown, the image processing circuit 3, the memory 9, the register control circuit 25, the register table 14, and the data comparison circuit 17 are configured. The image processing circuit 3, the memory 9, the register table 14, and the data comparison circuit 17 in the figure are the same as those described in the first embodiment, and thus the description is omitted. The register control circuit 25 outputs the update address 12 and the address write signal 13 similar to those in the first embodiment to the register table 14 in response to the processing end signal 10 from the image processing circuit 3 and is set in the address storage area 19. This is a circuit that controls updating of the address.

In the second embodiment, the data comparison result 18 is input to a register control circuit 25 and a register table 14 in order to perform an error repairing process. 3 is also input. Also, reference numeral 26 in the figure
Indicates a data selection signal, and reference numeral 27 indicates an error notification signal. The error notification signal 27 is a signal output from the register control circuit 25, and instructs to repair the error when the error occurs.

(2) Operation of the Second Embodiment Also in the second embodiment, the image processing circuit 3 once stores the input image data 1 in the memory 9 and then reads out the image data from the memory 9 again to perform the processing. The write and read operations are the same as in the first embodiment, and a description thereof will be omitted. The operations of the register table 14 and the data comparison circuit 17 are the same as those of the first embodiment.
Is output to the data comparison circuit 17, and the data comparison circuit 17 performs data comparison and outputs a data comparison result 18.

In the second embodiment, the data comparison result 18
Are the register control circuit 25 and the register table 14
Has been entered. When the register control circuit 25 detects false from the data comparison result 18, the register control circuit 25 determines that an error has occurred at the address of the memory 9 from which the reading process was performed at that time, and replaces the register in the register table 14 with the error of the memory 9. Reserve as an alternative area for the occurrence address. Specifically, the register control circuit 25 outputs a data selection signal 26 corresponding to the data comparison result 18 to the image processing circuit 3.
Output to The data selection signal 26 is the data comparison result 1
8 is true, the memory data 7 is selected. If the data comparison result 18 is false, the register table 1 is used as an alternative to the memory data 7 read from the memory 9.
4 indicates that the comparison data 15 output from 4 is selected as image processing data. That is, when the data comparison result 18 is false at the address where the data comparison is performed, the comparison data 15 is the same as the written data, but the memory data 7 is different from the written data. Therefore, by replacing the data read from the address in the memory 9 where the error has occurred with the data stored in the register table 14, the error can be repaired.

In the subsequent processing, the register control circuit 25 controls the update address 12 and the address write signal 13 so as not to update the test address value in the address storage area 19 indicating the same value as the address where the error has occurred. Is secured as a dedicated area of the error occurrence address in the memory 9 in the subsequent processing. However, since the register area in the register table 14 is finite,
When the number of error occurrence addresses reaches the number of register areas existing in the register table 14, further error recovery becomes impossible. Therefore, when the number of error occurrence addresses reaches the number of register areas, the register control circuit 25
Outputs an error notification signal 27 to notify an external error.

As described above, in the second embodiment, when an error occurs at a certain address in the memory 9, the register table 1 is used instead of the address at which the error has occurred.
By allocating the registers in 4, the error can be repaired, and the memory check can be performed without interrupting the processing until the number of errors reaches the number of registers.

[0031]

As described above, according to the present invention,
It is possible to provide a memory test apparatus capable of checking a memory during actual processing without having a special check mode.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment.

FIG. 2 is a block diagram showing a configuration example of a register table 14;

FIG. 3 is a block diagram illustrating a configuration of a second embodiment.

[Explanation of symbols]

1 .... input image data, 2 .... output image data, 3 ....
Image processing circuit, 4 chip select signal, 5 write enable signal, 6 read enable signal, 7 memory data, 8 memory address, 9 memory, 10 memory
A process end signal, 11 an address update circuit, 12
Update address, 13 address write signal, 14
Register table, 15 comparison data, 16 comparison enable signal, 17 data comparison circuit, 18 data comparison result, 19 address storage area, 20a to 20h
..Register write signal, 21. register select signal, 22a to 22h .. register, 23a to 23h ..
Register data, 24 multiplexer, 25 register control circuit, 26 data selection signal, 27 error notification signal, 100 memory check circuit, 101
..Process stop means

Claims (5)

[Claims] 1. A test address storage means for storing a predetermined address of a memory under test as a test address, and when data is written to the test address of the memory under test, Test data register means for storing the same test data in association with the test address, and when data is read from the test address in the memory under test, the corresponding data is read out from the test. A memory test apparatus comprising: comparison means for reading from the data register means for comparing the two; and a test address change means for changing the test address. 2. The memory test apparatus according to claim 1, wherein the test address changing means increments or decrements an address stored in the register by a predetermined value each time one process is completed. . 3. The apparatus according to claim 1, further comprising a processing stop means for notifying of the occurrence of an error when the comparison result of said comparison means is false, and for interrupting the processing being executed. 3. The memory test device according to claim 1. 4. When the comparison result of the comparing means is false, one area of the register is secured as a dedicated area for the address, and when the address is accessed in the subsequent processing, 3. The memory test apparatus according to claim 1, further comprising register control means for controlling use of one area of said register allocated exclusively for said address as a substitute for said memory. 5. The memory test apparatus according to claim 4, further comprising a notifying means for notifying an error occurrence to the outside when an error occurrence address reaches the number of areas of said register.