JPH0235545A - Diagnosing method for set associative cache memory - Google Patents

Abstract

PURPOSE:To facilitate diagnosing operation by generating at least one signal which enables stored information to be read out or written in a substitution priority storage means for data of each way. CONSTITUTION:A control register 21 sets a control signal TEST to '1' and a control signal RW to '0' or '1'. The control signal TEST places a cache memory in diagnostic mode when '1'. The control signal RW allows information to be written in an LRU bit memory 8 when '0' in diagnostic mode and also allows stored information to be read out of the LRU bit memory 8 when '1' in diagnostic mode. Then when the control signal RW is '0', the information to be written in the LRU bit memory 8 is written in the LRU bit memory 8 specified by a set select 3 through a control circuit 22. Further, when the control signal RW is '1', the information stored in the LRU bit memory 8 specified by the set select 3 is read out through the control circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for diagnosing a set-associative cache memory.

[Conventional technology]

FIGS. 2(al) and (b) are an address configuration diagram and a block configuration diagram of a 4-way set associative cache memory for explaining a conventional set-associative cache memory diagnosis method. The CQ associative cache memory is
Publisher's [Interface J September 19B7 issue 25
It is written on page 0.

In FIG. 2(a), 1 is the address to access the cache memory, 2 is the address tag which is part of address 1, 3 is the set select which is part of address 1, and 4 is part of address 1. This is a word select. In addition, in Figure 2), 5 is an address tag memory that holds address tags in the cache memory;
is a variable bit memory that indicates whether the data held in the data block memory 7, which will be described later, is valid or invalid.

Reference numeral 7 represents a data block memory for holding data in the cache memory, and reference numeral 8 represents an LRU bit memory as a data replacement priority storage means for each way. L.R.U.
The bit memory 8 performs data replacement using LRU (Lea
This is a status register controlled by the stRecentlyUsed) algorithm. Furthermore, 9 is an address tag comparator which compares the address data held in the address tag 2 and the address data held in the address tag memory 5 to see if they match, and 10 is selected by the word select 4 of address l. A selector 11 is a selector selected by an address tag comparator, and a is data output from the selector 11.

Next, the operation will be explained. When an address l is given from the outside, the contents of the address tag memory 5 of each way selected by the set select 3 are sent to the address tag comparator 9, and the contents of the data block memory 7 are also sent to the selector 10.
The word data selected by the word select 4 is sent to the selector 11. Then, in the address tag comparator 9,
Contents of selected address tag memory 5 and address tag 2
If there is a matching way, the selector 11 outputs the data of that way as output data a. However, if there is a mismatch in the address comparator 9, the data is read in the main memory (not shown) outside the cache memory, sent to the MPU, and stored in the data block memory 7 in the cache memory. . At this time, the LRU algorithm determines in which way the data should be stored, and this information is stored in the LRU bit memory 8.

Next, a method of diagnosing the LRU bit memory 8 of this cache memory will be described. In this conventional example, it is not possible to directly write information to the LRU bit memory 8 from the outside, so in order to set the LRU bit memory 8 to the value that should be diagnosed, it is necessary to write the data in the main memory to the cache memory multiple times. It was necessary. In addition, in this conventional example, since it is not possible to directly read the stored information from the LRU bit memory 8 to the outside, it is necessary to confirm that the stored information in the LRU beat/beat memory 8 is set to a desired value.
In order to recognize IiI, it was necessary to read data from the cache memory multiple times and write data from the main memory to the cache memory multiple times.

As described above, the conventional method for diagnosing the LRU bit memory 8 has been to judge the quality of the memory 8 through indirect observation, since direct reading and writing of the LR (J bit memory 8) is impossible.

[Problem to be solved by the invention]

In order to diagnose the LRU bit memory 8 of the conventional set associative cache memory, information cannot be directly written to the LRU bit memory 8 from the outside, so in order to set the LR [J bit memory 8 to the value to be diagnosed However, there was a problem in that the data in the main memory had to be written to the cache memory multiple times.

In addition, in order to diagnose the LRU bit memory 8 of the conventional set associative cache memory, the LR
Since stored information cannot be directly read externally from the U bit memory 8, in order to confirm that the stored information in the LRU bit memory 8 is set to the desired value, multiple read operations from the cache memory are required. There was a problem in that it was necessary to write the data in the main memory to the cache memory multiple times.

The present invention has been made in view of the above points, and its purpose is to enable direct reading and writing of information stored in the LRU bit memory in the diagnostic mode of the LRU bit memory of the set associative cache memory. Therefore, it is an object of the present invention to provide a method for diagnosing a set associative type cache memory that is easy to diagnose.

[Means to solve the problem]

In order to solve such problems, the present invention provides an N-way set associative type cache memory that, in the diagnostic mode, reads out the storage information of the data replacement priority storage means of each way, and The apparatus is configured to generate at least one signal for permitting information to be written to the storage means.

[Effect]

In the diagnostic method according to the present invention, in the N-way set associative cache memory, in the diagnostic mode,
By generating one signal and specifying a set select to permit reading out the storage information of the data replacement priority storage means of each way, the memory corresponding to the set selection of the replacement priority storage means is generated. Read information.

Further, in the N-way set associative cache memory, in the diagnostic mode, by generating at least one signal to permit writing of information into the data replacement priority storage means of each way and specifying set selection, Information is written to a storage location corresponding to the set selection in the replacement priority storage means.

〔Example〕

A method for diagnosing a set associative cache memory according to the present invention will be described below with reference to FIG. FIGS. 1(a) and 1(b) are an address configuration diagram and a block diagram of a four-way set associative cache memory for explaining a conventional method of diagnosing a sent associative cache memory. In Figure 1,
21 is a control register that generates a control signal TEST and a control signal RW, and 22 is a control circuit that controls reading of stored information from the LRU bit memory 8 and writing of information to the LRU bit memory 8 using the control signal TEST and the control signal RW. In this figure, the same or corresponding parts as in FIG. 2 are given the same reference numerals.

Next, the operation will be explained. The normal operation of the four-way set associative cache memory shown in FIG. 1 (bl) is exactly the same as the operation of the conventional cache memory shown in FIG. The diagnostic operation of the LRU bit memory 8 in the diagnostic mode will be explained.

First, the operation of writing information to the LRU bit memory 8 will be described. To write information to the LRU bit memory 8 in the diagnostic mode', the control signal TEST is set to "11" and the control signal RW to "0" by the control register 21.The control signal TEST is set to "1". When the cache memory is set to the diagnostic mode, the control signal RW allows reading of stored information from the LRU bit memory 8 when it is "I" in the diagnostic mode, and allows reading of stored information from the LRU bit memory 8 when it is "0" in the diagnostic mode. By setting the control signal in this way and specifying set select 3, the information to be written to the LRU bit memory 8 is the information specified by set select 3 through control diagram B22. It is written to the LRU focus memory 8.

Next, the operation of reading information from the LRU via memory 8 will be explained. To read information from the LRU focus memory 8 in the diagnostic mode, the control register 21 sets the control signal TEST to "1" and the control signal RW to "1". By setting the control signal in this way and specifying the set select 3, the storage information of the LRU focus memory 8 specified by the front select 3 is transferred to the control circuit 22.
read out through

The method of diagnosing a cache memory according to the present invention is particularly effective when diagnosing a cache memory in a cache memory configured with an integrated circuit or in a microprocessor configured with an integrated circuit including a cache memory.

Further, in FIG. 1, the control signals RW and TEST are output from the control register 21, but they can also be provided from outside the cache memory.

[Effects of the Invention] As described above, according to the present invention, in the diagnosis mode of the replacement priority storage means of a set associative cache memory, set select is specified and information stored in the replacement priority storage means is read and Writing allows direct reading and writing of the information stored in the replacement priority storage means, which has the effect of facilitating diagnosis of the set associative type cache memory.

[Brief explanation of the drawing]

FIGS. 1A and 1B are an address configuration diagram and a system diagram of a set associative cache memory for explaining an embodiment of the diagnostic method according to the present invention, and FIGS.
a) and (bl) are an address configuration diagram and a system diagram of a set associative cache memory for explaining a conventional diagnostic method. 1...Address, 2...Address tag, 3...Set select, 4... Word select, 5... Address configuration diagram, 6... Balint bit memory, 7...
...Data block memory, 8...LRU bit memory, 9...Address tag comparator, 10.11...Selector, 21...Control register, 22...Control circuit.

Claims (1)

[Claims] In an N-way set associative type cache memory where N is a natural number of 2 or more, in the diagnostic mode, reading the information stored in the replacement priority storage means for data of each way and transmitting information to the replacement priority storage means. By generating at least one signal to permit writing of the information and specifying a set select, reading of the stored information corresponding to the set select of the replacement priority storage means and writing to a storage location corresponding to the set select is performed. A method for diagnosing an N-way set associative cache memory, comprising writing the information.