JP2821326B2 - Cache memory failure detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system used in the field of information processing, and more particularly to a failure detection device for detecting a failure in a tag memory circuit or a comparison circuit of a cache memory during operation.

[0002]

2. Description of the Related Art Conventionally, in a cache memory failure detection apparatus of this kind, writing and reading of the tag memory circuit storing the address management tag information of the cache memory by the failure diagnosis information from the self-diagnosis apparatus are performed. A failure detection method has been adopted. FIG. 5 shows an example of a cache memory provided with such a self-diagnosis device.
In the figure, 1 is a CPU, 2 is a main storage device, 3 is an input / output device, 4 is an address latch circuit, 13 is a cache data memory circuit, 38 is a tag memory circuit, 10 is a comparison circuit, and 16 is a system bus. . 14 is an address bus, 15 is a data bus, 17 is upper bit information of address information, 18 is a part of the address information, 33 is a failure signal, and 34 is a response signal.

The self-diagnosis device 44 includes an information generation circuit 6 for generating failure diagnosis information, a write control signal 42 for writing failure diagnosis information to the tag memory circuit 38, and the failure diagnosis information written to the tag memory circuit 38. A diagnostic control circuit 41 for outputting a read control signal 43 for reading, a counter circuit 5 for sequentially designating write and read target positions in the tag memory circuit 38, and a failure diagnosis for writing to the tag memory circuit 38 The self-diagnosis comparison circuit 39 compares the information and the failure diagnosis information read from the tag memory circuit 38, and the flag circuit 40 stores the accumulated result of the self-diagnosis comparison circuit 39.

The operation of the self-diagnosis device in the cache memory is such that failure diagnosis information is output from the information generation circuit 6 in a state separated from the configuration of the cache memory system,
In response to the position of the address management tag information 27 of the tag memory circuit 38 indicated by the counter circuit 5, the write control signal 4 from the diagnostic control circuit 41 to the tag memory circuit 38
2, writing with the failure diagnosis information is executed, and the writing is performed for all positions of the tag memory circuit 38. After the execution of the writing, the failure diagnostic information written in all the positions of the tag memory circuit 38 indicated by the counter circuit 5 is read by the read control signal 43 from the diagnostic control circuit 41 to the tag memory circuit 38 so that the tag memory circuit 38 The written fault diagnosis information is sequentially read from all positions. The read failure diagnosis information and the failure diagnosis information at the time of writing are sequentially input to the self-diagnosis comparison circuit 39, and the accumulated information of the result information from the self-diagnosis comparison circuit 39 is stored in the flag circuit 40. Is done. Based on the information in the flag circuit 40, the occurrence of a failure in the tag memory circuit 38 is determined.

[0005]

In the conventional cache memory failure detection device described above, the self-diagnosis device detects failures at all positions of the tag memory circuit, but the self-diagnosis function operates. When writing or reading is performed on the tag memory circuit of the cache memory based on the failure diagnosis information, the address management tag information of the tag memory circuit during a normal cache operation is rewritten. Since the correspondence with the cache data memory circuit becomes inconsistent, it can be implemented only in a state separated from the cache memory system configuration. Further, there is a problem that it takes a lot of test time to complete writing and reading for failure detection with respect to all address management tag information positions in the tag memory circuit. An object of the present invention is to provide a failure detection device that can detect a failure in a cache memory without interrupting the operation of the cache memory system.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a first memory area of a tag memory circuit designated by a counter circuit during a period of data replacement from a main storage device to a cache data memory circuit due to a mishit in a cache memory. Reading the address management tag information at the position, temporarily storing the address management tag information in the second memory area of the tag memory circuit, writing the failure diagnosis information at the position designated by the counter circuit, and writing at the write position. By reading out information and comparing each of them, a failure can be detected. After the failure detection, the address management tag information stored in the second memory area of the tag memory circuit is stored in the first memory area of the tag memory circuit. By doing so, the correspondence between the tag memory circuit and the cache data memory circuit is established, and the operation can be resumed without interrupting the cache operation. Further, the position of the address management tag information of the tag memory circuit to be subjected to the failure detection is sequentially executed by the counter circuit over all the positions of the address management tag information, and is equal to the number of the address management tag information of the tag memory circuit. If the replacement occurs, all the inspections can be performed. In addition, the test time for failure detection operates in parallel with the data replacement period from the main storage device to the cache data memory circuit, so that a special test time is unnecessary compared to the test time by the self-diagnosis device. .

[0007]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, parts equivalent to those of the conventional configuration in FIG. 5 are denoted by the same reference numerals. In contrast to the conventional configuration, in this embodiment, the control means 7, the index selection circuit 8, the tag selection circuit 9,
A comparison circuit 11 is provided. Also, the tag memory circuit 12
Is composed of a first memory area 36 and a second memory area 37. In the first memory area 36, writing and reading of information are performed by the write signal 24 and the read signal 23. Information is written to and read from the second memory area 37 by the write signal 27 and the read signal 26.

Next, the specific operation of FIG. 1 will be described. First, the address information of the CPU 1 is stored in the address latch circuit 4 via the address bus 14. Output information from the index selection circuit 8 (hereinafter referred to as index information 21) to which a part of the address information 18 stored in the address latch circuit 4 is input is input to the tag memory circuit 12, and the first memory area Search in 36,
The address management tag information 27 is read. The read address management tag information 27 and the output information from the tag selection circuit 9 (hereinafter referred to as access tag information 22) are compared in the comparison circuit 10. As a result, the request data of the CPU 1 is obtained from the comparison result information 28. It is determined whether the data exists on the cache data memory circuit 13.

When the comparison between the address management tag information 27 and the access tag information 22 from the tag selection circuit 9 matches, since the requested data of the CPU 1 exists on the cache data memory circuit 13, the output circuit 11 A read signal 29 and a response signal 34 to the CPU 1 are output to the cache data memory circuit 13. The cache data memory circuit 13 outputs C
The request data of PU1 is output to data bus 15. On the other hand, the CPU 1 receiving the response signal 34 receives the data to be sought from the data bus 15 and ends the operation.

However, when the comparison between the address management tag information 27 and the access tag information 22 from the tag selection circuit 9 shows a result of mismatch, the position of the address management tag information specified by the index information 21 is replaced. The data block in a fixed unit including the requested data of the CPU 1 from the main storage device 2 is stored in the cache data memory 13 corresponding to the position of the address management tag information through the system bus 16 a plurality of times. Writing is performed by a cycle. These operations and the operation of the cache failure detection device according to the present invention are shown in the flowcharts of FIGS.

In parallel with the replacement operation to the cache data memory circuit 13, the control means 7 started when the comparison result information 28 from the comparison circuit 10 indicates a mismatch.
Is a counter circuit which outputs the invalidation signal 30 for fixing the output of the response signal 34 to the CPU 1 to the output circuit 11 and the index information 21 from the index selection circuit 8 to a part of the information 18 of the address information of the CPU 1 5 is output to the output information 19 side. Then, in the index selection circuit 8, a read signal 23 from the control means 7 to the first memory area 36 is output to the position of the address management tag information specified by the output information from the counter circuit 5, and the read signal is read. The address management tag information stored in the tag memory circuit 12 is stored in the second
The data is input to the memory area 37 and stored by the write signal 26 output from the control means 7.

In the tag selection circuit 9, the CPU 1
The control unit 7 outputs a switching signal 32 for selecting the failure diagnosis information 20 side of the information generating circuit 6 from the information 17 of the upper bits of the address information. Index information 2
1 writes the access tag information 22 from the tag selection circuit 9 to the position of the first memory area 36 of the tag memory circuit 12 designated by 1 by the write signal 24 from the control means 7 to the first memory area 36. Is carried out. After the execution of the writing, the control means 7 sends the first memory area 3 to the position of the tag memory circuit 12 where the writing has been executed.
6 is output, and the address management tag information is read from the first memory area 36.

A comparison circuit 1 compares the read address management tag information 27 with the written access tag information 22.
0, and the comparison result information 28 is stored in the control unit 7.
Output to The comparison result information 28 is stored in the tag memory circuit 1
If a match is indicated by the address management tag information from No. 2 and the written access tag information, it can be determined that no failure has occurred, and the failure detection operation ends normally. When the operation of the failure detection is completed, a read signal 23 for outputting the address management tag information stored in the second memory area 37 of the tag memory circuit 12 to the first memory area 36 is output from the control means 7, The write signal 24 for writing the address management tag information to the first memory area 36 of the tag memory circuit is output from the control means 7, and the first memory of the tag memory circuit 12 from which the access tag information has been read before is output. It is stored at the position of the area 36.

The index information 21 from the index selection circuit 8 is converted into the output information 19 from the counter circuit 5 by a switching signal 31 output from the control means 7.
Side to the part of the address information 18 of the CPU 1 and the access tag information 22 of the tag selection circuit 9.
Is switched to the information 17 on the upper bit side of the address information of the CPU 1 by the switching signal 32 output from the control means 7, and the failure detection operation is completed. Upon termination of the failure detection operation, the invalidation signal 30 from the control means 7 to the output circuit 11 is released.

When the replacement of data from the main storage device 2 to the cache data memory circuit 13 is completed, the access tag information 22 output from the tag selection circuit 9 is replaced with the replacement position of the first memory area 36 of the tag memory circuit 12. And a response signal 34 to the CPU 1 is output from the output circuit 11 and a read signal 29 is output to the cache data memory circuit 13 by the output circuit 11.
Output more. Thereby, the CPU 1 receives the requested data via the data bus 15. Here, the output circuit 11 receives the comparison result information 28 from the comparison circuit 10 and the invalidation signal 30 from the control means 7, and outputs the response signal 34 to the CPU 1 and the cache data memory circuit 13. With the read signal 29, the invalidation signal 3
By 0, the output signals of the response signal 34 and the read signal 29 to the cache data memory circuit are invalidated.

On the other hand, if the access tag information 22 from the tag selection circuit 9 does not match the read address management tag information 27 according to the comparison result information 28 of the comparison circuit 10, the control unit 7 sends a failure signal. 33 is output and C
PU1 is notified. And stop the replacement operation,
The switching signal 31 is sent to the index selection circuit 8.
And the tag selection circuit 9 selects and outputs the information 17 side of the upper bit of the address information of the CPU 1 to the tag selection circuit 9 by the switching signal 32. If the output information of the counter circuit 5 is read out to the outside, it is possible to detect the position where the failure occurs in the tag memory circuit 12.

In the above failure detection device, the failure can be easily detected by writing the diagnostic information generation into the address management tag information of the tag memory circuit 12 by the above-described failure detection, and the comparison circuit can be easily detected. A fault at 10 can also be detected. Here, by changing or repeatedly executing the value of the failure diagnosis information, it is possible to detect a fixed failure of 1 or 0, a transition failure from 1 to 0 or 0 to 1, and the like. Also, the tag memory circuit 1
2 are sequentially subjected to the failure detection test, the failure detection can be performed very efficiently with respect to the address management tag information, and the time required for the failure detection is transferred from the main storage device 2 to the cache data memory circuit 13. Since the operation is performed in parallel with the data replacement period, the test time is not particularly necessary.

If these relationships are shown by specific numerical values, the size of one block in the cache data memory circuit 13 is 32 bytes, and the amount of data transferred from the main storage device 2 to the cache data memory circuit 13 is 2 clocks. If 4 bytes per cycle, the number of clocks required to replace the cache data memory circuit 13 is the value obtained by dividing the block size of 32 bytes by the transfer amount per cycle of 4 bytes and multiplying the number of clocks per cycle by 2 clocks. Requires a total of 16 clocks. On the other hand, the number of clocks required for detecting a failure in the cache memory is two clocks for storing data from the first memory area 36 of the tag memory circuit 12 to the second memory area 37, and the number of clocks required for the first memory area 36 of the tag memory circuit 12 is two. 4 clocks for failure detection, 2 for storage from the second memory area 37 to the first memory area 36
A total of 10 clocks are required in consideration of the case where two clocks are used to store the clock and the address information where the cache mishit has occurred in the tag memory circuit. Therefore, it is sufficiently possible to operate the failure detection diagnosis in parallel during the replacement period with the cache data memory circuit 13.

Therefore, during the data replacement period,
By performing failure detection by writing and reading at the position of the address management tag information specified by the counter circuit 5, the tag memory circuit 12 and the comparison circuit 1
This makes it possible to execute the detection of a failure with 0 during the operation of the system, and the reliability of the cache memory system itself can be greatly improved. In the present invention, the address management tag information at the position where the failure detection is performed is temporarily saved in the second memory area 37 of the tag memory circuit 12, and is stored in the first memory area 36 of the tag memory circuit 12 when the failure detection is completed. Since the data is written back, the tag memory circuit 12 and the cache data memory circuit 13 can be consistent with each other without any problem, and can be executed without interruption of operation due to failure detection.

FIG. 4 is a block diagram of a second embodiment of the present invention. This embodiment is a cache memory system having two associative units, and has two tag memory circuits 12a and 12b and two tag memory circuits 1a and 12b.
This embodiment differs from the above embodiment in that two cache data memory circuits 13a and 13b corresponding to 2a and 12b are provided. Note that the tag memory circuits 12a and 12b include:
First memory areas 36a and 36b and second memory areas 37a and 37b are provided, respectively.

The basic operation of this embodiment is the same as that of the first embodiment, but has two associative units.
When the tag memory circuits 12a and 12b are searched based on the address information, and a mismatch occurs along with the comparison result, one of the two associative unit tag memory circuits 12a and 12b is selected as a replacement target. In the case of the fault detection of the present invention, the first memory area 3 of the tag memory circuits 12a and 12b is simultaneously used for two associative units.
Since it is possible to store data in the second memory areas 37a and 37b from the memory cells 6a and 36b and to simultaneously perform writing and reading based on the failure diagnosis information, it is possible to determine failure diagnosis at the same time. As a result, in order to check all the tag memory circuits 12a and 12b, it is only necessary to implement the number corresponding to one associative unit, which is very efficient.

In the case of this embodiment, since the degree of freedom for storing the address management tag information is increased by using a cache memory configuration of two associative units, the hit rate in the cache memory system can be further improved. Although it is possible, on the other hand, the need for reliability is particularly problematic due to the more complex structure, but high reliability can be obtained with the present invention.

[0023]

As described above, according to the present invention, in the cache memory system, when the inside of the tag memory circuit is searched by the address information of the CPU and the comparison result indicates that no matching address management information exists, At the position indicated by the counter circuit, the address management tag information is temporarily stored in the second memory area of the tag memory circuit, and the writing and reading based on the failure diagnosis information from the information generating circuit are performed and read. Based on the result of comparison with the failure diagnosis information, it is easy to detect a failure in the cache tag memory circuit and a failure in the comparison circuit.This operation does not need to be performed separately from the normal cache operation. Can be performed. Further, after the failure diagnosis is performed, the address management tag information is rewritten from the temporarily stored second memory area of the tag memory circuit to a position before the first memory area of the tag memory circuit, whereby
Correspondence between the tag memory circuit and the cache data memory circuit thereafter can be established, and the operation can be performed without interrupting the operation. Further, since the tag memory circuit has the same cell configuration as the first memory area and the second memory area, the circuit scale for failure detection can be reduced.

Therefore, when replacement by cache mishit occurs for the number of address management tag information in the tag memory circuit, it is possible to carry out the replacement equally over all of the tag memory circuits. In a cache system having a plurality of associative units, faults can be detected in each of the associative units at the same time. Fault detection can be performed. As described above, since the failure detection is sequentially performed during the cache mishit period for the tag memory circuit, the failure detection becomes very efficient, and high reliability can be easily obtained. In addition, since this failure detection operation is performed in parallel with the data replacement operation from the main storage device to the cache data memory circuit, no time is particularly required for failure detection. Therefore, it is possible to greatly contribute to improvement in reliability in configuring a cache memory system.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a first flowchart illustrating the operation of FIG. 1;

FIG. 3 is a second flowchart illustrating the operation of FIG. 1;

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of an example of a conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Main storage device 3 I / O device 4 Address latch circuit 5 Counter circuit 6 Information generation circuit 7 Control means 8 Index selection circuit 9 Tag selection circuit 10 Comparison circuit 11 Output circuit 12, 12a, 12b Tag memory circuit 13, 13a, 13b cache data memory circuit 14 address bus 15 data bus 16 system bus

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 12/16 G06F 11/22 350 G06F 12/08

Claims (1)

(57) [Claims] 1. A cache memory system, comprising: an information generation circuit for outputting failure diagnosis information; a counter circuit for outputting information on a position where a failure diagnosis is to be performed; A tag selection circuit for inputting the failure diagnosis information of the above, an index selection circuit for inputting a part of the address information of the CPU and the output information from the counter circuit, and address management of the output information from the tag selection circuit A tag memory circuit that stores the tag information and takes it out, temporarily stores it, and stores it again; a comparison circuit that inputs the output information of the tag selection circuit and the address management tag information extracted from the tag memory circuit; An output circuit for receiving the result information of the comparison circuit and transmitting a response signal to the CPU;
Control means, wherein the tag memory circuit stores output information from the tag selection circuit as address management tag information, and retrieves the stored address management tag information, and stores the information in the first memory area. And a second memory area for temporarily storing the temporarily stored address management tag information in the first memory area. At the time of data replacement from the storage device to the cache data memory circuit, the result information from the comparison circuit is input, and the switching signal to the index selection circuit, the switching signal to the tag selection circuit, and the first memory area of the tag memory circuit Read signal, a write signal to the first memory area of the tag memory circuit, and a second memo of the tag memory circuit. Read signal to the region, a second write signal to the memory area of the tag memory circuit, a control signal, disabling signal to the output circuit to the counter circuit, and a CPU
A failure signal for outputting a failure signal to a cache memory.