JP3060825B2 - Semiconductor integrated circuit and inspection method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a test method therefor, and more particularly to a semiconductor integrated circuit capable of self-diagnosis and a test method therefor.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit having a built-in memory,
In addition to the test of the logic part, disconnection of the memory cell of the memory part,
It is necessary to confirm whether there is a failure in the address selection, read and write functions due to device defects such as short circuit and capacitance coupling.

In this memory test, it is necessary to give an address and data to the memory unit by some method, read data written after a write operation, and compare the read data with the written data (expected value). .

The address and data are supplied to the memory section by (1) a method of using an address terminal and a data terminal to supply the data from outside the semiconductor integrated circuit at the time of memory inspection, and (2) a method of generating an address. And a method of providing a data generation unit (also referred to as a test sequence generation unit) inside a semiconductor integrated circuit.

In particular, in the method (2), in addition to the address generating means and the data generating means, means for determining read data is added, or the data generating means and the response compressing means are combined, and the compression result determining means is used. In some cases, the self-diagnosis of the memory unit is enabled by providing a memory.

[0006]

However, in the above-mentioned method (1), a device for generating an address and data externally is required, and it is necessary to prepare a test program for providing the address and data. Further, a bus for supplying an address from the address terminal to each memory must be newly provided. Further, in a semiconductor integrated circuit having a plurality of memories therein, it is difficult to perform tests on these memories in parallel, so that it takes time to perform the tests. After the semiconductor integrated circuit is incorporated in the system, it is difficult to use this inspection method, so that there is a drawback that the test of the memory unit is only a functional test.

In the above method (2), it is not necessary to newly provide a bus as in (1). However, even if an existing address latch is used as the address generating means, the data generating means and the response compressing means can be used. It is necessary to provide a memory for each memory. Particularly, in a semiconductor integrated circuit having a plurality of memories, the increase of the total hardware becomes large on the semiconductor integrated circuit. Since it is necessary to provide a means for judging the compression result, the area of the semiconductor integrated circuit is increased, and there is a problem that the price increases and the yield decreases.

Accordingly, the present invention has been made in view of the above problems, and in a semiconductor integrated circuit incorporating a plurality of memories, a bus to which a memory is connected is used at the time of testing a memory. An object of the present invention is to provide a semiconductor integrated circuit and a test method which can perform a self-diagnosis at a high speed by connecting a comparing means.

[0009]

In order to achieve the above-mentioned object, according to the present invention, a plurality of buses to which at least one memory is connected, and a bus which is connected to all the buses and has a Data generation means for supplying pattern data that becomes write pattern data to the target memory and pattern data that becomes an expected value to the memory to be read, and a memory to be read from the plurality of buses are connected. A bus is selected and data read from the memory to be read is used as a first input, and a bus other than the bus selected by the first input is selected and an expected value output by the data generation means is set to a first input. And a data comparing means for comparing the first and second input data and outputting the comparison result.

[0010] The means taken by the invention of claim 3 is claim 1.
The invention further comprises N-1 bus switches for dividing one bus to which N or more memories are connected into N buses, and wherein the data comparing means is divided into N buses. This is a configuration provided for each bus.

[0011] The means adopted by the invention of claim 4 is claim 1.
In the invention, when a bus width of any two buses input to the data comparison unit is smaller than a bit width of the data comparison unit, a plurality of buses are selected as one input, and a bus of the selected plurality of buses is selected. If the sum of the widths is still less than the bit width of the data comparing means, the data comparing means has a function of masking a portion where no data is placed according to the bus width.

The measures taken by the invention of claim 5 are the following:
An instruction cache including a data memory and a tag memory, wherein one of the plurality of buses is an instruction bus, and a memory connected to the instruction bus employs either a direct map or a set associative method. Wherein the data comparison means uses the data read from the data memory to the instruction bus as a first input, and the expected value output from the data generation means to a bus other than the instruction bus as a second input. Tag comparison means for outputting the comparison result, using the data read from the tag memory as a first input, the tag portion of the address for accessing the instruction cache as a second input, and outputting the comparison result; A comparison result storage unit for storing pass / fail judgment information output from the plurality of comparison units. That.

[0013] The means taken by the invention of claim 6 is claim 1.
A data cache having a data memory and a tag memory, wherein one of the plurality of buses is a data bus, and a memory connected to the data bus adopts either a direct map or a set associative method. Wherein the data comparison means uses data read from the data memory to a data bus as a first input, and the expected value output from the data generation means to a bus other than the data bus as a second input. A tag comparing means for outputting the comparison result, using the data read from the tag memory as a first input, a tag portion of an address for accessing a data cache as a second input, and outputting the comparison result, And comparison result storage means for storing the pass / fail judgment information output from the comparison means. It is intended.

The measures taken by the invention of claim 7 are the following:
In the invention, the plurality of buses include an instruction bus and a data bus, and a data memory of an instruction cache and a data memory of a data cache are connected to the instruction bus and the data bus, respectively.

The measures taken by the invention of claim 8 are the following.
Alternatively, in the invention according to the sixth aspect, a selector for selecting a tag portion of an address to access the cache in a normal state and selecting data on a bus output from the data generating means when checking the tag memory is provided.

According to a ninth aspect of the present invention, at the time of writing to the memory, the data generation means outputs write pattern data to all the buses connected to the memory, so that the plurality of buses connected to each of the buses are output. Performing one of the plurality of buses as the first input of the data comparing means during the process of performing parallel writing to the memory and the first input of the data comparing means at the time of the memory read inspection, and as the second input of the data comparing means A bus other than the bus selected as the first input is selected, data read from a memory connected to the bus is output as the first input, and output of the data generating means is output as the second input. By providing the expected value, a process for comparing the read data with the expected value is provided.

According to an eleventh aspect of the present invention, in the ninth aspect of the present invention, one bus in which at least N or more memories are connected by N-1 bus switches is reduced to N buses. The write pattern data output to the bus by the data generating means is written in parallel to the N or more memories, and the bus is divided for read inspection to divide the bus.
And outputs the read data from the memories to the N divided buses, and inputs the read data as a first input of N data comparison means provided for each of the divided buses. By inputting the expected value output from the data generating means as the input 2, the reading inspection of the N memories is performed in parallel.

In a twelfth aspect of the present invention, in the ninth aspect of the present invention, when the bus selected as the first input of the data comparing means is smaller than the bit width of the data comparing means, the connection of the memory is performed. By simultaneously selecting the plurality of buses as the first input, the operations of reading out the memories connected to the plurality of buses and comparing with the expected value are performed in parallel.

The means adopted by the invention of claim 13 is the invention according to claim 9, wherein one of the plurality of buses is an instruction bus, and the instruction bus is either a direct map or a set associative system. The data memory of an instruction cache having a data memory and a tag memory is connected, and the quality of the data memory is determined by using data read from the data memory to an instruction bus as a first input, and An expected value output to a bus other than the bus is compared as a second input by the data comparing means, and the acceptability of the tag memory of the instruction cache is determined by using the data read from the tag memory as a first input. By comparing the tag part of the address for accessing the cache with the tag comparing means having the second input, The read / write check of the data memory and the tag memory of the instruction cache is performed in parallel by inputting the pass / fail judgment information output from the respective data comparison means and the tag comparison means to the comparison result storage means. is there.

According to a fourteenth aspect of the present invention, in the ninth aspect of the present invention, one of the plurality of buses is a data bus, and any one of a direct map and a set associative system is used for the data bus. The data memory of a data cache having a data memory and a tag memory is connected, and the quality of the data memory is determined by using data read from the data memory to a data bus as a first input, and An expected value output to a bus other than the bus is compared as a second input by the data comparing means, and the quality of the tag memory of the data cache is determined by using the data read from the tag memory as a first input. Tag comparison means using the tag part of the address accessing the cache as the second input By inputting the pass / fail judgment information output from the respective data comparing means and the tag comparing means to the comparison result storing means, the reading inspection of the data memory and the tag memory of the instruction cache is performed in parallel. It was done.

According to a fifteenth aspect of the present invention, in the invention of the thirteenth or fourteenth aspect, a tag portion of an address for accessing a cache is selected in a normal state, and a bus output from the data generating means when a tag memory is inspected. A selector for selecting the above data, and by inputting the output of the selector to the tag memory and the tag comparing means, the write data at the time of inspection of the tag memory or the expected value used for comparison with the tag is written to the data memory. Alternatively, it can be shared with the expected value.

The means adopted by the invention of claim 16 is the invention according to claim 9, wherein the writing pattern data is output from the data generation means to all the buses connected to the memory at the time of writing to the memory. And simultaneously selecting one of the plurality of buses as the first input of the data comparing means, and performing the parallel writing to the plurality of memories connected to each of the data comparing means. By selecting a bus other than the bus selected as the first input, and comparing the pattern data output to the first input with the second input and output by the data generating means. And performing a process of detecting a failure in the bus wiring, and performing one of the plurality of buses as a first input of the data comparing means during a memory read test. A bus is selected, and a bus other than the bus selected as the first input is selected as a second input of the data comparison means, and the first input is a data read from a memory connected to the bus. A process for comparing the read data with the expected value by supplying an expected value output from the data generating means to the second input.

The means of the invention according to claim 17 is the invention according to claim 11, wherein the bus is not divided at the time of writing to the memory, and the data generation means outputs the write pattern data to the plurality of N or more data buses. At the same time as comparing the pattern data output from the data generating means as the first input and the second input of the N data comparing means provided for each of the divided buses. Detecting a failure for each of the divided bus wirings,
A process of identifying a fault location of the divided bus by comparing fault fault detection results for each bus wiring.

[0024]

According to the first aspect of the present invention, a plurality of buses to which one or more memories are connected, and write pattern data for the memories to be written and connected to all the buses, become the write pattern data, and A data generating means for supplying pattern data as an expected value, and selecting a bus to which a memory to be read is connected from the plurality of buses, and reading data read from the memory to be read. A data which selects a bus other than the bus selected by the first input as the first input, sets the expected value output from the data generating means as the second input, compares these two input data, and outputs the comparison result By providing the comparing means, the self-diagnosis of the memory can be performed without giving an address or data from outside the semiconductor integrated circuit.

According to a third aspect of the present invention, in addition to the first aspect of the present invention, a single bus to which a plurality of memories are connected so that a plurality of N or more memories can be read in parallel is provided. N-1 bus switches are provided for each of the N divided buses so that the data read in parallel and the expected value can be compared in parallel. By providing the comparing means, the read operations of the plurality of memories can be checked in parallel, and the speed of the self-diagnosis of the memories can be increased.

According to a fourth aspect of the present invention, in addition to the first aspect, when the bus width of any two selected buses input to the data comparing means is smaller than the bit width of the data comparing means, Select multiple buses as one input,
When the bit width of the data comparison means is less than the bit width, the data comparison means is provided with a function of masking a portion where no data is placed according to the bus width, so that a memory having a different bit configuration connected to a different bus has a read operation. Can be tested in parallel.

According to a fifth aspect of the present invention, in the first aspect of the present invention, one of the plurality of buses is an instruction bus, and the instruction bus adopts any of a direct map and a set associative system. The data memory of the cache is connected, and the pass / fail judgment of the data memory is performed by using the data read from the data memory to the instruction bus as a first input and the expected value output from the data generation means to a bus other than the instruction bus as a second input. Of the tag memory is determined by comparing the data read from the tag memory with the first data.
And a comparison result storage unit for storing pass / fail judgment information output from each comparison unit by comparing a tag portion of an address for accessing the instruction cache as an input of the comparison unit by a tag comparison unit as a second input. This makes it possible to perform read inspection of the data memory and the tag memory of the instruction cache in parallel.

According to a sixth aspect of the present invention, in the first aspect of the present invention, one of the plurality of buses is a data bus, and the data bus adopts either a direct map or a set associative system. The data memory of the cache is connected, and the pass / fail judgment of the data memory is performed by using the data read from the data memory to the data bus as a first input and the expected value output to the bus other than the data bus by the data generating means as a second input. The quality of the tag memory is determined by comparing the data read from the tag memory as the first input and the tag portion of the address for accessing the data cache as the second input. Pass / fail judgment information that is obtained by comparison by comparing means and output from each comparing means. Read test data memory and the tag memory of the data cache by providing a comparison result storage means for storing it can be performed in parallel.

According to a seventh aspect of the present invention, in the first aspect of the present invention, the plurality of buses include an instruction bus and a data bus, and the data memory and the data of the instruction cache connected to the instruction bus and the data bus, respectively. Self-diagnosis of the data memory of the cache can be performed.

According to an eighth aspect of the present invention, in the fifth and sixth aspects of the present invention, the tag portion of the address for accessing the cache is selected in a normal state, and the data on the bus output from the data generating means at the time of checking the tag memory. Selector, and the output of the selector is connected to the tag memory and the tag comparing means, so that the write data at the time of inspection of the tag memory or the expected value used for comparison with the tag are compared with those of the data memory. Since the data can be shared, the write data generating means and the expected value generating means for the tag memory become unnecessary.

According to a ninth aspect of the present invention, in the same manner as in the first aspect of the present invention, the write pattern data is output from the data generating means to all the buses connected to the memory at the time of inspection of the memory, so that Performs a parallel write to a plurality of memories connected to each other, and selects one bus from the plurality of buses as a first input of the data comparison means during a memory read check, thereby performing a first input. A bus other than the bus selected as the first input is selected, and as the second input, data obtained by reading a memory connected to the bus is provided as the first input. By comparing the read data with the expected value by supplying the expected value to be output, the memory self-diagnosis can be performed without giving an address or data from outside the semiconductor integrated circuit. Playable.

According to an eleventh aspect of the present invention, in addition to the ninth aspect of the present invention, one bus in which at least N or more memories are connected by N-1 bus switches is connected to the N bus.
The write pattern data output to the bus by the data generation means is written in parallel to the N or more memories in parallel when writing data to the memory, and the bus is divided during read inspection. The data read out from the N memories to the N divided buses are output, and N data provided for each of the divided buses are output.
By inputting the read data as the first input of the data comparing means and inputting the expected value output by the data generating means as the second input, the reading inspection of the N memories is performed in parallel. The writing and reading inspections of the N or more memories can be executed in parallel, and the speed of the self-diagnosis of the memories can be increased.

According to a twelfth aspect of the present invention, when the bus selected as the first input of the data comparing means is smaller than the bit width of the data comparing means, the plurality of connected memories may be changed. By simultaneously selecting the bus as the first input, it becomes possible to perform reading of memories connected to different buses having different bit configurations and comparison operations with expected values in parallel, thereby speeding up the reading test.

According to a thirteenth aspect of the present invention, in the ninth aspect of the present invention, one of the plurality of buses is an instruction bus, and the instruction bus adopts any of a direct map and a set associative system. The data memory of the cache is connected, and the pass / fail judgment of the data memory is performed by using the data read from the data memory to the instruction bus as a first input, and the expected value output to the bus other than the instruction bus by the data generation means as a first input. The data is read by the tag memory as the first input, and the tag portion of the address for accessing the instruction cache is compared with the second input. The pass / fail judgment information output from each comparing means is compared by performing the comparison by the tag comparing means. It is possible to read out test by inputting the result storage means in parallel with the data memory and the tag memory, thereby speeding the reading test.

According to a fourteenth aspect of the present invention, in the ninth aspect of the present invention, one of the plurality of buses is a data bus, and the data bus employs either a direct map or a set associative system. The data memory of the cache is connected, and the pass / fail judgment of the data memory is performed by using the data read from the data memory to the instruction bus as a first input, and the expected value output from the data generating means to a bus other than the data bus as a first input. The input is input by comparing the data read out from the tag memory as the first input, and the tag portion of the address for accessing the data cache is compared with the second input. Pass / fail judgment by comparing the data with the tag comparing means. It becomes possible to perform the reading test by inputting the comparison result storage means for distribution in parallel with the data memory and the tag memory, thereby speeding the reading test.

According to a fifteenth aspect of the present invention, in the thirteenth aspect or the fourteenth aspect, a tag portion of an address for accessing a cache is selected in a normal state, and data on a bus output from a data generating means is checked when a tag memory is inspected. A selector for selecting the data, and inputting the output of the selector to the write port of the tag memory and the tag comparing means, so that the write data at the time of inspection of the tag memory or the expected value used for comparison with the tag are shared with those of the data memory. Therefore, the write data generating means and the expected value generating means for the tag memory become unnecessary.

According to a sixteenth aspect of the present invention, in the ninth aspect of the present invention, at the time of writing to the memory, the write pattern data is output from the data generating means to all the buses connected to the memory, thereby connecting to each of the buses. At the same time as performing the parallel writing to the plurality of memories, one bus is selected from the plurality of buses as the first input of the data comparing means, and the second bus is selected as the second input of the data comparing means. By selecting a bus other than the bus selected as the first input and comparing the first input with the pattern data output from the data generation means and applied to the second input, the selected bus wiring is selected. A process for detecting a failure is performed, and one of the plurality of buses is selected as a first input of the data comparison means during a memory read test. Then, a bus other than the bus selected as the first input is selected as the second input of the data comparison means, and the data read from the memory connected to the bus is selected as the first input. The second input is provided with a process of comparing the read data with the expected value by supplying the expected value output from the data generating means.

According to a seventeenth aspect of the present invention, in the invention of the eleventh aspect, at the time of writing to the memory, the bus is not divided and the write pattern data output to the bus by the data generation means is parallelized to the N or more memories. At the same time as the pattern data output from the data generating means as the first input and the second input of the N data comparing means provided for each of the divided buses.
Detecting a failure in each of the divided bus lines, and comparing the failure detection result of each of the bus lines to specify a failure location of the divided bus.

[0039]

【Example】

(Embodiment 1) A semiconductor integrated circuit incorporating a memory and an inspection method according to an embodiment of the present invention will be described below with reference to the drawings. The same numbers and symbols in the drawings used in the following description indicate the same elements throughout the drawings.

In the first embodiment, a method for inspecting a memory built in a semiconductor integrated circuit will be described. For simplicity, the instruction cache and the data cache have the same line size and number of lines. In FIG. 1, an external memory and a connection portion between the external memory and the semiconductor integrated circuit are omitted.

FIG. 1 is a configuration diagram of a semiconductor integrated circuit having a built-in memory according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an instruction cache employing a two-way set associative system, to which an instruction bus 100 is connected. The instruction cache 1 includes a first bank 12 and a second bank 13, and these banks have exactly the same configuration. To each bank, the address generation means 11 supplies an address for write or read access. The instruction address to be accessed is output from the CPU during normal operation, and the address generating means 11 operates as an address latch, and the address of access to each bank is supplied. These banks 12, 13
Is a data memory 14 for storing instructions and a tag memory 15
And an address decoder 17 for comparing the data read from the tag memory with the tag part of the address.

Reference numeral 2 denotes a data cache which employs a two-way set associative system similarly to the instruction cache 1, and is connected to a data bus 200. The data cache 2 includes a first bank 22 and a second bank 23, and these banks have exactly the same configuration. Each bank is supplied with an address accessed by the address generation means 21. The data address to be accessed is output from the CPU during a normal operation, and the address generating means 21 operates as an address latch, and an address for accessing each bank is supplied. These banks 22 and 23 are provided with a data memory 2 for storing data.
4, a tag memory 25, comparison means 26 for comparing the contents of the tag memory with the tag portion of the address, and an address decoder 27.
It is composed of

A bus control unit 3 connects the instruction bus 100 and the data bus 200 and performs the following three operations during normal operation. (1) When a miss occurs in the instruction cache 1, the bus control unit 3 reads an instruction from the external memory and outputs the instruction to the instruction bus 100. In instruction cache 1,
The instruction on the instruction bus 100 is written to the bank to be written. (2) If the data cache 2 misses due to a load instruction, the bus control unit 3 reads data from the external memory and outputs the data to the data bus 200. In the data cache 2, data on the data bus 200 is written to a bank to be written. (3) In the data cache 2 employing the write-through method, when writing data to an external memory by a store instruction, the bus control unit 3 outputs data on the data bus 200 to the external memory. In the data cache 2 adopting the write-back method, in order to reflect the data changed on the data cache to the external memory, the data cache 2 outputs the changed data on the data bus 200 at the time of context switch, and the bus control unit 3 outputs this data to an external memory.

Reference numeral 31 denotes a data generation unit, and 32 denotes a data comparison unit, both of which are connected to the instruction bus 100 and the data bus 200, and operate only when the memory is inspected. When the memory is inspected, the output of an instruction to the instruction bus 100 by the bus control unit 3 or the data bus 200
Since the output of data to the bus does not occur, a bus driver for driving each bus can be shared with the data generation unit 31.

Reference numeral 4 denotes a comparison result register which receives the comparison results from the data comparison means 32 and the tag comparison means in all the banks of the cache and stores all the self-diagnosis results in the data memory and the tag memory.

At the time of checking the memory, all of the data memories and the tag memories of the instruction cache 1 and the data cache 2 are subjected to writing and reading inspection.

FIG. 2 is a diagram for explaining a data pattern to be written to the memory according to the first embodiment of the present invention.

There are four types of data patterns used for memory inspection, as shown in FIGS. The memory shown in the figure is
Line size is 1 word (32 bits), number of lines is 6
4 and has a capacity of 256 bytes. The patterns in FIG. 2A are all 0, and the patterns in FIG. 2B are all 1. The pattern of (b) may be considered as a logical inversion of the pattern of (a). (c) is a checkerboard pattern in which 1s and 0s are alternately arranged in adjacent memory cells, and (d) is a checkerboard pattern in which 0s and 1s are alternately arranged.
May be considered as logically inverted. in this way,
In order to inspect the memory with four types of data patterns, four write operations are required for each memory.

If the number of lines is 64 and both the instruction length and the data length are fixed to words (32 bits), of the 32 bits of the logical address of this memory, the index part for selecting a line is 6 bits, and the tag part is The remaining 26 bits are used.

FIG. 3 is a flowchart for self-diagnosing the memory in the first embodiment of the present invention. The writing to all memories is performed in parallel, and the reading and comparison with the expected value are performed from the first bank 12 of the instruction cache 1 for each bank.

A method for easily and rapidly executing a self-diagnosis of a memory in a semiconductor integrated circuit having a memory configured as described above will be described with reference to FIGS. 1 and 2 based on a flowchart of FIG. .

First, in ST10, the data generating means 3
1 selects a data pattern in which all bits are 0 as the first data pattern, and selects all connected buses,
That is, it is output to the instruction bus 100 and the data bus 200.

In ST11, data patterns on the buses connected to these buses are written in parallel to the data memories 14 and 24 connected to these buses. Tag memory 1
In 5 and 25, the tag portions of the addresses output by the address generation means 11 and 21 are written in parallel. At the time of inspection of the memory, the tag portion of the address output from the address generation means 11 and 21 is the same as the data pattern output from the data generation means 31. In this case, the data pattern is such that all bits are 0. ing.

The index portion of the write address is generated by the respective address generating means 11 and 21 so as to be increased by one, and specifies the lines of the memory in ascending order. As a result, a data pattern in which all bits are 0 as shown in FIG. 2A is written in parallel to all of the data memory and the tag memory.

When the write operation for all the lines of the data memory and the tag memory is completed, the read operation and the comparison with the expected value are performed in ST12 and thereafter. The write operation was performed in parallel for all of the data memory and the tag memory, but the read and comparison operations were performed for each bank of one cache. This is because the expected value (the output of the data generation unit 31) is output to either the instruction bus 100 or the data bus 200, and the data read from the data memory of the bank to be tested is output to the other remaining bus. It is.

The operation of reading data from the data memory and comparing it with the expected value is performed by the data comparing means 32 having two buses as inputs.
This is performed by comparing the read data with an expected value.

The read operation of the tag memory and the operation of comparing the expected value are performed by the tag comparing means 16 or 26 by the data read from the tag memory and the address generating means 11 or 21.
Is compared with the tag portion of the address output by When inspecting the memory, the address generation means 1
The tag portion of the address output by 1 or 21 is the same as the data pattern output by the data generation means 31.

The index portion of the read address is set to 1 by the address generation means 11 as in the write operation.
The lines of the memory generated so as to increase by one are designated in ascending order.

In ST12, the expected value output from the data generating means 31 is placed on the data bus 200, and the instruction bus 1
At 00, the output of the data memory 14 of the first bank of the instruction cache 1 for executing the test is read. The expected value and the read data are compared by the data comparing means 32. If data that does not match the expected value is read from the data memory 14, the bit corresponding to the data memory 14 checked in the comparison result register 4 is set. And the data memory 1
4 has a defect.

At the same time, the first
The read operation and the comparison operation of the tag memory 15 of the bank are also performed. The comparing operation of the tag memory 15 is performed by the tag comparing means 16.
When data that does not match the expected value is read from the tag memory 15, the comparison result register 4
The bit corresponding to the inspected tag memory 15 is set to store that there is a defect in the tag memory.

When the reading and comparing operations of all the lines in the first bank 12 are completed, subsequently, in ST13, the reading and comparing operations of the second bank 13 of the instruction cache 1 are executed.

This operation is the same as ST12, and the reading and comparison operations of the data memory 14 and the tag memory 15 are executed in parallel. The difference is that the data read to the instruction bus 100 is replaced from the data memory 14 of the first bank 12 to the data memory 14 of the second bank 13, and that the comparison result register 4 The only difference is the position of the bit to be set.

When data that does not match the expected value is read from the data memory 14, a bit corresponding to the inspected data memory in the comparison result register 4 is set.

At the same time, reading from the tag memory 15 of the second bank 13 and comparison operation are also performed. The comparison operation of the tag memory 15 is performed using the tag comparison means 16. If data that does not match the expected value is read from the tag memory 15, the bit corresponding to the checked tag memory 15 in the comparison result register 4 is read. Is set.

The execution of ST12 and ST13 completes the reading of the instruction cache 1 and the comparison operation. Then ST
The data written in 14 and ST15 are read and compared with the expected value to perform the reading and comparison operation of the data cache 2.

In ST14, the expected value output from the data generating means 31 is placed on the instruction bus 100 and the data bus 20
0 of the data cache 2 performing the read check
The output of the data memory 24 of the bank is read. The expected value and the read data are compared by the data comparing means 32. If data not matching the expected value is read from the data memory 24, the bit corresponding to the inspected data memory 24 of the comparison result register 4 is set. set.

At the same time, reading from the tag memory 25 of the first bank 22 and comparison are also performed. The comparison operation of the tag memory 25 is performed using the tag comparison means 26. If data that does not match the expected value is read from the tag memory 25, the bit corresponding to the inspected tag memory 25 in the comparison result register 4 is set. set.

When reading and comparison of all the lines of the first bank 22 of the data cache 2 are completed, ST
At 15, the second bank 23 of the data cache 2 is read and compared. This operation is the same as ST14, and the reading and comparison operations of the data memory and the tag memory are executed in parallel. If data that does not match the expected value is read from the data memory 24, a bit corresponding to the inspected data memory 24 in the comparison result register 4 is set. If data that does not match the expected value is read from the tag memory 25, a bit corresponding to the inspected tag memory 25 in the comparison result register 4 is set.

Thus, the writing and reading inspections for the data pattern in which all the bits are 0 are completed. By this inspection, all the fixed faults can be detected.

Subsequently, the inspection of the memory is continued by changing the data pattern. In ST16, it is determined whether or not inspection of all four data patterns has been completed, and writing and reading inspection are performed on the data pattern in which all the bits are 1. Only the data pattern is different, and the order of inspection is the same as that of the data pattern in which all bits are 0. By completing the write and read inspections for the data pattern in which all bits are 1, all 0 fixed faults can be detected.

The data pattern is changed again and the memory test is continued. In ST16, it is determined whether or not all data patterns have been inspected, and subsequently, a write and read inspection for the checkerboard pattern (FIG. 2C) is performed. Also in this case, the order of inspection is the same except for the data pattern.

However, unlike the case where the data pattern is all 0s or 1s, in order for the data patterns to be arranged in the memory as shown in FIG. It is necessary to generate a data pattern in accordance with scrambling (correspondence between a logical address and a physical location of a memory). To write data to all memories in parallel,
It is necessary to unify the scrambling configuration of all memories.

By ending the writing and reading inspections for the checkerboard pattern, a malfunction (pattern-sensitive failure) due to the interaction between the memories is completed.
Can be detected.

The final test is performed by changing the data pattern. In ST16, it is determined whether or not the inspection of all four data patterns has been completed, and then the writing and reading inspection for the checkerboard pattern (FIG. 2D) is performed. Also in this case, the order of inspection is the same except for the data pattern. By terminating the write and read inspections for the checkerboard pattern, a pattern-sensitive failure can be detected.

Thus, the self-diagnosis of the memory for all four types of data patterns is completed. After the inspection of the memory is completed, the comparison result register 4 is read, and if all the bits corresponding to the inspected memory are 0, all the inspected memories are normal, and if any of the bits is 1,
It can be seen that a failure has occurred in the memory corresponding to the bit.

As described above, by performing writing to all memories in parallel, the writing time is shortened, and at the same time, the data generating means used for writing is used as a means for generating an expected value also in the reading test, and the reading is performed. By providing one data comparing means for comparing data and expected value, read inspection is enabled, so that high-speed self-diagnosis of the memory built in the semiconductor integrated circuit can be performed by adding a small amount of hardware. Become.

Next, a method of inspecting the bus wiring connected to the memory using the data generating means and the data comparing means provided for the self-diagnosis of the memory will be described with reference to FIG. FIG. 6A shows a bus that does not use the precharge method, and FIG. 6B shows a bus that uses the precharge method. The instruction bus 100 includes a wiring 100
a, 100b... 100n. Also,
The data bus 200 includes wirings 200a, 200b... 2
00n. In the data comparing means 32, the first
And the second input, the value of the wiring 100a and the wiring 2
00a, 100b, 200b, 100
The value of n is compared with the value of 200n. In ST11 where data is written in parallel to all banks,
The data pattern output from the data generation means 31 is output to the instruction bus 100 and the data bus 200. FIG.
As shown in (a), when a fixed failure of 1 occurs on the wiring 100a of the instruction bus 100 and a fixed failure of 0 occurs on the wiring 100b, regardless of the value output from the data generating means 31,
The value of a is fixed at 1, and the value of 100b is fixed at 0. At this time, if the data pattern is all bits 0 or a checkerboard pattern in which 0 is given to the wires 100a and 200a, the data comparing means 32
The value (1) of 00a is compared with the value (0) of 200a, and a mismatch is detected. Also, the data pattern is all bits 1 or 1 for the wirings 100b and 200b.
Is a checkerboard pattern that gives
The value (0) of the wiring 100b and 200
The value b is compared with the value (1), and a mismatch is detected.
When a mismatch is detected, a bit corresponding to the wiring failure in the comparison result register 4 is set, and the fact that the wiring has a failure such as a fixed failure is stored.

As described above, by comparing the data of the instruction bus 100 and the data of the data bus 200 by the data comparing means 32 in ST11, a fixed fault and a fixed fault of the bus wiring can be detected.

Although the fixed fault has been described, if the instruction bus 100 and the data bus 200 are precharged buses, even a disconnection of a wiring or a bridge (short) with an adjacent wiring can be detected. As shown in FIG. 6B, precharge means 104 and 204 are connected to the instruction bus 100 and the data bus 200, respectively.
A case where n is a disconnection and wirings 100a and 100b are bridged will be described. When the wire is disconnected, the wiring 100n is not driven (pulled down) by the data generation circuit 31 and remains at 1 which is precharged. Either all bits are 0 or the wiring 1
If the checkerboard pattern gives 0 to 00n and 200n, the data comparing means 32
The value (1) of n is compared with the value (0) of 200n, and a mismatch is detected. When a mismatch is detected, a bit corresponding to the wiring failure in the comparison result register 4 is set, and the fact that the wiring is defective is stored.

Next, a case where a bridge has occurred will be described. Wiring 100a is 1 in the bridged wiring
If the wiring 100b is a checkerboard pattern having a different value such as 0, the wiring 1 that is bridged when the data generation circuit 31 drives the wiring 100b to 0
The potential of 00a is also pulled down to zero. This allows
The value (0) of the wiring 100a and 200
A mismatch is detected by comparing the value of a with the value (1). Also in this case, the bit corresponding to the wiring failure of the comparison result register 4 is set to store that the wiring is defective.

As described above, if the bus is precharged, disconnection and bridge failure can be detected in addition to the 1-fixed fault and 0-fixed fault of the wiring.

As described above, the wiring can be inspected by comparing the values of the bus wiring with the data comparing means 32 in ST11. Thereby, when the data read from the memory is different from the expected value, it is possible to specify the cause of the wiring failure or the memory failure,
Failure analysis of the semiconductor integrated circuit is facilitated.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to the drawings. In the second embodiment, a write operation is performed on all memories in parallel as in the description of the first embodiment, and a read and compare operation is performed for each cache, or in other words, for each bus. 4 will be described.

FIG. 4 is a configuration diagram of a semiconductor integrated circuit having a built-in memory according to the second embodiment of the present invention. What is different from FIG. 1 is that the data comparing means is provided for the first bank 33 and the second bank 33.
Data selectors 18 and 28 for selecting the data pattern to be written to the tag memory and the data pattern of the data generating means 31 output to the instruction bus or the data bus as an expected value, the instruction bus and the data bus. Between the instruction buses 102 and 103 and the data buses 202 and 203, respectively.
01 and 201 are provided.

By adopting this configuration, it is possible to perform reading of the data memories of the two banks constituting the cache and comparison with the expected value in parallel. When writing to the tag memory and comparing with the expected value, the data pattern output from the data generating means 31 and output to the instruction bus or the data bus is not used by the address generating means 11 or 21 to generate the data pattern. It can be selected and used by selectors 18 and 28.

The write operation is described above, that is, ST1.
0 and ST11, and the data generation means 31 output to the bus as write data to the tag memory
This is the same except that the data pattern is selected and used. In addition, since the order of inspection is the same even if the data patterns are different, only the operation of reading a data pattern in which all bits are 0 and comparing it with the expected value will be described.

In order to execute reading and comparison operations from the instruction cache 1, the data generation means 3 is connected to the data bus 202.
Put the expected value of 1 output. The bus switch 201 is in the ON state, and the expected value output from the data generation unit 31 is also supplied to the data bus 203. The output of the data memory 14 of the first bank for executing the test is read onto the instruction bus 102. Similarly, the output of the data memory 14 of the second bank for executing the test in parallel with the data memory 14 of the first bank is read onto the instruction bus 103.

At the time of reading and comparing the instruction cache 1, the bus switch 101 is off, and the instruction buses 102 and 103 are not connected. The expected value and the data read from the data memory 14 of each bank are compared by the first data comparing means 33 and the second data comparing means 34, respectively, and the data which does not match the expected value is stored in the first data memory 14 or the second data comparing means 34. When the data is read from the second data memory 14, the bit corresponding to the data memory 14 that does not match the expected value of the comparison result register 4 is set, and the fact that the data memory is defective is stored.

In parallel with these operations, the reading from the tag memory 15 of each bank of the instruction cache 1 and the comparison operation are also performed. The comparing operation of the tag memory 15 is performed by the tag comparing means 16.
If the data that does not match the expected value is read from the first tag memory 15 or the second tag memory 15, the data corresponding to the tag memory 15 that does not match the expected value in the comparison result register 4 Set the bit to
The fact that there is a defect in the tag memory is stored.

The data pattern of the data generation means 31 output to the instruction bus selected by the data selector 18 is used as the expected value in this comparison operation.

By thus dividing the instruction bus and providing data comparing means for each of the divided buses, the first bank and the second bank of the instruction cache 1 can be read in parallel.

When the reading and comparison of all the lines of the instruction cache 1 are completed, the expected value output from the data generating means 31 is placed on the instruction bus 102. Bus switch 1
01 is an ON state, and the expected value output from the data generating means 31 is also supplied to the instruction bus 103. Data bus 2
02, the output of the data memory 24 of the first bank 22 of the data cache 2 to be tested is read.

Similarly, the output of the data memory 24 of the second bank 23 for executing the test in parallel with the data memory 24 of the first bank 22 is read onto the data bus 203. At the time of reading and comparing data cache 2, the bus switch 201 is off, and the data buses 202 and 20 are turned off.
3 is not connected. The expected value and the data read from the data memory 24 of each bank are compared by the first data comparing means 33 and the second data comparing means 34, respectively, and the data which does not match the expected value is stored in the first data memory. If the data is read from the second data memory 24 or the second data memory 24, a bit corresponding to the data memory 24 that does not match the expected value of the comparison result register 4 is set.

In parallel with these operations, the reading and comparison operations of the tag memory 25 of each bank of the data cache 2 are also performed. The comparison operation of the tag memory 25 is performed using the tag comparison means 26. When data that does not match the expected value is read from the first tag memory 25 or the second tag memory 25, the comparison result register 4 A bit corresponding to the tag memory 25 that does not match the expected value is set.

The data selector 28 used as the expected value in this comparison operation is the same as in the case of the instruction cache 1.
Data generating means 3 output to the data bus selected in step 3.
1 data pattern.

By dividing the data bus and providing data comparing means for each of the divided buses, the read inspection of the first bank 22 and the second bank 23 of the data cache 2 can be performed in parallel.

Thus, the writing and reading inspection for the data pattern in which all bits are 0 are completed. Also in this method, write and read inspections are performed on the remaining three data patterns.

That is, ST12 and ST13 which are the read check of the instruction cache 1 in FIG. 3 are executed in parallel, and ST14 and ST which are the read check of the data cache 2 are executed.
T15 can also be executed in parallel.

As described above, writing can be performed on all the memories in parallel, as in the first embodiment, and the bus connected to the memories to be read checked is connected to the bus switch 10.
By dividing the memory using the data 1,1,201, a plurality of memories connected to the same bus can be read in parallel. Data comparing means 33, 34 are provided for each of the plurality of memories, and one input receives data read from the memory. By selecting and selecting the bus that outputs the expected value to the other input, the memory read and comparison operations connected to the same bus can also be executed in parallel, so that the self-diagnosis of the memory can be performed faster. You.

In this embodiment, a cache employing the two-way set associative system has been described as an example. However, for example, in the case of a cache employing the three-way set associative system having three data memories, each bus has three buses. Providing two divided bus switches enables the memory read and comparison operations to be performed in parallel.

Next, a method of inspecting a bus connected to a memory using a data generating means and a data comparing means provided for self-diagnosis of the memory will be described with reference to FIG. The instruction bus 102 includes wirings 102a, 102b,
.. 102n, the instruction bus 103 is connected to the wiring 103a, 1
.. 103n. The data bus 202 includes wirings 202a, 202b,.
Thus, the data bus 203 includes wirings 203a, 203b,.
-It is composed of 203n. Instruction bus 102, 10
3. Precharge means 105, 106, 205, 206 are connected to the data buses 202, 203, respectively. In the data comparing means 33, the first input and the second input, the value of the wiring 102a, the value of the wiring 202a,
The value of b and the value of 202b are compared with the value of 102n and the value of 202n, respectively. In the data comparison means 34, the first input and the second input, the value of the wiring 103a, the value of the wiring 203a, the value of 103b and the value of 203b,
The value of 103n is compared with the value of 203n.

In ST11 in which data is written to all banks in parallel, the data pattern output from the data generating means 31 is output to the instruction bus 102 and the data bus 202. In ST11, all the bus switches are on, and if the bus wiring is normal, the expected value output from the data generating means 31 is also supplied to the instruction bus 103 and the data bus 203.

In the following, a case where a disconnection fault has occurred in the wiring 102a of the instruction bus 102 and the wiring 103b of the instruction bus 103 as shown in FIG. 7 will be described.

The wires 102a, 1 connected to the first inputs of the data comparing means 33, 34 due to the disconnection of the wires 102a.
The data pattern output from the data generation means 31 is not supplied to 03a, and a precharged 1 is input irrespective of the data pattern. Also, due to the disconnection of the wiring 103b, the data pattern output from the data generating means 31 is not supplied to the wiring 103b connected to the first input of the data comparing means 34, and the precharged 1 regardless of the data pattern. Is entered.

If the data pattern output from the data generating means 31 is all bits 0, the data comparing means 33 compares the value (1) of the wiring 102a with the value (0) of the wiring 202a and detects a mismatch. . Further, the data comparing means 34
Then, the value (1) of the wiring 103a is compared with the value (0) of the wiring 203a, and the value (1) of the wiring 103b is compared with the value (0) of the wiring 203b. When these inconsistencies are detected, the bit corresponding to the wiring failure in the comparison result register 4 is set, and the fact that the wiring is defective is stored.

If the failure is only at the location of the wiring 102a, the failure of the wiring is detected by both the data comparing means 33 and the data comparing means. If the failure is only at the location of the wiring 103b, the failure of the wiring is detected only by the data comparison circuit 34. That is, when detecting a wiring failure in ST11 or by making the bit assignment of the comparison result register 4 independent, whether a wiring failure has been detected by both the data comparison means 33 and the data comparison means 34 or one of them is detected. By checking whether the wiring has been performed, a defective portion of the wiring can be specified.

As described above, by comparing the detection results of the data comparing means 33 and 34 in ST11, it is possible to specify a fault location in addition to the wiring inspection. Thus, when the data read from the memory is different from the expected value, it is possible to specify the cause of the wiring failure or the memory failure, and further facilitate the failure analysis such as the specification of the wiring defective portion. .

(Embodiment 3) Next, a third embodiment of the present invention will be described with reference to the drawings. In the above two embodiments, the two buses, the instruction bus and the data bus, have the same bit width. However, the bus width of each of the buses connected to the memory may be different in the semiconductor integrated circuit. Therefore, in the third embodiment, the read test in this case will be described next with reference to FIG.

FIG. 5 is a configuration diagram of a semiconductor integrated circuit according to the third embodiment of the present invention when the buses connected to the memories have different bus widths. In FIG. 5, reference numeral 5 denotes a first memory, which is connected to a 32-bit bus 501. Reference numeral 6 denotes a second memory, which is a 16-bit bus 601.
It is connected to the. 7 is a third memory, also 16
It is connected to a bit bus 701. Reference numeral 31 denotes a data generation unit, which is connected to the buses 501, 601 and 701. Numeral 35 denotes a data comparing means. The first input has a bus 501, and the second input has a bus 601 and a bus 701.
Are connected, and the comparison results 301, 302, and 303 are output to the comparison result register 4.

Both the data generating means 31 and the data comparing means 35 can generate or compare 32-bit data having the same maximum bus width.

The inspection using the four data patterns as shown in FIG. 2 is performed on a plurality of memories connected to the buses having different bus widths.

Writing can be performed on all memories in parallel because the output of the data generating means 31 is connected to all buses.

In the read test, the test order is the same for any data pattern. Therefore, only the data pattern in which all bits are 0 will be described here.

In order to perform a read operation of the first memory 5 and a comparison operation with the expected value, the data of the first memory 5 is read. The read data is provided to a first input of the data comparison means 35. The expected value is stored in the data
, And outputs the upper 16 bits of the expected value to the bus 601 and the lower 16 bits of the expected value to the bus 701.

The bus 601 is connected to the upper 16 bits of the second input of the data comparing means 35, and the bus 701 is connected to the lower 16 bits. Become. As described above, the data comparison unit 35 inputs the data read from the memory and the expected value, and outputs the comparison result 301. The comparison result 301 is
It is input to and stored in the comparison result register 4.

The operations of reading the second memory and the third memory and comparing the expected values are performed in parallel. The 32-bit expected value generated by the data generation unit 31 and output to the bus 501 is provided to a first input of the data comparison unit 35. The 16-bit data read from the second memory 6 is given to the upper 16 bits of the second input of the data comparing means 35, and the 16-bit data read from the third memory 7 is read.
The bit data is given to the lower 16 bits of the second input of the data comparing means 35. As described above, the data comparison unit 35 inputs the data read from the memory and the expected value, and outputs the comparison result.

As described above, when performing a read check of a memory connected to a bus less than the bit width that can be processed by the data comparing means 35, a plurality of buses connected to the memory to be read checked are selected. As the first input,
By using the expected value output from the data generating means 31 as the second input, the operations of reading the memories connected to the two buses connected to the first input and comparing the expected value are performed in parallel. Performs self-diagnosis of memory at high speed.

In this description, the data comparing means 35
By connecting two buses to the input of the data comparison means 3
Although the same 32 bits as the processable bit width of 5 were obtained, but less than 32 bits even if a plurality of buses were connected, the unnecessary portion was masked in accordance with the effective bit width of the input data. It is necessary to perform the comparison by the comparing means 35.

Further, in order to make it possible to distinguish the comparison result of each memory subjected to the read test in parallel, the comparison result 602 of the upper 16 bits and the comparison result 60 of the lower 16 bits are required.
3 must be output to the comparison result register 4.

Although the embodiment has been described on the assumption that the number of lines (entries) of the memory is the same, the parallel writing at the time of writing and the parallel reading at the time of reading inspection can cope with a mixture of memories having different numbers of lines. Needless to say.

[0121]

As described above, according to the first aspect of the present invention, a plurality of buses to which one or more memories are connected and a memory to be written which is connected to all the buses are written. A data generating means for supplying pattern data which becomes write pattern data and becomes an expected value for a memory to be read; and a bus to which the memory to be read is connected is selected from among the plurality of buses, and The data read from the memory is selected as a first input, a bus other than the bus selected by the first input is selected, and an expected value output from the data generating means is set as a second input. And data comparing means for outputting the result of the comparison, so that all memories connected to the bus without giving an address or data from outside the semiconductor integrated circuit are provided. Self-diagnosis can be performed.

According to a third aspect of the present invention, in addition to the first aspect of the present invention, N-1 buses for dividing one bus to which N or more memories are connected into N buses are provided. By providing a switch and N pieces of the data comparison means for each of the N divided buses, a plurality of memories can be connected to the same bus since reading inspections of N pieces of memory can be performed in parallel. Self-diagnosis of the memory of the semiconductor integrated circuit can be performed at higher speed.

According to a fourth aspect of the present invention, in addition to the first aspect, the bus width of any two buses selected and inputted to the data comparing means is smaller than the bit width of the data comparing means. If a plurality of buses are selected as one input and the sum of the bus widths of the selected plurality of buses is still less than the bit width of the data comparison means, a portion where valid data is not placed is masked according to the bus width. This function is added to the data comparing means, so that the data comparing means can be effectively used, and the reading test can be performed in parallel when the buses connected to the memories have different bus widths.

According to a fifth aspect of the present invention, in the first aspect of the present invention, one of the plurality of buses is an instruction bus, and the instruction bus is provided with either a direct map or a set associative system. A data memory of an instruction cache to be used is connected, and a read check of the data memory is performed by setting data read from the data memory to an instruction bus as a first input, and an expected value output by the data generation means to a bus other than the instruction bus. Is compared by the data comparison means as a second input, and the read check of the tag memory of the instruction cache is performed by using the data read from the tag memory as the first input and the tag portion of the address for accessing the instruction cache. The comparison is performed by the tag comparing means serving as the second input, and output from each comparing means. A comparison result storage means for inputting the comparison result to be input and storing the result as pass / fail judgment information of the memory, so that the read check of the data memory and the tag memory of the instruction cache can be performed in parallel, and the self-diagnosis of the memory can be performed more quickly. You.

According to a sixth aspect of the present invention, in the first aspect of the present invention, one of the plurality of buses is a data bus, and the data bus is provided with either a direct map or a set associative system. The data memory of the data cache to be used is connected, and the read check of the data memory is performed by setting the data read from the data memory to the data bus as a first input, and the expected value output by the data generating means to a bus other than the data bus. Is compared by the data comparing means as a second input, and the read inspection of the tag memory of the data cache is performed by using the data read from the tag memory as the first input, and checking the tag portion of the address for accessing the data cache. The comparison is performed by the tag comparison means as the second input, and A comparison result storage means for inputting the comparison result output from the comparison means and storing the result as pass / fail judgment information of the memory, so that the read inspection of the data memory and the tag memory of the data cache can be performed in parallel, and the self-diagnosis of the memory can be further improved. You can go fast.

According to a seventh aspect of the present invention, in the first aspect of the present invention, the plurality of buses include an instruction bus and a data bus, and the data memory of the instruction cache connected to each of the instruction bus and the data bus. And a self-diagnosis of the data memory of the data cache.

According to the invention of claim 8, in the invention of claim 5 or 6, the tag portion of the address to access the cache is selected at normal times, and the tag output from the data generation means is output at the time of inspection of the tag memory. A selector for selecting the data of the data memory, and inputting the output of the selector to the write port of the tag memory and the tag comparing means to thereby write the expected data used for comparison with the write data or the tag at the time of the inspection of the tag memory of the data memory. Therefore, the function of the address generation means at the time of memory inspection is only address generation, and the configuration of the address generation means can be simplified.

According to the ninth aspect of the present invention, similarly to the first aspect of the present invention, at the time of writing to the memory, the write pattern data is output from the data generating means to all the buses connected to the memory. Performing parallel writing to a plurality of memories connected to each of the buses,
At the time of memory read inspection, the first
One bus is selected from the plurality of buses as the first input, a bus other than the bus selected as the first input is selected as the first input, and the second input is selected as the second input. The data read from the memory connected to the bus is supplied to the second input with the expected value output from the data generating means, and the read data is compared with the expected value. Self-diagnosis of memory can be performed without giving data or data.

According to the eleventh aspect, the ninth aspect is provided.
In addition to the invention of (1), one bus to which at least N or more memories are connected can be divided into N by N-1 bus switches, and data is generated without dividing the bus when writing data to the memory. The write pattern data output by the means to the bus is written in parallel to the N or more memories, and at the time of read inspection, the bus is divided and read from the N memories to the N divided buses. Outputting the data, inputting the read data as a first input of N data comparing means provided for each of the divided buses, and inputting an expected value output by the data generating means as a second input; Thus, the self-diagnosis of the memory of the semiconductor integrated circuit in which a plurality of memories are connected to the same bus can be performed at higher speed.

According to the twelfth aspect, the ninth aspect is provided.
In the invention, when a bus selected as a first input of the data comparing means is smaller than a bit width of the data comparing means, a plurality of buses connected to a memory are simultaneously selected as a first input to thereby obtain a plurality of buses. By performing the read operation of the memory connected to the different bus and the comparison operation with the expected value in parallel, the read operation of the memory of different bit configuration connected to the different bus and the comparison operation with the expected value can be performed in parallel And the speed of the read inspection can be increased.

According to the thirteenth aspect, the ninth aspect is provided.
In the invention, one of the plurality of buses is an instruction bus, and a data memory of an instruction cache employing either a direct map or a set associative system is connected to the instruction bus. Is performed by using the data read from the data memory to the instruction bus as a first input, and comparing the expected value output to a bus other than the instruction bus by the data generation means with the data comparison means as a second input. The read check of the tag memory is performed by comparing data read from the tag memory with the first input and comparing the tag portion of the address for accessing the instruction cache with the second input using the tag comparing means. The comparison result output from the means is input to the comparison result storage means as pass / fail judgment information of the memory. By doing so, it is possible to perform read inspection of the data memory of the data cache and the tag memory in parallel, and it is possible to perform the read operation and the comparison operation with the expected value in the data memory and the tag memory in parallel without requiring additional means, The speed of the read inspection can be increased.

According to the fourteenth aspect, the ninth aspect is provided.
In the invention, one of the plurality of buses is a data bus, and the data bus is connected to a data memory of a data cache employing either a direct map or a set associative method, and a read test of the data memory is performed. Uses the data read from the data memory to the data bus as a first input, and outputs the expected value output from the data generation means to a bus other than the data bus as a second input.
The data is read out from the tag memory as the first input, and the tag portion of the address for accessing the data cache is used as the second input. The comparison is performed by the tag comparing means, and the comparison result output from each of the comparing means is input to the comparison result storing means as the pass / fail judgment information of the memory, so that the reading test of the data memory of the data cache and the tag memory is performed in parallel. And the speed of the read inspection can be increased.

According to the fifteenth aspect, the first aspect is provided.
The invention according to the third or 14th aspect, further comprising a selector for selecting a tag portion of an address for accessing the cache at normal times, and selecting data on a bus output from the data generating means at the time of inspection of the tag memory. By inputting the data to the memory and the tag comparing means, the write data at the time of the inspection of the tag memory or the expected value used for comparison with the tag can be shared with the write data or the expected value of the data memory, thereby simplifying the configuration of the address generating means. can do.

According to the sixteenth aspect, the ninth aspect is provided.
In the invention, when writing to a memory, by outputting write pattern data from the data generating means to all buses connected to the memory, a process of performing parallel writing to a plurality of memories connected to each of the buses is provided. At the same time, one bus is selected from the plurality of buses as a first input of the data comparison means, and a bus other than the bus selected as the first input is selected as a second input of the data comparison means. By selecting and comparing the pattern data output from the data generating means to the first input and the second input, a process of detecting a failure of the selected bus wiring is performed. One of the plurality of buses is selected as the first input of the data comparing means, and the second bus is selected as the second input of the data comparing means. A bus other than the bus selected as the first input is selected, data read from a memory connected to the bus is output as the first input, and output of the data generating means is output as the second input. By providing the expected value, a process for comparing the read data with the expected value is provided. If the data read from the memory is different from the expected value, the cause may be a wiring failure or a memory failure. Can be specified, and the failure analysis of the semiconductor integrated circuit can be easily performed.

According to the seventeenth aspect, the first aspect is provided.
In the present invention, the bus is not divided at the time of writing to the memory, and the write pattern data output to the bus by the data generating means is written in parallel to the plurality of N or more memories at the same time as the divided bus. N provided
By comparing the pattern data output from the data generating means as the first input and the second input of the data comparing means, a fault for each of the divided bus lines is detected, and a fault detection for each bus line is detected. A process for identifying a faulty portion of the divided bus by comparing the results, if the data read from the memory is different from the expected value, it may be caused by a wiring failure or a memory failure. The identification becomes possible, and the failure analysis such as the identification of the defective portion of the wiring is further facilitated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit including a memory according to a first embodiment of the present invention;

FIG. 2 is a diagram showing four types of data patterns written to a memory in the embodiment.

FIG. 3 is a flowchart showing a method of inspecting a semiconductor integrated circuit having a built-in memory in the embodiment.

FIG. 4 is a configuration diagram of a semiconductor integrated circuit including a memory according to a second embodiment.

FIG. 5 is a configuration diagram of a semiconductor integrated circuit including a memory according to a third embodiment.

FIG. 6 is a diagram illustrating a wiring failure of a semiconductor integrated circuit having a built-in memory according to the first embodiment;

FIG. 7 is a diagram illustrating a wiring failure of a semiconductor integrated circuit having a built-in memory according to a second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction cache 2 Data cache 3 Bus control means 4 Result storage register 11 Address generation means 14,24 Data memory 15,25 Tag memory 16,26 Tag comparison means 17,27 Address decoder unit 21 Address generation means 31 Data generation means 32 Data Comparison means 100 instruction bus 200 data bus

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 29/00 G06F 12/08 H01L 21/66

Claims (17)

(57) [Claims] 1. A semiconductor integrated circuit for performing self-diagnosis of a memory, comprising: a plurality of buses to which one or more memories are connected; and a write pattern for a memory to be written which is connected to all the buses. Data generating means for supplying pattern data which becomes data and an expected value to a memory to be read, and a bus to which a memory to be read is connected is selected from the plurality of buses to select a bus to be read. The data read from the memory is used as a first input, and an expected value output from the data generating means by selecting a bus other than the bus selected by the first input is used as a second input. A semiconductor integrated circuit comprising: data comparing means for comparing the second input data and outputting the comparison result. 2. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit further comprising comparison result storage means for inputting the comparison result and storing the result as pass / fail judgment information of a memory. 3. The semiconductor integrated circuit according to claim 1, wherein
Further, there are (N-1) bus switches for dividing one bus to which N or more memories are connected into N buses, and the data comparison means is provided for each of the N divided buses. A semiconductor integrated circuit characterized in that: 4. The semiconductor integrated circuit according to claim 1, wherein
When the bus width of any two buses input to the data comparing means is smaller than the bit width of the data comparing means,
If a plurality of buses are selected as one input and the total bus width of the selected plurality of buses is still less than the bit width of the data comparing means, a portion where valid data is not placed is masked according to the bus width. A semiconductor integrated circuit, wherein the function of performing the above operation is added to the data comparing means. 5. The semiconductor integrated circuit according to claim 1, wherein
One of the plurality of buses is an instruction bus, and a memory connected to the instruction bus employs either a direct map or a set associative method, and is a data memory of an instruction cache having a data memory and a tag memory. Wherein the data comparison means uses the data read from the data memory to the instruction bus as a first input, and the expected value output to the bus other than the instruction bus by the data generation means as a second input; A tag comparing means for outputting data read from the tag memory as a first input, a tag portion of an address for accessing the instruction cache as a second input, and outputting a comparison result thereof; Input the comparison result output from the means,
A semiconductor integrated circuit comprising comparison result storage means for storing as memory pass / fail judgment information, and performing a read test of a data memory and a tag memory of an instruction cache in parallel. 6. The semiconductor integrated circuit according to claim 1, wherein
One of the plurality of buses is a data bus, and a memory connected to the data bus employs either a direct map or a set associative system, and is a data memory of a data cache having a data memory and a tag memory. The data comparison means uses the data read from the data memory to a data bus as a first input, and the expected value output from the data generation means to a bus other than the data bus as a second input to calculate the comparison result. A tag comparing means for outputting data, reading the data read from the tag memory as a first input, a tag portion of an address for accessing a data cache as a second input, and outputting a comparison result, and the plurality of comparing means Input the comparison result output from
A semiconductor integrated circuit comprising comparison result storage means for storing as memory pass / fail judgment information, and performing a read test of a data memory and a tag memory of a data cache in parallel. 7. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit, wherein the plurality of buses include an instruction bus and a data bus, and a data memory of an instruction cache and a data memory of a data cache are connected to the instruction bus and the data bus, respectively. 8. The semiconductor integrated circuit according to claim 5, further comprising a step of selecting a tag portion of an address for accessing a cache in a normal state, and selecting data on a bus output from a data generating means during a test of a tag memory. Wherein the output of the selector is connected to a tag memory and a tag comparing means. 9. A process for performing parallel writing to a plurality of memories connected to each of the buses by outputting write pattern data from the data generating means to all buses connected to the memory at the time of writing to the memory. And selecting one of the plurality of buses as the first input of the data comparing means at the time of the memory read test, and selecting the first input as the second input of the data comparing means. By selecting a bus other than the bus and supplying the data read from the memory connected to the bus to the first input and the expected value output from the data generating means to the second input, the read is performed. A method for inspecting a semiconductor integrated circuit, comprising: a process of comparing data with an expected value. 10. The method for inspecting a semiconductor integrated circuit according to claim 9, wherein when the read inspection of all the memories connected to the bus selected as the first input is completed, the first of the data comparing means is performed. A method for inspecting a semiconductor integrated circuit, comprising a process of selecting a bus to which a memory on which a read test has not been performed is connected as an input and performing a read test on a memory on which a read test has not been performed. 11. The method for testing a semiconductor integrated circuit according to claim 9, wherein one bus to which at least N or more memories are connected by N-1 bus switches is set to N.
The write pattern data output to the bus by the data generation means is not divided into N buses when writing data to the memory.
At the time of read inspection, the bus is divided and the data read out from the N memories are output to the N divided buses at the time of read inspection, and the read data is provided for each of the divided buses. By inputting the read data as the first input of the obtained N data comparing means and inputting the expected value output by the data generating means as the second input, the reading test of the N memories is performed in parallel. A semiconductor integrated circuit inspection method. 12. The method according to claim 9, wherein when a bus selected as a first input of said data comparing means is smaller than a bit width of said data comparing means, a plurality of connected memories are provided. A testing method for a semiconductor integrated circuit, wherein reading of a memory connected to a plurality of buses and comparison with an expected value are performed in parallel by simultaneously selecting the first bus as a first input. 13. A method for testing a semiconductor integrated circuit according to claim 9, wherein one of said plurality of buses is an instruction bus, and said instruction bus employs either a direct map or a set associative method. A data memory of an instruction cache having a data memory and a tag memory is connected. In the read check of the data memory, data read from the data memory to an instruction bus is used as a first input, and the data generation means is other than the instruction bus. The expected value output to the bus is compared as the second input by the data comparison means. The read check of the tag memory is performed by using the data read from the tag memory as the first input and accessing the instruction cache. By comparing the tag portion of the address to be compared with the tag comparing means having the second input. By inputting the comparison results output from the respective data comparison means and the tag comparison means to the comparison result storage means for storing as the pass / fail judgment information of the memory, the read inspection of the data memory and the tag memory of the data cache can be performed in parallel. A method for inspecting a semiconductor integrated circuit, which is performed. 14. The method for testing a semiconductor integrated circuit according to claim 9, wherein one of said plurality of buses is a data bus, and the data bus employs either a direct map or a set associative system. A data memory of a data cache having a data memory and a tag memory is connected, and in the read check of the data memory, data read from the data memory to a data bus is used as a first input;
The expected value output from the data generation means to a bus other than the data bus is compared as a second input by the data comparison means, and the read check of the tag memory is performed by reading the data read from the tag memory. 1 and the tag portion of the address accessing the data cache is compared by the tag comparing means as the second input, and the comparison result output from each of the data comparing means and the tag comparing means is used to determine whether the memory is good or bad. A test method for a semiconductor integrated circuit, wherein a read test of a data memory and a tag memory of a data cache is performed in parallel by inputting to a comparison result storage means for storing as determination information. 15. A semiconductor integrated circuit according to claim 13, wherein a tag portion of an address for accessing a cache is selected in a normal state, and data on a bus output from a data generating means is selected in a test of a tag memory. A selector is provided, and the output of the selector is input to the tag memory and the tag comparing means, so that the write data at the time of inspection of the tag memory or the expected value used for comparison with the tag is shared with the write data or the expected value of the data memory. A method for inspecting a semiconductor integrated circuit. 16. A method for testing a semiconductor integrated circuit according to claim 9, wherein at the time of writing to a memory, write pattern data is output from a data generating means to all buses connected to the memory, so that each of said buses is output. At the same time as the process of performing parallel writing to a plurality of connected memories, one bus is selected from the plurality of buses as a first input of the data comparing means, and the second input of the data comparing means is selected. By selecting a bus other than the bus selected as the first input and comparing the pattern data output from the data generation means to the first input and the second input, the selected bus wiring Of the plurality of buses as a first input of the data comparison means at the time of a memory read test. And selecting a bus other than the bus selected as the first input as the second input of the data comparison means, and reading the data read from the memory connected to the bus as the first input, A method for comparing read data with an expected value by supplying an expected value output from the data generating means to the second input, and testing the semiconductor integrated circuit. 17. A method for testing a semiconductor integrated circuit according to claim 11, wherein a bus is not divided at the time of writing to a memory, and write pattern data output from said data generating means to said bus is written to said N or more memories. At the same time as writing in parallel, by comparing the pattern data output from the data generation means as the first input and the second input of the N data comparison means provided for each of the divided buses, A method for inspecting a semiconductor integrated circuit, comprising: detecting a failure of each of the bus wirings and comparing a failure detection result of each of the bus wirings to specify a failure location of the divided bus.