JP3494072B2 - Cache memory and fault detection method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly to a cache memory having a diagnostic function and a diagnostic method therefor.

[0002]

2. Description of the Related Art Due to the increase in the integration density and operating frequency of processors, computer systems have become able to process a large amount of data in a short time. However, the improvement of the operating frequency of the main storage device is slower than that of the processor, and a large amount of time is spent for the whole processing by reading or writing data, which hinders the improvement of the processing performance of the entire computer system. Therefore, a cache memory has been developed which holds a copy of a part of the main memory in the processor and can read or write data at high speed. This solves the problem that the frequently referred data can be loaded at high speed and the data supply becomes a performance bottleneck.

[0003]

However, the update of the contents of the cache memory is generally asynchronous and often operates at a timing that is not assumed in the design stage, so that the logic that cannot be detected by software simulation is used. Design mistakes may remain. If a problem occurs during the evaluation or verification stage on the actual machine, asynchronous update is performed, so even if the instruction tracer can collect it as an error log, it is difficult to identify the update timing of the address that caused the error. . Therefore, even when it is found that the data read from the cache memory is incorrect, it is difficult to find out when the data was updated and what kind of data was loaded from the memory.

Further, a random access memory (RA
For the failure of M), the conventional parity check method cannot detect the failure when the parity bits happen to coincide with each other due to the intermittent failure, and the coverage rate of the check is low. Also,
Even if a mismatch of read data is detected, there is a problem that the determination as to whether it is due to a failure or due to a mistake in logic design is delayed.

On the other hand, for example, JP-A-2-27555
Japanese Patent No. 1 discloses a debug device that compares two data read from a cache memory and a main memory to detect a mismatch. However, in the device described in this document, access to the main memory is required for error detection, and not only the performance is degraded, but also the operation timing is different between the debug mode and the normal operation mode, and reproducibility is poor. There is also the problem that it cannot be guaranteed.

The object of the present invention is to solve the problems of the prior art,
The purpose is to reliably detect an error in the cache memory.

[0007]

In order to solve the above problems, a cache memory according to the present invention has an auxiliary data memory for storing at least a part of the contents stored in the cache memory therein. If the contents do not match the cache memory, it is detected that the cache memory has failed.

Further, another cache memory of the present invention is
In a cache memory having an address array for storing addresses and a data memory for storing data corresponding to the addresses stored in the address array, at least one copy of the addresses stored in the address array is stored in each entry. An auxiliary address array, an auxiliary data memory for storing the data stored in the data memory corresponding to the address stored in each entry of the auxiliary address array, and the contents stored in the auxiliary data memory are the data. And a comparator for detecting whether or not the contents of the memory match.

Another cache memory according to the present invention is
Further including a mode holding circuit for holding the store mode,
When the store mode is active, any of the cache fill and the store instruction among the writes to the data memory is reflected in the auxiliary data memory, and when the store mode is not active, of the writes to the data memory The cache fill is reflected in the auxiliary data memory and the store instruction is not reflected.

In another cache memory of the present invention, the comparator outputs a valid value when the store mode is active, and does not output a valid value when the store mode is not active.

Further, in another cache memory of the present invention, the mode holding circuit further holds a dynamic mode, and when the address array is updated by cache fill, the auxiliary address if the dynamic mode is active. The same update content is reflected in the array, and is not reflected in the auxiliary address array when the dynamic mode is not active.

Further, in another cache memory of the present invention, the auxiliary address array detects whether or not the monitoring target register for which an interrupt generation condition is set and the condition set in this monitoring target register are matched. And a coincidence detector.

Further, in another cache memory of the present invention, the monitoring target register holds an instruction code and an access destination address as an interrupt generation condition.

In another cache memory of the present invention, the address array includes a counter that is counted in response to a condition match in the match detector, and an output of this counter as one input and another input. A count comparator for detecting a match is further included, the monitoring target register further holds an expected value of the number of detections in the match detector, and the count comparator holds the value of the counter in the monitoring target register. Notify that an interrupt has occurred if it matches the expected value.

Further, in another cache memory of the present invention, the monitoring target register holds an instruction code and a register number as an interrupt generation condition.

In another cache memory of the present invention, the address array includes a counter that is counted in response to a condition match in the match detector, and an output of this counter as one input and another input. A match count detector for detecting a match, the monitoring target register further holds an expected value of the number of detections in the match detector, and the count comparator holds the counter value in the monitoring target register. If it matches the expected value, the interrupt is notified.

Further, according to the method of detecting a failure in a cache memory of the present invention, an address array for storing an address, a data memory for storing data corresponding to an address stored in the address array, and the address array are stored. An auxiliary address array for storing at least one copy of the address in each entry, and an auxiliary data memory for storing the data stored in the data memory corresponding to the address stored in each entry of the auxiliary address array A failure detection method in a cache memory having a mode holding circuit for holding a store mode, wherein when the store mode is active, any one of a cache fill and a store instruction of writing to the data memory is the auxiliary. Reflected in data memory, When the tor mode is not active, the writing to the data memory by the cache fill is controlled so as to be reflected in the auxiliary data memory and not by the store instruction. When the store mode is active, the auxiliary is controlled. Whether or not the contents stored in the data memory match the contents of the data memory is output, and if it is determined that the contents match, if there is a cache hit, an interrupt signal for fault occurrence is generated.

According to another method of detecting a failure in a cache memory of the present invention, the mode holding circuit further holds a dynamic mode, and when the dynamic mode is active, the auxiliary address array is updated at the time of cache fill. .

Further, another method of detecting a failure in a cache memory according to the present invention further generates an interrupt when a predetermined condition is satisfied a predetermined number of times, and when the interrupt occurs, the address array, the data memory, and the auxiliary address array. , And the contents of the auxiliary data memory.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a cache memory of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a computer system to which the present invention is applied has a processor 200 for processing operations and the like, and a main storage device 300 for holding data necessary for the processing of the processor 200. The cache memory 100 is provided between the memory 200 and the main memory 300. A diagnostic device 400 that diagnoses the cache memory 100 is connected to the cache memory 100.

Referring to FIG. 2, the embodiment of the cache memory of the present invention has an address array 110 and a data memory like an ordinary cache memory, and the accessed address is held in the address array 110. Whether or not there is a search is performed by the comparator 161. In the present invention, the auxiliary address array 120 which holds a part of the contents of the address array 110 and the auxiliary data memory 1 which holds a part of the contents of the data memory 130.
40, a data memory 130, and an auxiliary data memory 140
And a comparator 172 for detecting a mismatch between and. In addition, the auxiliary address array 120 and the auxiliary data memory 1
A mode holding circuit 171 for holding a mode for controlling the operation of 40 is further included.

The instruction register 151 is used in the processor 200.
The instruction code input from the signal line 203 is held. The address register 152 holds the access address input from the processor 200 via the signal line 201. The store data register 153 is used by the processor 20.
The store data input from 0 to the signal line 202 is held. The store data register 153 is used for a store instruction and not used for a load instruction.

When a cache miss for a load instruction occurs in the cache memory 100, the cache memory 100 instructs the main storage device 300 to read the fill block data in order to fill the corresponding block data. The fill data buffer 154 transfers the fill block data from the main storage device 300 to the signal line 30.
Receive via 2 and hold. The fill data buffer 154 arranges the writing to the data memory 130 in the order required. Specifically, at the same time as the block data from the main storage device 300, the tag assigned to each block and the position within the block are input from the main storage device 300 via the signal line 301, and according to these tags and positions. Fill data buffer 15
The storage location in 4 is determined. For example, if the number of requests that can be requested to the main storage device 300 is 2, the tag is either "0" or "1", and 128 bytes of data per block is the cache memory 100 in units of 8 bytes. If it is transferred to, the position will be any value from “0” to “15”.

If the address due to the store instruction does not exist in the cache memory, the fill operation is not performed, and hereinafter, the cache miss means the cache miss due to the load instruction. Generally, as load instructions, a cacheable load instruction that holds the target data in the cache memory and a load instruction that does not hold the target data are considered, but in the following description, the load instruction will be described as a cacheable load instruction. .

The miss processing circuit 155 performs a fill operation in the case of a cache miss. The miss processing circuit 155
The block address during the filling operation is held inside, and the corresponding block address is output to the selector 157 based on the tag transferred from the main storage device 300 via the signal line 301. Further, the miss processing circuit 155 stores the data input from the signal line 302 in the fill data buffer 154 according to the tag and the position input from the signal line 301. Further, the miss processing circuit 155
Controls the update of the address array 110 at the time of a miss via the signal line 193.

The decoder 156 detects that the instruction held in the instruction register 151 is a store instruction and a cache hit or a cache fill is detected, and outputs an update signal to the data memory 130.

The selector 157 selects the address held in the address register 152 at the time of storing, selects the address from the miss processing circuit 155 at the time of filling due to a cache miss, and outputs it to the signal line 191.

The selectors 159 and 158 select either the fill data from the fill data buffer 154 or the store data from the store data register 153 and input them to the data memory 130 and the auxiliary data memory 140, respectively.

The mode holding circuit 171 holds a mode, which will be described later, and stores the auxiliary address array 120 and the comparator 172.
Output the current mode to. The comparator 172 includes the data from the data memory 130 and the auxiliary data memory 14
The data from 0 is compared, and whether the two match or not is output to the processor 200 via the signal line 205. When the mode holding circuit 171 indicates a predetermined mode,
The comparator 172 does not output the mismatch signal.

The data read from the data memory 130 is held in the load data register 173 and output to the processor 200 via the signal line 204. The hit / miss judgment by the comparator 161 is output to the processor 200 via the signal line 206. Further, the interrupt detected in the auxiliary address array 120 is output to the processor 200 via the signal line 207.

There are two types of modes held by the mode holding circuit 171. One is the store mode and the other is the dynamic mode. When the store mode is active, the auxiliary data memory 1 is used both when filling due to a cache miss and when writing due to a store instruction.
Update to 40. On the other hand, when the store mode is not active, the auxiliary data memory 140 is filled only at the time of filling.
To the auxiliary data memory 140 at the time of writing by the store instruction. Further, when the dynamic mode is active, the auxiliary address array 12 is so-called dynamically for each fill due to a cache miss.
Update 0. On the other hand, when the dynamic mode is not active, the auxiliary address array 120 is not updated even if there is a fill due to a cache miss, and the operation is continued with the initial setting.

The store mode and the dynamic mode operate independently of each other. The former controls updating of the auxiliary data memory 140, and the latter controls updating of the auxiliary address array 120. When the store mode is activated, the update to the data memory 130 is reflected in the auxiliary data memory 140, so the comparator 172
An error can be detected in. On the other hand, when the store mode is not active, the auxiliary data memory 140 is not always in the latest state, so even if the comparator 172 detects a mismatch, that does not necessarily mean an error. Therefore, in this case, the comparator 1
72 does not output a mismatch. The store mode is provided so that the store instruction can be separated from other instructions by making the store mode inactive and collecting the contents of the auxiliary data memory 140. That is, when the store mode is activated and the auxiliary data memory 140 is updated in the same manner as the data memory 130, and when the store mode is inactive, the writing by the store instruction is performed by the data memory 130.
This is because it is possible to determine whether the cause of the error is due to the cache fill or the store instruction by analyzing the difference from the only one. The cause of the error is that if an unintended store instruction occurs due to a logical mistake, if the address to be stored is garbled, if there is a logical mistake in the cache fill sequence, or if there is an alpha ray or the like. It is possible that the contents of the data memory are corrupted due to the influence.

When the dynamic mode is activated, the auxiliary address array 120 is updated at the same time when the address array 110 is updated at the time of filling due to a cache miss, so that the address just updated can be appropriately checked. On the other hand, if the dynamic mode is set to inactive, the contents of the auxiliary address array 120 are left as the initial settings, so that the desired address can be checked intensively.

The diagnostic device 400 sets the auxiliary address array 120 and the mode holding circuit 171 via signal lines 401 and 403, respectively. Further, when the contents of the auxiliary address array 120, the auxiliary data memory 140, and the mode holding circuit 171 are sampled in the diagnostic device 400, the signal lines 401 to 403 are used respectively.

Referring to FIG. 3, the auxiliary address array 120 in the first embodiment of the present invention has four sub address arrays.
It has a set of address registers 122 and a comparator 123. The number of sets provided may be arbitrarily set according to the system requirements. The address register 122 holds an address corresponding to a block (line) of the address array 110. The auxiliary address array 120 is the address array 1
Since the number of entries is smaller than that of 10, all the entries in the address array 110 cannot be held. When the above-mentioned dynamic mode is used, when a new fill due to a cache miss occurs, old entries are sequentially deleted. As such a control method, a method of sequentially selecting address registers to be registered by round robin is conceivable. For example, first register in address # 0 register, then address # 1
Registering in the register, then registering in the address # 2 register, then registering in the address # 3 register, then registering in the address # 0 register, and so on. To realize this, a counter indicating the entry to be registered may be prepared.

Each of the address registers 122 includes a valid bit indicating whether it is valid or not, and the one showing “valid” is the comparison target in the corresponding comparator 123. The comparison results of the respective comparators 123 are collected by the encoder 124, and are “00”, “01”,
The number of the matching entry of either "10" or "11" (hereinafter referred to as local address) is indicated. This local address is output to the auxiliary data memory 140 via the signal line 194 together with the lower part of the address.

The diagnostic device 400 can set the initial value of the address register 122 by means such as a scan path. If the dynamic mode is not activated, its initial value can be maintained.

The decoder 125 instructs the auxiliary data memory 140 to perform a read or write operation via the signal line 195. That is, if the instruction on the signal line 192 is a load instruction and a match is detected by any of the comparators 123, the auxiliary data memory 140 is instructed to read the data corresponding to the local address. In the case of a cache mishit, in the dynamic mode, the auxiliary data memory 140 is instructed to write by the fill operation. Further, if the instruction on the signal line 192 is a store instruction and a match is detected by any of the comparators 123, the writing is instructed to the auxiliary data memory 140 in the store mode and the dynamic mode.

The monitoring target register 121 has an expected number of times 1211, an instruction code 1212, and an address 1213.
And hold. The monitoring target register 121 is set by the signal line 401. The comparator 126 detects a match between the instruction code 1212 and the instruction code of the signal line 192. The comparator 127 has an address 1213 and a signal line 191.
Detect a match with the address of. By these comparators 126 and 127, it is possible to distinguish the store or load to the desired address and detect the occurrence of the event.
When both the comparators 126 and 127 detect the coincidence, the AND circuit 128 causes the incrementer 1202 to increment the counter 1201 by “1”. Comparators 126 and 127
And the AND circuit 128 are collectively referred to as a coincidence detector. When the number of times comparator 129 detects that the number of times indicated by the counter 1202 matches the expected number of times 1211, the signal line 2
An interrupt signal is output to 07. As a result, it is possible to specify the number of times a predetermined instruction has been executed for a predetermined address, generate an interrupt, and collect the state of the cache memory.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIGS. 2 to 6, first, when the instruction is a load instruction (step S501), if a match is detected by any of the comparators 123 in the auxiliary address array 120 (step S502), the register to be monitored. The occurrence of interrupt by 121 is checked (step S503).
This interrupt check is performed by the comparator 1 as shown in FIG.
26 and 127, when the coincidence of the instruction and the address is detected by the AND circuit 128 (step S6)
01), the counter 12 by the incrementer 1202
01 is incremented by "1" (step S602). The value of the counter 1201 is the expected number of times 1 of the register 121 to be monitored.
When it matches with 211 (step S603), the frequency comparator 129 notifies the processor 200 of the occurrence of the interrupt via the signal line 207 (step S604).

In parallel with the interrupt check, data is read from the auxiliary data memory 140 according to the instruction of the signal lines 194 and 195 from the auxiliary address array 120 (step S504). Further, when the mode held in the mode holding circuit 171 is the store mode, the data read from the auxiliary data memory 140 and the data read from the data memory 130 are compared with each other by the comparator 172.
Are compared with each other (step S506). Then, the comparator 17
It is output to the processor 200 through the signal line 205 whether or not the data match in 2 and the comparator 161
Is output to the processor 200 through the signal line 206. As shown in FIG. 6, when the data read from the auxiliary data memory 140 and the data read from the data memory 130 do not match (step S701) and there is a cache hit (step S702), the processor 200
An interrupt processing circuit (not shown) therein generates an interrupt signal indicating the occurrence of a failure (step S703).

On the other hand, when the instruction is the store instruction (step S511), the comparator 12 in the auxiliary address array 120 is used.
When a match is detected in any of 3 (step S51
2) The occurrence of an interrupt by the monitoring target register 121 is checked (step S513). The check of this interrupt is the same as that of the above-mentioned FIG. If the mode held in the mode holding circuit 171 is the store mode (step S515) and the output of the comparator 161 indicates a cache hit (step S516),
Store data is written in the auxiliary data memory 140 (step S517).

If it is a cache fill (step S521), and if a match is detected by any of the comparators 123 in the auxiliary address array 120 (step S522), the interruption in FIG. 5 is generated. Check (step S523). If no match is detected in step S522, the mode held in the mode holding circuit 171 is the dynamic mode (step S5).
31), the address that is the target of cache filling is registered in the auxiliary address array 120 (step S53).
2). If it is determined in step S522 that the addresses match, or if it is determined in step S531 that the mode is the dynamic mode, the cache fill data is written to the auxiliary data memory 140 (step S517).

As described above, according to the first embodiment of the present invention, since the auxiliary address array 120, the auxiliary data memory 140 and the comparator 172 are newly provided, the error generated in the data memory 130 is high. It can be detected by the coverage rate. Further, by setting the store mode held in the mode holding circuit 171 to the inactive state, the auxiliary data memory 140 by the store instruction is stored.
Data can be collected by dividing the writing to the. Further, by setting the dynamic mode held in the mode holding circuit 171 to the inactive state, it is possible to suppress the update of the auxiliary address array 120 and collect the data with respect to the address designated by the initial setting. In order to collect these data, it is possible to set an interrupt generation condition in the monitoring target register 121 and generate an interrupt when a predetermined instruction 1212 is executed a predetermined number of times 1211 for a predetermined address 1213.

Next, a second embodiment of the cache memory of the present invention will be described.

Referring to FIG. 7, the auxiliary address array 120 according to the second embodiment is similar to the instruction register 151.
A signal line 199 (not shown in FIG. 2) is input to the comparator 127, and the address 12
13 is the same as that of the first embodiment described with reference to FIG. 3 except that it is compared with a monitoring register number 1214 provided in place of 13. In the second embodiment of FIG. 7, it is possible to generate an interrupt for a load instruction or a store instruction that occurs with respect to the register designated by the monitoring register number 1214. That is, as in the first embodiment shown in FIG. 3, when the comparators 126 and 127 detect the coincidence, the AND circuit 128 causes the incrementer 1202.
The counter 1201 is incremented by "1". When the number of times comparator 129 detects that the number of times indicated by the counter 1202 matches the expected number of times 1211, it outputs an interrupt signal to the signal line 207. As a result, it is possible to specify the number of times a given instruction has been executed for a given register number, generate an interrupt, and collect the state of the cache memory.

As described above, according to the second embodiment of the present invention, in order to collect the above-mentioned data, the interrupt generation condition is set in the monitoring target register 121, and the predetermined instruction for the predetermined register number 1214 is set. 1212 a predetermined number of times 12
An interrupt can be generated when executing for 11 minutes.

[0050]

As is apparent from the above description, according to the present invention, it is possible to detect a physical failure of a data array in a cache memory with high coverage. Moreover, flexible data collection can be performed by setting various modes. Furthermore, when a predetermined command is executed a predetermined number of times, an interrupt can be generated to collect data.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a computer system to which a cache memory of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of an embodiment of a cache memory of the present invention.

FIG. 3 is a block diagram showing a configuration of an auxiliary address array in the cache memory according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an operation of the embodiment of the cache memory of the present invention.

FIG. 5 is a diagram showing an interrupt determination procedure in the embodiment of the cache memory of the present invention.

FIG. 6 is a diagram showing a hit determination procedure in the embodiment of the cache memory of the present invention.

FIG. 7 is a block diagram showing a configuration of an auxiliary address array in the second embodiment of the cache memory of the present invention.

[Explanation of symbols]

100 cash memory 110 address array 120 auxiliary address array 121 Monitoring target register 122 address register 123,126,127 comparator 124 encoder 125 decoder 128 AND circuit 129 Time comparator 130 data memory 140 auxiliary data memory 151 instruction register 152 address register 153 Store data register 154 fill buffer 155 Miss processing circuit 156 decoder 157-159 Selector 161,172 comparator 171 mode holding circuit 173 Load data register 200 processors 300 main memory 400 diagnostic device

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Claims (10)

(57) [Claims] 1. A cache memory having an address array for storing addresses and a data memory for storing data corresponding to the addresses stored in the address array, wherein at least one copy of the addresses stored in the address array is An auxiliary address array to be stored in each entry, an auxiliary data memory to store the data stored in the data memory corresponding to the address stored in each entry of the auxiliary address array, and an auxiliary data memory to be stored in the auxiliary data memory. A comparator for detecting whether the stored contents match the contents of the data memory, and a mode holding circuit for holding the store mode, and the data memory when the store mode is active.
Write to memory is reflected in the auxiliary data memory,
Data memory if tore mode is not active
Of the writing to the cache fill,
A cache memory characterized by being reflected in the auxiliary data memory . Wherein said comparator outputs a valid value when the storage mode is active, according to claim 1, wherein the storage mode is characterized in that it does not output the valid value when not active Cache memory. 3. The mode holding circuit further holds a dynamic mode, and when the address array is updated by cache fill, the same update content is reflected in the auxiliary address array when the dynamic mode is active. The cache memory according to claim 2 , wherein when the dynamic mode is not active, it is not reflected in the auxiliary address array. 4. The auxiliary address array has a monitoring target register for which an interrupt generation condition is set, and whether or not the conditions set in the monitoring target register match.
Or detecting a cache memory according to claim 1, characterized in that it comprises a match is detected and interrupts to notify the occurrence <br/> Ru coincidence detector. 5. The coincidence detector is configured to detect a specific condition among the conditions set in the monitoring target register.
A detector that detects whether or not the items match, and a counter that counts in response to the match detection by the detector.
Is set in the output of the counter and the register to be monitored.
A count comparator that compares the expected value with the expected value.
Characterized by notifying the occurrence of an interrupt when they match
The cache memory according to claim 4, wherein 6. The monitoring target register is the specific section.
6. The cache memory according to claim 5 , wherein an instruction code and an access destination address are held as a condition. 7. The monitoring target register is the specific section.
6. The cache memory according to claim 5 , wherein an instruction code and a register number are held as a condition. 8. An address array for storing addresses,
A data memory for storing data corresponding to the addresses stored in the address array, an auxiliary address array for storing at least one copy of the addresses stored in the address array in each entry, and an auxiliary address array A failure detection method in a cache memory, comprising: an auxiliary data memory that stores data stored in the data memory corresponding to an address stored in each entry; and a mode holding circuit that holds a store mode. When the mode is active, both the cache fill and the store instruction among the writes to the data memory are reflected in the auxiliary data memory, and when the store mode is not active, the cache fill among the writes to the data memory is reflected. By the above It is controlled so that the contents stored in the auxiliary data memory are not reflected, and whether the contents stored in the auxiliary data memory match the contents of the data memory when the store mode is active. A method for detecting a failure in a cache memory, which outputs a signal, and generates an interrupt signal indicating a failure if a cache hit occurs when it is determined that they match. 9. The mode holding circuit further holds a dynamic mode, and when the address array is updated by cache fill, the same update content is reflected in the auxiliary address array when the dynamic mode is active. 9. The method according to claim 8 , wherein when the dynamic mode is not active, it is not reflected in the auxiliary address array. 10. A method of detecting a failure in the cache memory, further comprising generating an interrupt when a predetermined condition is satisfied a predetermined number of times, and generating an address when the interrupt occurs, the address array, the data memory, the auxiliary address array, and 10. The method for detecting a failure in a cache memory according to claim 9 , wherein the contents of the auxiliary data memory are collected.