JP3168489B2 - TLB control method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a translation lookaside buffer of a full associative system.
er: Hereinafter, a TLB control method and apparatus in a microprocessor (hereinafter, abbreviated as MPU) having a TLB, particularly when the MPU does not have a specific mask level in exception processing in which TLB fault processing is performed. T at
The present invention relates to an LB control method and apparatus .

For example, in a 68000-series MPU, TLB
When a fault occurs, the MPU is notified as a bus error and is processed. Also 68000
Even if a bus error occurs and the bus error exception handling starts to operate, the
The mask level of U is maintained at the program running level before the bus error occurred. Usually, the mask level is set by the first instruction in the exception processing of the bus error. After setting to the maximum value (level 7), bus error processing is performed.

However, if there is an interrupt factor of a higher level than the program running level at that time between the stack operation for the exception processing of the bus error and the first instruction in the bus error exception processing, the bus operation is stopped. The interrupt is accepted before the first instruction in the error exception processing is executed, and the interrupt processing is performed with priority.

[0004] Therefore, in such a type of MPU, when a program is operating in a multi-task environment, a request for TLB fault processing is sent to an area common to each process to bus error processing. Occurs twice, so that two entries for the same address are T
By setting to LB, a double select error is likely to occur, but even in such a case, it is required to be able to correctly convert a logical page address to a physical page address.

[0005]

2. Description of the Related Art FIG. 6 shows a conventional system configuration to which the present invention is applied, wherein 1 indicates an MPU, and 2 indicates a memory management unit (hereinafter referred to as M).
MU), forming an address translation mechanism for the memory. A memory control unit 3 controls the memory 4.

In FIG. 6, when a logical address is output from the MPU 1, the MMU 2 converts the logical address into a physical address based on the logical address and converts the address into an address line (AD).
R). The memory control unit 3 outputs the data corresponding to the address from the memory 4 by outputting the physical address as a memory address. In the figure, CTL indicates a control line.

FIG. 7 shows the internal logic of a conventional MMU to which the present invention is applied. Reference numeral 11 denotes a TLB corresponding to the number n of entries, in which a logical page address and a physical page address in MPU data are respectively entered. I is an invalid bit indicating that the entry has been invalidated, R is a reference bit indicating that the entry has been referenced (read or written), and C is an update bit indicating that the entry has been updated. . Reference numeral 12 denotes n comparison circuits for comparing a logical page address in an MPU address with a logical page address entered in each TLB. 13
Are n AND circuits, which output a physical page address corresponding to the logical page address of the MPU set in the TLB when the comparison circuits match. Numeral 14 denotes a double select error detection unit which outputs a double select error when two or more comparison circuits match.

[0008] The address of the MPU is composed of a logical page address and an address within a page. MPU data set in the TLB is stored in the memory 4 shown in FIG.
The logical page address and the physical page address are read from an address conversion table stored in advance in the address conversion table. When the comparison circuit 12 detects a match of the logical page address, the physical page address entered in the TLB is output via the AND circuit 13, and the in-page address in the MPU address is added without conversion. A physical address (memory address) for the memory control unit 3 shown in FIG. 6 is generated.

At this time, if the program erroneously sets two or more identical entries in the TLB, an erroneous address is output by selecting two physical addresses, so that a double select error occurs. A double select error is output by the detection unit 14, and the address output in this case is invalidated.

FIG. 8 shows a conventional TLB control system, and illustrates a case of a multi-task process in which processes 1 and 2 are processed. First, when an address A having a common area is accessed in the process 1,
If a TLB fault occurs because the TLB entry for address A is not set in the TLB, this TLB
The B fault is notified to the MPU by a bus error interrupt.

The MPU performs a bus error process as an exception process for a running program based on an interrupt. Therefore, a stack process for saving necessary minimum hardware information such as register information in a process to a stack area. To start. For MPUs such as the 68000 series,
During this stack processing, if there is an interrupt request of a higher level than the current running level, this interrupt will be accepted before executing the first instruction of the bus error processing. Stack processing is performed for the processing. Then, following the stack processing, the cause of the interrupt is determined and processing for the cause is performed. This process is performed as an extension of the interrupt process, and it is assumed that another process (process 2) has started operation.

If the address A in the same common area as the process 1 is accessed during the execution of the process 2, the process 1
Since the TLB fault processing for address A has not been executed yet, the TLB entry for address A has not been set, and a TLB fault occurs again for address A. Since this TLB fault is also notified to the MPU by a bus error, the MPU keeps the TLB fault processing of the address A of the process 1 pending and executes the TLB for the process 2 as a bus error processing.
Execute fault processing first.

The MPU performs stack processing for the process 2, sets the mask level of the interrupt processing to the highest level “7”, clears the TLB fault status (STS) in the MMU, and then stores the TLB entry in the TLB entry. A logical page address corresponding to address A and a corresponding physical page address are set. As a result, the process of the TLB fault for the process 2 is completed. Therefore, the return (RTE) instruction is executed, the stack process of the process 2 is performed, and the information first saved in the process 2 is restored to the original hardware. , Process 2
It returns to the processing of.

By returning to the process 2, the address A is accessed and the process 2 is executed. When process 2 ends, execute RTE,
After performing the stack processing for returning to the bus error processing, the processing returns to the TLB fault processing for the process 1.

The MPU sets the mask level of the interrupt processing to level '7', clears the STS of the TLB fault of the MMU, and then stores the logical page address corresponding to the address A and the corresponding physical address in the TLB entry. Set the page address. At this point, two physical page addresses corresponding to the same logical page address have been entered in the TLB as indicated by *.

As a result, the processing of the TLB fault for the process 1 is completed. After the RTE is executed and the stack processing for returning to the process 1 is performed,
It returns to the processing of.

By returning to the process 1, the address A is accessed, but the address A has already been accessed in the process 2. In this state, the MMU outputs a double select error to notify the MPU, thereby invalidating the address output in this case.

[0018]

In a certain MPU having a TLB of the full associative system and in which the MPU performs the TLB fault processing by the exception processing of the bus error, a specific mask is used for the TLB fault processing.・
Since there is no level, exception processing is interrupted by the occurrence of an interrupt, and TLB fault processing requests are duplicated. Therefore, two physical page addresses are set to one logical page address in the TLB entry, and double A select error occurs.

The present invention is intended to solve such a problem of the prior art. Even when such an MPU is used, a logical page address and a physical page address are always assigned to a TLB entry. It is an object of the present invention to provide a TLB control method and apparatus that can set a correspondence correctly and convert between a logical page address and a physical page address.

[0020]

According to the present invention, there is provided an address conversion table comprising a plurality of entries for setting data indicating correspondence between a logical page address and a physical page address output by a microprocessor (MPU). A translation index buffer (TLB) 11 having a plurality of entries for setting the data for speeding up the address translation is provided on a memory, and a logical page address output by the MPU and a logical page address set in the TLB are provided. It has a full associative memory management unit (MMU) 2 that outputs a physical page address when a match is detected, and a specific mask level in exception processing in which the MPU performs fault processing at the time of address translation in the TLB Interrupt, this exception processing is interrupted by an interrupt. In the system, a flag indicating that data is set in the TLB entry is provided in the address conversion table, and this flag is checked when the correspondence between the logical page address and the physical page address is set in the TLB entry. If the flag is set, the fault processing in the TLB is terminated without setting data in the TLB entry, and if the flag is cleared, the data is set in the TLB entry and the flag is set, thereby setting the TLB. This is to make the logical page address match only for a single entry.

(2) Further, the present invention has an address translation table comprising a plurality of entries for setting data indicating the correspondence between the logical page address and the physical page address output by the MPU 1 in the memory, thereby speeding up the address translation. Consisting of multiple entries to set the data for
LB11, a full associative MMU2 that outputs a physical page address when a match between the logical page address output by the MPU and the logical page address set in the TLB is detected, and the MPU performs address conversion in the TLB. Exception handling for fault handling at the time does not have a specific mask level, this exception handling is interrupted by an interrupt, and T
In a system provided with a double select error detecting unit 14 for detecting that logical page addresses in a plurality of entries of the LB match, a double select error detecting unit performs double-selection of a plurality of entries on the TLB at the time of address translation. When a select error is detected, all entries on the TLB are invalidated, a fault is generated in the TLB by re-access, and then an entry for this logical page address is set in the TLB again, so that the logical page address is correctly set. It is converted to a physical page address.

(3) Further, according to (2), the present invention invalidates only a plurality of entries on the TLB where a double select error is detected for the same logical page address,
After generating a TLB fault by re-access,
Again the entry for this logical page address is TLB
, The logical page address is correctly converted to the physical page address.

(4) Further, the present invention has an address conversion table in the memory, which includes a plurality of entries for setting data indicating the correspondence between the logical page address and the physical page address output by the MPU 1, and speeds up the address conversion. Consisting of multiple entries to set the data for
LB11, a full associative MMU2 that outputs a physical page address when a match between the logical page address output by the MPU and the logical page address set in the TLB is detected, and the MPU performs address conversion in the TLB. Exception handling for fault handling at the time does not have a specific mask level, this exception handling is interrupted by an interrupt, and T
In a system having a double select error detecting unit 14 for detecting that logical page addresses in a plurality of entries of the LB coincide with each other and further having a reference flag and an update flag on the TLB, double select for the same logical page address is performed. T at which an error was detected
By invalidating only the entry for which neither the reference flag nor the update flag is set among the plurality of entries on the LB, the logical page address is correctly converted to the physical page address.

[0024]

(1) In the MMU 2 of the full associative system, a TLB 11 including a plurality of entries is provided.
Data indicating the correspondence between the logical page address and the physical page address output by the MPU 1 is set. And M
When a match between the logical page address output by the PU and the logical page address set in the TLB is detected,
This physical page address is output.

Further, the MPU does not have a specific mask level in exception processing for performing fault processing at the time of address translation in the TLB, and this exception processing is interrupted by an interrupt.

In this case, in the address conversion table,
A flag indicating that data is set in the TLB entry is provided, and this flag is checked when the correspondence between the logical page address and the physical page address is set in the TLB entry. If the flag is set, T
The fault processing in the TLB is completed without setting data in the LB entry, and if the flag is cleared, the data is set in the TLB entry and the flag is set.

As described above, in the present invention, the occurrence of a double select error in a TLB entry is prevented by referring to the flag in the address translation table. Therefore, the logical page address of only a single entry in the TLB is always maintained. A match can occur.

(2) MM of full associative system
U2 further includes a double select error detection unit 14 for detecting that the logical page address in a plurality of entries of the TLB matches the logical page address specified by the MPU at the time of address translation.

In this case, when the double select error detector detects a match for a plurality of entries in the TLB at the time of address translation, all entries in the TLB are invalidated, and a fault in the TLB is generated by re-access. After that, the entry for the logical page address is set in the TLB again.

As described above, in the present invention, a double select error is once generated. In this case, all entries on the TLB are invalidated and a TLB fault is generated by re-access, so that a logical page address for the logical page address is again generated. Since the entry is set in the TLB, the logical page address can be correctly converted to the physical page address.

(3) In the case of (2), when a double select error is detected for the same logical page address,
After invalidating only a plurality of entries on the LB and causing a TLB fault by re-access, the TLB entry for this logical page address may be set again, whereby the logical page address is correctly changed to the physical page address. Can be converted to

(4) MM of full associative system
In U2, a reference flag and an update flag are further provided. The reference flag indicates that the address has been referenced (read or written), and the update flag indicates that the address has been updated. .

The logical page address in the entry on the TLB in which the reference flag or the update flag is set has been correctly accessed once, and this address can be immediately accessed and executed.

Accordingly, by invalidating only the entry in which neither the reference flag nor the update flag is set, out of the plurality of entries on the TLB where a double select error is detected for the same logical page address, the Logical page addresses can be translated into physical page addresses.

[0035]

1 and 2 show the operation flow of an embodiment (1) of the present invention. FIG. 1 shows the checking and setting of a flag, and FIG. 2 shows that the TLB entry is full. In this case, the flag is cleared. In the embodiment shown in FIGS. 1 and 2, a 1-bit flag indicating that the data is currently set in the TLB entry is provided for each data on the address conversion table in the memory.

In FIG. 1, when a TLB fault occurs when the process 1 accesses the address A having the common area, the TLB fault is notified to the MPU by a bus error interrupt.

The MPU executes the process 1 based on the interrupt.
Start stack processing for. If there is an interrupt request higher than the current running level during this stack processing, this interrupt is accepted before executing the first instruction of the bus error exception processing. This allows MP
U further performs stack processing for bus error processing. Then, following the stack processing, the cause of the interrupt is determined and processing for the cause is performed. This process is performed as an extension of the interrupt process, and it is assumed that another process (process 2) has started operation.

Assuming that the address A in the same common area as the process 1 is accessed during the execution of the process 2, the process 1
Since the TLB fault processing for address A has not been executed yet, a TLB fault occurs again for address A. Since the TLB fault is also notified to the MPU by a bus error, the MPU first performs the TLB fault process for the process 2 as a bus error process while leaving the TLB fault process of the address A of the process 1 in the pending state. Execute.

The MPU performs the stack processing for the process 2, sets the mask level of the interrupt processing to the level '7', and sets the STS of the MLB's TLB fault.
Is cleared, the flag of the address A in the address conversion table is checked. At this time, since the data of the MPU is not set in the TLB entry, the flag is “0”.

In the MMU, a logical page address corresponding to address A and a corresponding physical page address are set in the TLB entry. At this time, the flag of the address A in the address conversion table is set to “1” to indicate that this entry is currently set in the TLB.

As a result, the process of the TLB fault for the process 2 is completed, so that the RTE is executed, and the stack process for returning to the process 2 is performed.
It returns to the processing of.

By returning to the process 2, the address A is accessed and the process 2 is executed. When the processing of the process 2 is completed, the RTE is executed, the stack processing for returning to the bus error processing is performed, and then the processing returns to the TLB fault processing for the process 1.

The MPU sets the mask level of the interrupt processing to level '7', clears the STS of the TLB fault in the MMU, and then checks the flag of the address A in the address conversion table. In this case, since the flag has already been set to "1", no processing is performed in this TLB fault processing. Therefore,
The correspondence between the logical page address and the physical page address for address A is not erroneously set in another TLB entry.

After the TLB process, the RTE is executed, the stack process for returning to the process 1 is performed, and then the process returns to the process 1. By returning to the processing of the process 1, when the address A is accessed, the processing of the address A is correctly performed.

The flag on the address conversion table for address A is subsequently set to "0" when the entry at address A is invalidated in order to set the correspondence between another logical page address and physical page address. Cleared.

In FIG. 2, in process 1, B
When the address is accessed, the TLB entry is full, so the address B cannot be set in the TLB entry, and if a TLB fault occurs, this TLB
The fault is notified to the MPU by a bus error interrupt.

Based on the interrupt, the MPU performs stack processing for the process 1 in order to perform TLB fault processing of the process 1 as exception processing for bus error processing. Then, the mask level of the interrupt processing is set to level “7”, and the SLB of the TLB fault of the MMU is set.
Clear TS. Then, for example, the flag of the address A in the address conversion table is cleared, and the entry of the address A in the TLB is purged.

Next, when the flag at address B in the address conversion table is checked, it is set to "1" because it is "0". Then, in the MMU, the TLB
In the entry, a logical page address corresponding to address B,
Set the corresponding physical page address.

Thus, the process of the TLB fault for the process 1 is completed. The RTE is executed, the stack process for returning to the process 1 is performed, and then the process 1
By returning to the processing of (1) and accessing the address B, the processing of the process 1 is executed.

FIGS. 3 and 4 show an embodiment (2) of the present invention.
FIG. 3 shows TL again.
FIG. 4 shows a case (1) in which a B fault is generated, and FIG. 4 shows a case (2) in which a TLB fault is generated again.

As described with reference to FIG. 8, first, the TPU fault that occurred at address A of the common area in process 1 causes the MPU to execute the bus error exception processing during the stack processing for executing the bus error exception processing. When an interrupt request with a higher priority is accepted, the MPU
By executing a stack process for the other process and performing a process for the interrupt factor to obtain another process (process 2).
Starts working.

When the address A is accessed again during the execution of the process 2, the TL is also accessed for the address A in the process 2.
A B fault occurs. This TLB fault is also notified to the MPU by a bus error, and the TLB of the address A of the process 1 is processed.
With the fault process pending, the TLB fault process for process 2 is executed first, and the correspondence between the logical page address and physical page address for address A is set in the TLB entry.

When the TLB fault processing (bus error processing) is completed, the process returns to the process 2, the address A is accessed, and the processing of the process 2 is continued. When the processing is completed, the interrupted process 1 is executed. The processing returns to the bus error processing for. In this bus error processing, a TLB fault processing is executed for the interrupted address A,
The correspondence between the logical page address and the physical page address for address A is set in another TLB entry.

When the process returns from the TLB fault process to the process 1 and accesses the address A, a double select error occurs because there are a plurality of matching entries on the TLB.

In FIG. 3, in process 1, the common area A
If a double select error occurs when accessing an address, the double select error is
Is notified by a bus error interrupt.

The MPU executes the process 1 based on the interrupt.
Stack processing is performed for
The level is set to level '7', and the STS of the double select error in the MMU is cleared. Then, purge all entries in the TLB.

Next, the RTE is executed, a stack process for returning to the process 1 is performed, and then the process returns to the process 1 to access the address A. In this case, since the TLB entry is invalidated, a TLB fault occurs again. This TLB fault is notified to the MPU by a bus error interrupt.

The MPU executes the process 1 based on the interrupt.
Stack processing is performed for
Set the level to level '7' and set the T
Clear the LB fault STS. After that, a TLB entry for address A is set. This terminates the TLB fault processing for process 1.
After executing the RTE and performing the stack processing for returning to the process 1, the processing returns to the processing of the process 1.

In the process 1 in this case, since the TLB entry for the address A is set, it is possible to correctly access the address A, and the process 1 is executed.

As described above, a double select error is generated once, but then, a retry is performed without causing the system to go down, and a TLB fault is generated again. An entry can be set.

As another method, as shown in FIG. 4, when a double select error occurs by accessing the address A of the common area in the process 1, a double select error is sent to the MPU. After notifying by a bus error interrupt, the MPU performs stack processing for process 1, sets the mask level of the interrupt processing to level '7', and clears the STS of the double select error in the MMU. And TLB
May be purged.

The subsequent processing is the same as in FIG.
After executing the TE and performing the stack processing for returning to the process 1, when returning to the processing of the process 1 and accessing the address A, a TLB fault occurs because the TLB entry is not performed in this case as well. This TLB fault is notified to the MPU by a bus error interrupt.

After performing stack processing for process 1, the MPU sets the mask level for interrupt processing to level '7', clears the STS of the TLB fault in the MMU, and sets an entry for address A in the TLB. I do. Then, the RTE is executed, the stack process for returning to the process 1 is performed, and then the process returns to the process 1. Thus, when the address A is accessed, the processing of the process 1 is executed.

As described above, in the method of generating a TLB fault again, in the method of purging all entries as shown in FIG.
Since LB entries are also purged, system performance may degrade. On the other hand, in the method shown in FIG. 4, only the TLB entry corresponding to the process in which the double select error has occurred is purged to generate a TLB fault, and the TLB fault processing is performed, whereby correct execution can be performed. To do. Therefore, T other than address A
For the LB entry, since no TLB fault occurs, it can be executed immediately, and the system performance does not decrease so much.

FIG. 5 shows the embodiment (2) of the present invention, and shows a case where a TLB fault is not generated again. In FIG. 5, when the address A of the common area is accessed in the process 1, the double select
If an error occurs, the double select error is M
The PU is notified by a bus error interrupt.

The MPU executes the process 1 based on the interrupt.
Stack processing is performed for
The level is set to level '7', and the STS of the double select error in the MMU is cleared. After that, among the entries at the address A in the TLB, the entry in which the reference bit R and the update bit C are not set is purged.

Next, the RTE is executed, a stack process for returning to the process 1 is performed, and then the process returns to the process 1 and the address A is accessed, whereby the process of the process 1 for the address A is executed. .

When a double select error occurs at address A, as described with reference to FIG. 8, the address A is once correctly accessed. For the entry in this case, the reference bit R is set for read, and the update bit C is set for write (update). Therefore, without purging such an entry, all the contents of the entry at the address A in the TLB where both the R bit and the C bit are not set are purged.

In this way, when the RTE is executed and the stack processing for returning to the process 1 is performed, only the TLB entry corresponding to the correctly accessed address A remains. , Process 1 can be executed. In this method, it is not necessary to generate a TLB fault for address A, so that overhead can be reduced.
System performance can be further improved.

In the methods described with reference to FIGS. 3 to 5, the overhead of the normal TLB fault processing is not required, so that the system performance can be further improved.
In this case, an entry in the TLB is purged after a double select error is generated, and the address A is processed. However, the double select error occurs only when a bus error occurs. Since there is only a higher priority interrupt before the first instruction of the process is executed, the frequency of occurrence is considerably lower, and there is little risk of degrading system performance.

[0071]

As described above, according to the present invention, T
In a system using an MPU to which a specific high mask level is not assigned for a bus error exception handling for handling an LB fault, a plurality of physical page addresses are incorrect for one logical page address. Thus, it is possible to always correctly set the correspondence between the logical page address and the physical page address in the TLB entry.

[Brief description of the drawings]

FIG. 1 shows an operation flow of an embodiment (1) of the present invention.
It is a figure which shows a check of a flag and a set.

FIG. 2 shows an operation flow of an embodiment (1) of the present invention.
FIG. 14 is a diagram illustrating clearing of a flag when a TLB entry is full.

FIG. 3 shows an operation flow of the embodiment (2) of the present invention.
FIG. 9 is a diagram illustrating a case (1) in which a TLB fault is generated again.

FIG. 4 shows an operation flow of the embodiment (2) of the present invention.
FIG. 9 is a diagram illustrating a case (2) in which a TLB fault is generated again.

FIG. 5 shows an operation flow of the embodiment (2) of the present invention.
FIG. 11 is a diagram illustrating a case where a TLB fault is not generated again.

FIG. 6 is a diagram showing a conventional system configuration to which the present invention is applied.

FIG. 7 is a diagram showing the internal logic of a conventional MMU and to which the present invention is applied.

FIG. 8 is a diagram showing a conventional TLB control method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microprocessor (MPU) 2 Memory management unit (MMU) 11 Conversion look-up buffer (TLB) 14 Double select error detector

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-49-60640 (JP, A) JP-A-2-300951 (JP, A) JP-A-3-235148 (JP, A) JP-A-2- 23431 (JP, A) JP-A-63-241637 (JP, A) JP-A-58-57688 (JP, A) JP-A-61-173359 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) G06F 12/08-12/12

Claims (4)

(57) [Claims] An address conversion table comprising a plurality of entries for setting data indicating correspondence between a logical page address and a physical page address output by a microprocessor (hereinafter abbreviated as MPU) is provided in a memory, and a high-speed address conversion is performed. Conversion index buffer (hereinafter abbreviated to TLB) consisting of a plurality of entries for setting the data for data conversion
And the logical page address output by the MPU and the TL
A memory that outputs the physical page address when a match with the logical page address set in B is detected.
In a system having a management unit (hereinafter abbreviated as MMU), the MPU does not have a specific mask level in exception processing for performing fault processing at the time of address translation in TLB, and the exception processing is interrupted by an interrupt, A flag indicating that the data is set in the TLB entry is provided in the address conversion table, and the correspondence between the logical page address and the physical page address is set to T.
When the flag is set in the LB entry, the flag is checked. If the flag is set, the fault processing in the TLB is terminated without setting data in the TLB entry. If the flag is cleared, the TLB is cleared. A TLB control method comprising: setting data in an entry and setting the flag so that the logical page address matches only for a single entry in the TLB. 2. An address conversion table comprising a plurality of entries for setting data indicating a correspondence between a logical page address and a physical page address output by an MPU is provided in a memory. MPU with TLB consisting of multiple entries to be set
Has an MMU that outputs the physical page address when a match between the logical page address output from the TLB and the logical page address set in the TLB is detected.
In the exception processing for performing the fault processing at the time of address conversion in the LB, the exception processing does not have a specific mask level, and the exception processing is interrupted by an interrupt. In a system having a double select error detecting unit for detecting that logical page addresses in a plurality of entries match, and further having a reference flag and an update flag on a TLB, the double select error is detected for the same logical page address. Invalidates only the entry for which both the reference flag and the update flag are not set out of the plurality of entries on the TLB in which is detected, thereby correctly converting the logical page address to the physical page address. TLB control method . 3. An address translation table comprising a plurality of entries for setting data indicating correspondence between a logical page address and a physical page address output by a microprocessor (hereinafter abbreviated as MPU) is provided in a memory, and a high-speed address translation is performed. Conversion index buffer (hereinafter abbreviated to TLB) consisting of a plurality of entries for setting the data for data conversion
And the logical page address output by the MPU and the TL
A memory that outputs the physical page address when a match with the logical page address set in B is detected.
In a system having a management unit (hereinafter abbreviated as MMU), the MPU does not have a specific mask level in exception processing for performing fault processing at the time of address translation in TLB, and the exception processing is interrupted by an interrupt, in said address conversion table, the data is checked to the flag when set may be provided a flag indicating that is set in the TLB entry, the correspondence between the logical page address and the physical page address in the TLB entry Means and TL if the flag is set
Means for terminating the fault processing in the TLB without setting data in the B entry and, if the flag is cleared, setting data and setting the flag in the TLB entry. T
LB control device . 4. An address conversion table comprising a plurality of entries for setting data indicating a correspondence between a logical page address and a physical page address output by an MPU is provided in a memory. MPU with TLB consisting of multiple entries to be set
Has an MMU that outputs the physical page address when a match between the logical page address output from the TLB and the logical page address set in the TLB is detected.
In the exception processing for performing the fault processing at the time of address conversion in the LB, the exception processing does not have a specific mask level, the exception processing is interrupted by an interrupt, and the TLB of the logical page address specified by the MPU at the time of the address conversion is used. In a system having a double select error detecting unit for detecting that logical page addresses in a plurality of entries match, and further having a reference flag and an update flag on a TLB, the double select error is detected for the same logical page address. A TLB control device comprising means for invalidating only an entry in which both the reference flag and the update flag are not set, among a plurality of entries on the TLB in which is detected.