JP2658342B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a data processing apparatus that performs debugging for finding a hardware failure by matching instruction addresses.

[Conventional technology]

Conventionally, debugging by matching instruction addresses has been performed by holding the address to be debugged in a register and comparing the address held in the register with the address to be matched.

[Problems to be solved by the invention]

The conventional debug method based on address matching described above has a drawback that if a match is to be detected for a plurality of addresses because the data is held in a register, a corresponding register is required. There is a disadvantage that it cannot be stopped when it is desired.

[Means for solving the problem]

The data processing apparatus of the present invention has a branch history table for storing the address of a branch instruction and the branch destination address of the branch instruction in a pair. In the data processing apparatus for prefetching an instruction, the branch history is stored in accordance with an instruction fetch address. Index means for indexing a table, and first storage means for storing information corresponding to each entry of the branch history table, the information indicating that the address of the debug target instruction is stored in the entry instead of the address of the branch instruction When,
Second storage means for storing the remaining number of times that the debug target instruction address can be accessed until a debug interrupt is generated, corresponding to each entry of the branch history table; If it is detected that the instruction addresses stored in the history table match, and if the first storage unit determines that the address is a debug target address, if the remaining number of times by the second storage unit is a specified value, Means for updating the remaining number of the second storage means if a debug interrupt is generated and the remaining number of times by the second storage means is other than a certain specified value.

(Operation)

Since the debug target instruction address is stored in the branch history table, an increase in hardware can be reduced when a match is to be detected for a plurality of addresses. In addition, a debug interrupt can be generated during repeated execution.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the data processing device of the present invention.

The instruction address register 1 receives an instruction prefetch address. The instruction address register 1 receives an instruction prefetch address sent from an address generation circuit (not shown) via a signal line 101, and outputs the lower bits of the instruction address via a signal line 103. As addresses, branch address memory 2, branch destination address memory 3, debug information memory 4, and debug number memory 5
And to the branch address comparison circuit 6 via the upper bit signal line 102. The branch address memory 2 is a memory for storing the address of the branch instruction and the address to be matched by debugging, and stores the lower bits of the instruction address sent from the instruction address register 1 via the signal line 103 as an address. The upper bits of the instruction address are sent to the branch address comparison circuit 6 via the signal line 104. The branch destination address memory 3 is a memory that holds a branch destination address corresponding to the branch address memory 2.
Using the lower bits of the instruction address sent from the instruction address register 1 via the signal line 103 as an address, the predicted branch destination address is sent to the predicted branch destination address register 8 via the signal line 105. The debug information memory 4 is a memory that indicates whether or not the address is to be debugged, corresponding to the branch address memory 2, and stores the lower bits of the instruction address sent from the instruction address register 1 via the signal line 103 as an address. As a result, whether the address is to be debugged is transmitted to the AND circuit 11 and the nut circuit 10 via the signal line 106. The debug number memory 5 is a memory indicating the remaining number of times the debug target address can be accessed until a debug interrupt occurs, and the lower bit of the instruction address sent from the instruction address register 1 via the signal line 103 is used as the address. The remaining number is sent to the zero check circuit 12 and the remaining number counter 13 via the signal line 107, and the output of the remaining number counter 13 is received via the signal line 114. The branch address comparison circuit 6 stores the branch address memory 2
Is a comparator for checking whether or not the address stored in the instruction address matches the instruction address in the instruction address register 1. The upper bit of the instruction address sent from the instruction address register 1 via the signal line 102 and the branch address The upper bits of the instruction address sent from the memory 2 via the signal line 104 are compared, and the result is sent to the AND circuits 14 and 11 via the signal line 114. The predicted branch destination detection flag 7 is an F / F indicating whether a predicted branch destination has been detected by instruction prefetching, and sends the comparison result sent from the AND circuit 14 to the address generation circuit via the signal line 111. The predicted branch destination address register 8 receives the predicted branch destination address sent from the branch destination address memory 3 via the signal line 105 in synchronization with the predicted branch destination detection flag 7, and receives the predicted branch destination address. It is sent to the address generation circuit via 112. The pseudo fault flag 9 is an F / F indicating that the instruction of the debug target address has been prefetched, receives a match signal with the debug target address sent from the AND circuit 11 via the signal line 109, and receives the signal via the signal line 113. To a preceding control circuit (not shown). Nut circuit
Numeral 10 indicates that the address held in the instruction address register 1 is not a debug target address, and the negation of the debug information sent from the debug information memory 4 via the signal line 106 is performed via the signal line 115. AND circuit 14
To send to. The AND circuit 11 is a circuit for indicating that a debug target address is prefetched, thereby causing a false fault. The AND circuit 11 uses the signal coincidence information sent from the branch address comparison circuit 6 via the signal line 114 to generate a signal line 106.
From the debug information transmitted from the debug information memory 4 via the signal line 115 and the information on the remaining number of times 0 transmitted from the zero check circuit 12 via the signal line 115, and generates a pseudo fault flag via the signal line 109. 9 The zero check circuit 12 is a circuit for checking that the remaining number of times until the occurrence of the false fault is 0, receives the remaining number of times transmitted via the signal line 107 from the debug number memory 5, and it is "0". Information on whether or not is sent to the AND circuit 11 via the signal line 115. The remaining number counter 13 is a circuit for reducing the remaining number by one. The remaining number counter 13 receives the remaining number sent from the debug number memory 5 via the signal line 107, reduces the received number by one, and returns the debug information again via the signal line 114. Send it to memory 4. The AND circuit 14 is a circuit for indicating that a predicted branch destination address has been detected. Information indicating that the address of the instruction address register 1 matches the address of the branch address memory 2 is transmitted via a signal line 114. If the address is not a debug target from the line 115, the fact that the predicted branch destination address has been detected is sent to the predicted branch destination detection flag 7 via the signal line 108.

 Next, the operation of this embodiment will be briefly described.

First, during normal branch prediction, since the debug information memory 4 is "0", when the instruction address register 1 and the branch address memory 2 match, the signal line 114 becomes "1".
Since the signal line 106 is "0", the signal line 115 becomes "1", the predicted branch destination detection flag 7 is "1", and the pseudo fault flag 9 is "0".
It can be seen that the predicted branch destination address has been detected.

Next, since the debug information memory 4 is "1" when the address is the debug target address, the instruction address register 1
And the branch address memory 2 match, the signal line 11
4 is “1” and the signal line 106 is “1”,
115 becomes "0" and the predicted branch destination detection flag 7 is not turned on. At this time, the remaining number of times indicated by the debug number memory 5 is “0”.
If not, the signal line 115 becomes "0" and the pseudo fault flag 9 is not turned on. At this time, the remaining count is decremented by -1 by the remaining count counter 13 and the value is stored in the debug count memory 5. When the debug count memory 5 becomes “0”,
The output 115 of the zero check circuit 12 becomes "1", and the pseudo fault flag 9 is turned on.

〔The invention's effect〕

As described above, according to the present invention, by using the configuration of the branch history table, a plurality of debug addresses can be set with a small increase in the amount of hardware,
Also, there is an effect that a debug interrupt can be generated in the middle of repeated execution.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the data processing device of the present invention. 1 ... instruction address register, 2 ... branch address memory, 3 ... branch destination address memory, 4 ... debug information memory, 5 ... debug number memory, 6 ... branch address comparison circuit, 7 ... predicted branch destination Detection flag, 8: Predictive branch destination address register, 9: Pseudo fault flag, 10: Nut circuit, 11, 14: AND circuit, 12: Zero check circuit, 13: Remaining counter.

Claims (1)

(57) [Claims] 1. A data processing apparatus for prefetching an instruction, comprising: a branch history table for storing an address of a branch instruction and a branch destination address of the branch instruction in a pair, wherein the branch history table is indexed by an instruction fetch address. Index storage means for storing information indicating that the instruction address corresponding to each entry of the branch history table is stored in place of the address of the branch instruction instead of the address of the branch instruction; Second storage means for storing the remaining number of times that the debug target instruction address can be accessed until a debug interrupt is generated, corresponding to each entry of the branch history table; an instruction prefetch address and the branch history by the index means; It is detected that the instruction addresses stored in the table match, and the first If it is determined by the storage means that the address is a debug target address, a debug interrupt is generated if the remaining number of times by the second storage means is a specified value, and the remaining number of times by the second storage means is a specified value. A data processing apparatus comprising means for updating the remaining number of times in the second storage means if the status is other than the above.