JP2000305840A - Cache memory and its fault detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely detect an error in a cache memory due to a miss on logical design or a data change. SOLUTION: A cache memory 100 having an auxiliary address array 120 for storing a copy of a part of an address array 110 and an auxiliary data memory 140 for storing a copy of a part of a data memory 130 detects the non-coincidence of contents between both the memories 130, 140 by a comparator 172. A mode storing circuit 171 stores a storage mode indicating whether write based on a storing instruction is to be reflected to the memory 140 or not and a dynamic mode indicating whether a fill due to a cache miss is to be reflected to the array 120 or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache memory, and more particularly to a cache memory having a diagnostic function and a diagnostic method thereof.

[0002]

2. Description of the Related Art The improvement in the degree of integration and operating frequency of processors has made it possible for computer systems to process a large amount of data in a short time. However, the operation frequency of the main storage device is improved more slowly than that of the processor, and much time is spent in reading or writing data, thereby hindering improvement in the processing performance of the entire computer system. For this reason, a cache memory has been developed in which a copy of the main storage device is retained in the processor and data can be read or written at high speed. As a result, frequently referenced data can be loaded at a high speed, and the problem that data supply becomes a performance bottleneck has been solved.

[0003]

However, the update of the contents of the cache memory is generally asynchronous, and often operates at a timing that is not assumed in the design stage. Design errors may remain. If a problem occurs during the evaluation or verification stage on the actual machine, the update is performed asynchronously, so even if the instruction tracer can collect it as an error log, it is difficult to identify the update timing of the address that caused the error . For this reason, even if it turns out that the data read from the cache memory is incorrect, it is difficult to determine when data is updated and what data is loaded from the memory.

Further, a random access memory (RA)
In contrast to the failure in M), the conventional parity check method cannot detect a failure when the parity bits coincide with each other due to an intermittent failure, and the coverage of the check is low. Also,
Even if the mismatch of the read data is detected, there is a problem that the determination as to whether it is due to a failure or a logic design error is delayed.

On the other hand, for example, Japanese Patent Laid-Open No. 27555/1982
Japanese Patent Laid-Open Publication No. 1 (1999) discloses a debugging device that compares two data read from a cache memory and a main memory to detect a mismatch. However, in the device described in this document, access to the main memory is required for error detection, which not only degrades performance, but also has different operation timing between the debug mode and the normal operation mode, resulting in poor reproducibility. There is also a problem that it cannot be guaranteed.

An object of the present invention is to solve the conventional problems,
An object of the present invention is to reliably detect an error in a cache memory.

[0007]

In order to solve the above-mentioned problems, a cache memory according to the present invention has therein an auxiliary data memory for storing at least a part of the contents stored in the cache memory. If the content does not match the cache memory, it is detected that a failure has occurred in the cache memory.

Further, another cache memory of the present invention comprises:
In a cache memory having an address array for storing addresses and a data memory for storing data corresponding to the addresses stored in the address array, at least one copy of the addresses stored in the address array is stored in each entry. An auxiliary address array, an auxiliary data memory for storing data stored in the data memory corresponding to an address stored in each entry of the auxiliary address array, and a content stored in the auxiliary data memory. And a comparator for detecting whether or not the contents match the contents of the memory.

Further, another cache memory of the present invention comprises:
A mode holding circuit for holding a store mode,
When the store mode is active, any of the cache fill and store instructions among the writes to the data memory are reflected in the auxiliary data memory, and when the store mode is not active, the write to the data memory is performed. The result of the cache fill is reflected in the auxiliary data memory, and the result of the store instruction is not reflected.

In another cache memory according to the present invention, the comparator outputs a valid value when the store mode is active, and does not output a valid value when the store mode is not active.

In another cache memory according to the present invention, the mode holding circuit further holds a dynamic mode. When the address array is updated by a cache fill, if the dynamic mode is active, the auxiliary address The same update content is reflected in the array, and is not reflected in the auxiliary address array when the dynamic mode is not active.

In another cache memory according to the present invention, the auxiliary address array detects a monitored register in which an interrupt generation condition is set, and detects whether the condition set in the monitored register is met. A match detector.

In another cache memory according to the present invention, the monitoring target register holds an instruction code and an access destination address as an interrupt occurrence condition.

In another cache memory according to the present invention, the address array includes a counter that counts in response to a condition match in the match detector and an output of the counter as one input and another input. A number comparator for detecting a match, wherein the monitored register further holds an expected value of the number of detections in the match detector, and the number comparator has a value of the counter held in the monitored register. Notifies the occurrence of an interrupt when the value matches the expected value.

In another cache memory according to the present invention, the register to be monitored holds an instruction code and a register number as an interrupt occurrence condition.

In another cache memory according to the present invention, the address array includes a counter counted in response to a condition match in the match detector, and an output of the counter as one input and another input. A number comparator for detecting a match, wherein the register to be monitored further holds an expected value of the number of times of detection in the match detector, and the number of comparators holds the value of the counter in the register to be monitored. Notify that an interrupt has occurred when the value matches the expected value.

In the method of detecting a failure in a cache memory according to the present invention, an address array for storing an address, a data memory for storing data corresponding to an address stored in the address array, and a data memory for storing data in the address array are provided. An auxiliary address array for storing at least one copy of the address in each entry thereof; and an auxiliary data memory for storing data stored in the data memory corresponding to the address stored in each entry of the auxiliary address array. A failure detection method in a cache memory having a mode holding circuit for holding a store mode, wherein when the store mode is active, any of writing to the data memory by a cache fill and a store instruction is also used as the auxiliary. Reflected in data memory, When the tore mode is not active, control is performed so that the data written to the data memory due to the cache fill is reflected in the auxiliary data memory so that the data written by the store instruction is not reflected. It outputs whether or not the content stored in the data memory matches the content of the data memory. If it is determined that the content matches the content of the data memory, an interrupt signal indicating that a failure has occurred is generated if a cache hit occurs.

In another fault detection method for a cache memory according to the present invention, the mode holding circuit further holds a dynamic mode, and when the dynamic mode is active, updates the auxiliary address array when a cache fill is performed. .

Further, according to another failure detection method for a cache memory of the present invention, an interrupt is generated when a predetermined condition is satisfied a predetermined number of times, and when an interrupt occurs, the address array, the data memory, and the auxiliary address array And the contents of the auxiliary data memory are collected.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a cache memory according to the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a computer system to which the present invention is applied has a processor 200 for performing processing such as arithmetic and the like, and a main storage device 300 for holding data necessary for processing of the processor 200. The cache memory 100 is provided between the main memory 200 and the main memory 300. A diagnostic device 400 that diagnoses the cache memory 100 is connected to the cache memory 100.

Referring to FIG. 2, an embodiment of the cache memory according to the present invention has an address array 110 and a data memory, similarly to a normal cache memory, and accessed addresses are held in the address array 110. The comparator 161 searches for the presence or absence. In the present invention, the auxiliary address array 120 for holding a part of the contents of the address array 110 and the auxiliary data memory 1 for holding a part of the contents of the data memory 130 are further provided.
40, data memory 130 and auxiliary data memory 140
And a comparator 172 for detecting a mismatch between Further, the auxiliary address array 120 and the auxiliary data memory 1
A mode holding circuit 171 for holding a mode for controlling the operation of 40 is further included.

The instruction register 151 is provided in the processor 200
And the instruction code input from the signal line 203 is retained. The address register 152 holds an access address input from the processor 200 via the signal line 201. The store data register 153 stores the processor 20
From 0, the store data input by the signal line 202 is held. The store data register 153 is used at the time of a store instruction, and is not used at the time of a load instruction.

When a cache miss for a load instruction occurs in the cache memory 100, the cache memory 100 instructs the main memory 300 to read the fill block data in order to fill the corresponding block data. The fill data buffer 154 transfers the fill block data from the main storage device 300 to the signal line 30.
Receive via 2 and hold. The fill data buffer 154 arranges the writing to the data memory 130 such that the order is as requested. Specifically, at the same time as the block data from the main storage device 300, a tag assigned to each block and a position in the block are input from the main storage device 300 via a signal line 301, and according to these tags and positions, Fill data buffer 15
4 is determined. For example, if the number of requests that can be requested to the main storage device 300 is 2, the tag is either “0” or “1”, and data of 128 bytes per block is stored in the cache memory 100 in units of 8 bytes. , The position becomes any value from “0” to “15”.

When the address by the store instruction does not exist in the cache memory, the fill operation is not performed. Hereinafter, the cache miss indicates the cache miss by the load instruction. In general, a load instruction may be a cacheable load instruction that holds target data in a cache memory or a load instruction that does not, but hereinafter, the load instruction will be described as a cacheable load instruction. .

The miss processing circuit 155 performs a fill operation in the event of a cache miss. The miss processing circuit 155
The block address during the fill operation is held internally, and the corresponding block address is output to the selector 157 based on the tag transferred from the main storage device 300 via the signal line 301. Further, the miss processing circuit 155 causes the data input from the signal line 302 to be stored in the fill data buffer 154 according to the tag and the position input from the signal line 301. Further, a miss processing circuit 155
Controls updating of the address array 110 at the time of a mishit via the signal line 193.

The decoder 156 detects a case where the instruction held in the instruction register 151 is a store instruction and a cache hit or a cache fill, and outputs an update signal to the data memory 130.

The selector 157 selects the address held in the address register 152 at the time of storing, and selects the address from the miss processing circuit 155 at the time of filling due to a cache miss, and outputs the selected address to the signal line 191.

The selectors 159 and 158 select either the fill data from the fill data buffer 154 or the store data from the store data register 153 and input them to the data memory 130 and the auxiliary data memory 140, respectively.

The mode holding circuit 171 holds a mode to be described later, and stores the auxiliary address array 120 and the comparator 172.
Outputs the current mode to. The comparator 172 stores the data from the data memory 130 and the auxiliary data memory 14.
The data is compared with data from 0, and whether or not they match is output to the processor 200 via a signal line 205. When the mode holding circuit 171 indicates a predetermined mode,
The comparator 172 does not output a mismatch signal.

The data read from the data memory 130 is held in the load data register 173 and output to the processor 200 via the signal line 204. The hit / miss judgment by the comparator 161 is output to the processor 200 via the signal line 206. The interrupt detected in the auxiliary address array 120 is output to the processor 200 via the signal line 207.

The mode held by the mode holding circuit 171 is of two types. One is a store mode and the other is a dynamic mode. When the store mode is active, the auxiliary data memory 1 is used for both a fill due to a cache miss and a write due to a store instruction.
Update to 40. On the other hand, if the store mode is not active, the auxiliary data
To the auxiliary data memory 140 at the time of writing by the store instruction. Further, when the dynamic mode is active, the auxiliary address array 12 is dynamically generated every time a cache miss is caused.
Update 0. On the other hand, when the dynamic mode is not active, the auxiliary address array 120 is not updated even if there is a fill due to a cache miss, and the operation continues with the initial setting.

The store mode and the dynamic mode operate independently of each other. The former controls the update of the auxiliary data memory 140, and the latter controls the update of the auxiliary address array 120. When the store mode is activated, the update to the data memory 130 is reflected in the auxiliary data memory 140.
Can detect an error. On the other hand, when the store mode is not active, since the auxiliary data memory 140 is not always in the latest state, even if a mismatch is detected by the comparator 172, this does not necessarily mean an error. Therefore, in this case, the comparator 1
72 does not output a mismatch. The store mode is provided so that the store instruction can be separated from other instructions by inactivating the store mode and collecting the contents of the auxiliary data memory 140. That is, the update of the auxiliary data memory 140 is made the same as that of the data memory 130 by activating the store mode.
This is because the difference between the error and the result of only the error is analyzed to determine whether the error is caused by a cache fill or a store instruction. The cause of the error is that an unintended store instruction is generated due to a logical mistake, the address to be stored is corrupted, a cache fill sequence has a logical miss, It is possible that the contents of the data memory are garbled due to the influence.

When the dynamic mode is activated, the auxiliary address array 120 is updated at the same time as the address array 110 is updated at the time of a fill due to a cache miss, so that the address just updated can be appropriately checked. On the other hand, if the dynamic mode is not activated, the contents of the auxiliary address array 120 are left at the initial settings, so that the desired address can be checked mainly.

The setting of the auxiliary address array 120 and the mode holding circuit 171 is performed by the diagnostic apparatus 400 via signal lines 401 and 403, respectively. Also, when the contents of the auxiliary address array 120, the auxiliary data memory 140, and the mode holding circuit 171 are collected in the diagnostic device 400, the signal lines 401 to 403 are used, respectively.

Referring to FIG. 3, the auxiliary address array 120 according to the first embodiment of the present invention
It has a set of address registers 122 and a comparator 123. The number of sets may be arbitrarily set according to the requirements of the system. The address register 122 holds an address corresponding to a block (line) of the address array 110. The auxiliary address array 120 includes the address array 1
Since the number of entries is smaller than 10, not all entries in the address array 110 can be held. When the above-described dynamic mode is used, when a new fill occurs due to a cache miss, old entries are deleted sequentially. As such a control method, a method is conceivable in which address registers to be registered are sequentially selected in a round robin manner. For example, first register in the address # 0 register, and then register address # 1
Register in the register, then register in the address # 2 register, then register in the address # 3 register, then register in the address # 0 register, and so on. In order to realize this, a counter indicating the entry to be registered may be prepared.

Each of the address registers 122 includes a valid bit indicating whether the address register is valid or not. The one indicating "valid" is to be compared in the corresponding comparator 123. The comparison result of each comparator 123 is compiled in the encoder 124, and “00”, “01”,
The number of the entry that matches either “10” or “11” (hereinafter referred to as local address) is shown. This local address is output to the auxiliary data memory 140 via the signal line 194 together with the lower part of the address.

The diagnostic device 400 can set the initial value of the address register 122 by means such as a scan path. If the dynamic mode is not activated, the initial value can be maintained.

The decoder 125 instructs the auxiliary data memory 140 via a signal line 195 to perform a read or write operation. That is, if the instruction by the signal line 192 is a load instruction and a match is detected by any of the comparators 123, the auxiliary data memory 140 is instructed to read data corresponding to the local address. In the case of a cache miss, in the dynamic mode, the auxiliary data memory 140 is instructed to write by the fill operation. Further, if the instruction by the signal line 192 is a store instruction and any one of the comparators 123 detects a match, if the store mode and the dynamic mode are used, the auxiliary data memory 140 is instructed to write.

The monitoring target register 121 includes an expected number of times 1211, an instruction code 1212, and an address 1213.
And hold. The monitoring target register 121 is set by a signal line 401. The comparator 126 detects a match between the instruction code 1212 and the instruction code on the signal line 192. The comparator 127 is connected to the address 1213 and the signal line 191.
Detects a match with the address of By these comparators 126 and 127, the occurrence of an event can be detected by distinguishing the store or load for a desired address.
When both the comparators 126 and 127 detect a match, the AND circuit 128 increments the counter 1201 by “1” by the incrementer 1202. Comparators 126 and 127
And the AND circuit 128 are collectively referred to as a coincidence detector. When detecting that the number of times indicated by the counter 1202 matches the expected number of times 1211, the number-of-times comparator 129
07, an interrupt signal is output. Thus, an interrupt can be generated by specifying the number of times a predetermined instruction has been executed for a predetermined address, and the state of the cache memory can be sampled.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIGS. 2 to 6, first, when the instruction is a load instruction (step S501), if a match is detected in any of the comparators 123 in the auxiliary address array 120 (step S502), the monitoring target register is checked. It is checked whether or not an interrupt has occurred due to 121 (step S503).
This interrupt check is performed by the comparator 1 as shown in FIG.
When a match between the instruction and the address is detected by the AND circuit 128 in steps 26 and 127 (step S6).
01), the counter 12 is incremented by the incrementer 1202.
01 is incremented by "1" (step S602). The value of the counter 1201 is the expected number of times 1 of the register 121 to be monitored.
If the number matches 211 (step S603), the number comparator 129 notifies the processor 200 via the signal line 207 of the occurrence of the interrupt (step S604).

In parallel with the interrupt check, data is read from the auxiliary data memory 140 in accordance with the instructions on the signal lines 194 and 195 from the auxiliary address array 120 (step S504). If the mode held in the mode holding circuit 171 is the store mode, the data read from the auxiliary data memory 140 and the data read from the data memory 130 are compared with each other by the comparator 172.
Are compared (step S506). And the comparator 17
2 is output to the processor 200 via a signal line 205 as to whether or not the data coincides with each other.
Is output to the processor 200 via the signal line 206 as to whether or not there is a cache hit. As shown in FIG. 6, when the data read from the auxiliary data memory 140 does not match the data read from the data memory 130 (step S701) and there is a cache hit (step S702), the processor 200
An interrupt processing circuit (not shown) generates an interrupt signal notifying the occurrence of a failure (step S703).

On the other hand, if the instruction is a store instruction (step S511), the comparator 12 in the auxiliary address array 120
3 when a match is detected (step S51).
2) The occurrence of an interrupt by the monitoring target register 121 is checked (step S513). This interrupt check is the same as that of FIG. 5 described above. If the mode held by the mode holding circuit 171 is the store mode (step S515) and the output of the comparator 161 indicates a cache hit (step S516),
The storage data is written to the auxiliary data memory 140 (step S517).

In the case of cache fill (step S521), if a match is detected in any of the comparators 123 in the auxiliary address array 120 (step S522), the occurrence of the interrupt in FIG. Check (step S523). If no match is detected in step S522, if the mode held in the mode holding circuit 171 is the dynamic mode (step S5).
31), and register the cache-filled address in the auxiliary address array 120 (step S53).
2). If it is determined in step S522 that the addresses match, or if it is determined in step S531 that the mode is the dynamic mode, the cache fill data is written to the auxiliary data memory 140 (step S517).

As described above, according to the first embodiment of the present invention, by newly providing the auxiliary address array 120, the auxiliary data memory 140, and the comparator 172, the error generated in the data memory 130 can be increased. It can be detected by coverage. By setting the store mode held in the mode holding circuit 171 to an inactive state, the auxiliary data memory 140 according to the store instruction is set.
Data can be collected by separating writing into the data. Further, by setting the dynamic mode held in the mode holding circuit 171 to the inactive state, the update of the auxiliary address array 120 can be suppressed, and data can be collected for the address specified by the initial setting. In order to collect these data, an interrupt generation condition is set in the monitoring target register 121, and an interrupt can be generated when a predetermined instruction 1212 is executed a predetermined number of times 1211 for a predetermined address 1213.

Next, a description will be given of a second embodiment of the cache memory according to the present invention.

Referring to FIG. 7, the auxiliary address array 120 according to the second embodiment has an instruction register 151
The signal line 199 (not shown in FIG. 2) is input to the comparator 127, and the address 12
The third embodiment is the same as the first embodiment described with reference to FIG. 3 except that it is compared with a monitoring register number 1214 provided in place of 13. In the second embodiment shown in FIG. 7, an interrupt can be generated for a load instruction or a store instruction generated for the register specified by the monitoring register number 1214. That is, as in the first embodiment shown in FIG. 3, when both comparators 126 and 127 detect a match, the AND circuit 128 sets the incrementer 1202
Increments the counter 1201 by “1”. When detecting that the number indicated by the counter 1202 matches the expected number of times 1211, the number comparator 129 outputs an interrupt signal to the signal line 207. Thus, an interrupt can be generated by specifying the number of times a predetermined instruction has been executed for a predetermined register number, and the state of the cache memory can be collected.

As described above, according to the second embodiment of the present invention, in order to collect the above-described data, the interrupt generation condition is set in the monitoring target register 121, and the predetermined instruction for the predetermined register number 1214 is set. 1212 is the predetermined number of times 12
An interrupt can be generated when executed for 11 minutes.

[0050]

As apparent from the above description, according to the present invention, a physical failure of a data array in a cache memory can be detected at a high coverage. Further, by setting various modes, flexible data collection can be performed. Further, when the predetermined instruction is executed a predetermined number of times, an interrupt can be generated to collect data.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a computer system to which a cache memory of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a cache memory according to an embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of an auxiliary address array in the cache memory according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating an operation of the embodiment of the cache memory of the present invention.

FIG. 5 is a diagram showing an interrupt determination procedure in the embodiment of the cache memory of the present invention.

FIG. 6 is a diagram showing a hit determination procedure in the embodiment of the cache memory of the present invention.

FIG. 7 is a block diagram showing a configuration of an auxiliary address array in a cache memory according to a second embodiment of the present invention;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 cache memory 110 address array 120 auxiliary address array 121 monitored register 122 address register 123, 126, 127 comparator 124 encoder 125 decoder 128 AND circuit 129 count comparator 130 data memory 140 auxiliary data memory 151 instruction register 152 address register 153 Store data register 154 Fill buffer 155 Miss processing circuit 156 Decoder 157 to 159 Selector 161, 172 Comparator 171 Mode holding circuit 173 Load data register 200 Processor 300 Main storage device 400 Diagnostic device

Claims (13)

[Claims] An auxiliary data memory for storing at least a part of the content stored in a cache memory is provided therein. If the content of the auxiliary data memory does not match the cache memory, a failure occurs in the cache memory. Cache memory that detects that 2. A cache memory having an address array for storing addresses and a data memory for storing data corresponding to the addresses stored in the address array, wherein at least one copy of the addresses stored in the address array is copied. An auxiliary address array stored in each entry; an auxiliary data memory storing data stored in the data memory corresponding to an address stored in each entry of the auxiliary address array; and an auxiliary data memory stored in the auxiliary data memory. A comparator for detecting whether or not the contents of the data memory coincide with the contents of the data memory. 3. A mode holding circuit for holding a store mode, wherein when the store mode is active, writing to the data memory by cache fill and store instructions is reflected in the auxiliary data memory. 3. The cache memory according to claim 2, wherein when the store mode is inactive, the data written to the data memory by the cache fill is reflected in the auxiliary data memory, and the data written by the store instruction is not reflected. 4. The apparatus according to claim 3, wherein the comparator outputs a valid value when the store mode is active, and does not output a valid value when the store mode is not active. Cache memory. 5. The mode holding circuit further holds a dynamic mode, and when the address array is updated by a cache fill, when the dynamic mode is active, the same update content is reflected on the auxiliary address array. And
4. The cache memory according to claim 3, wherein when the dynamic mode is not active, it is not reflected in the auxiliary address array. 6. The auxiliary address array includes a monitored register for setting an interrupt occurrence condition, and a match detector for detecting whether or not a condition set in the monitored register is met. 3. The cache memory according to claim 2, wherein 7. The cache memory according to claim 6, wherein said monitoring target register holds an instruction code and an access destination address as an interrupt occurrence condition. 8. The address array includes a counter that counts in response to a condition match in the match detector, and a number comparator that uses the output of the counter as one input and detects a match with another input. The monitoring target register further holds an expected value of the number of detections in the coincidence detector, and the number comparator interrupts when the value of the counter matches the expected value held in the monitoring target register. 8. The cache memory according to claim 7, wherein the occurrence of the error is notified. 9. The cache memory according to claim 6, wherein said monitoring target register holds an instruction code and a register number as an interrupt occurrence condition. 10. The address array includes: a counter that counts in response to a condition match in the match detector;
A counter for detecting a match with another input using the output of the counter as one input, wherein the monitoring target register further holds an expected value of the number of detections in the match detector; 10. The cache memory according to claim 9, wherein when the value of said counter matches the expected value held in said monitoring target register, an interrupt is notified. 11. An address array for storing an address, a data memory for storing data corresponding to the address stored in the address array, and a copy of at least one of the addresses stored in the address array for each entry. , An auxiliary data memory for storing data stored in the data memory corresponding to an address stored in each entry of the auxiliary address array, and a mode holding circuit for holding a store mode. A failure detection method in the cache memory having the storage mode, wherein when the store mode is active, any of a cache fill and a store instruction in writing to the data memory is reflected in the auxiliary data memory, and the store mode is active. If not, the data memo When writing data to the auxiliary data memory, the data stored in the auxiliary data memory is controlled so that the data stored in the auxiliary data memory is not reflected. A failure detection method for a cache memory, which outputs whether or not the contents match the contents of the data memory, and if it is determined that the contents match, if a cache hit occurs, an interruption signal indicating occurrence of a failure is generated. 12. The mode holding circuit further holds a dynamic mode, and when the address array is updated by a cache fill, when the dynamic mode is active, the same update content is reflected on the auxiliary address array. And
12. The method according to claim 11, wherein when the dynamic mode is not active, the failure is not reflected in the auxiliary address array. 13. The method of detecting a failure in the cache memory, further comprising: generating an interrupt when a predetermined condition is satisfied a predetermined number of times; and generating an interrupt when the interrupt occurs, the address array, the data memory, the auxiliary address array, 12. The method according to claim 11, wherein the contents of the auxiliary data memory are collected.
A failure detection method in the cache memory described in the above.