JP3239935B2 - Tightly-coupled multiprocessor system control method, tightly-coupled multiprocessor system, and recording medium therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tightly coupled multiprocessor system in which a plurality of processors are respectively connected to a bus via a processor controller, and each processor shares a main storage device.

[0002]

2. Description of the Related Art A system in which a plurality of processors are connected to a bus via a processor controller and share a main storage device (main memory) is called a tightly coupled multiprocessor system. In this tightly-coupled multiprocessor system, when each processor is provided with a cache memory, it is necessary to process cache data held by each processor so as not to cause inconsistency, and this is called cache coherence processing.

[0003] Cache coherence processing is realized by monitoring the coherent transactions by all processors connected to the bus when a transaction (coherent transaction) requiring the processing is sent out onto the bus. At this time, in the processor holding the data of the same address as that of the coherent transaction sent to the bus in the cache memory, the data is written to the main memory, invalidated, or the state value of the cache data (the state value of the cache data) Is changed.

The state of cache data is usually Inval
id, Shared, Clean Exclusive, Dirty Exclusive 4
There are types, and the following states (1) to (4) are shown.

(1) Invalid: The cache line has no valid data.

(2) Shared: The cache line has valid data, and the same data exists in the cache memory of another processor.

(3) Clean Exclusive: The cache line has valid data, and the same data does not exist in the cache of another processor. The same data exists in the main memory.

(4) Dirty Exclusive: Valid data is stored in the cache line, and the same data does not exist in the cache memory of another processor. Although different data exists in the main memory, the data in the cache line is the latest.

When a transaction for data stored in a cache memory of another processor in a Dirty Exclusive state is sent out onto the bus, the issuing processor is not the main memory data but the cache memory of the other processor. Output from Dirty Exclu
The data in the sive state must be read.

In a tightly coupled multiprocessor system, in order to monitor a coherent transaction sent to a bus, each processor must take in a coherent transaction via a processor controller. Therefore, much time is required for coherence processing.

Therefore, in order to reduce the time required for the coherence processing, the processor controller is usually provided with a high-speed memory for storing tag information and status values of data held in the cache memory. This high-speed memory is called a copy tag memory. Upon receiving the coherent transaction transmitted on the bus, the processor controller searches the contents of the copy tag memory, and if valid data exists in the cache memory and it is necessary to rewrite the state of the cache data, the processor controller notifies the processor. Send transaction to However, if it is detected that valid data does not exist, or if the state value does not need to be rewritten even if valid data exists, the received coherent transaction is not transmitted to the processor. By performing such processing, the time of the coherence processing is reduced.

[0012]

However, in the above-described tightly-coupled multiprocessor system, when the tag information read from the copy tag memory is incorrect, the latest data is stored in the cache memory of the processor. Nevertheless, the data may be determined to be invalid by the tag information, and the coherent transaction to be transmitted to the processor may not be transmitted to the processor. For this reason, a parity bit is usually provided in the copy tag memory, and a parity check is performed to determine whether or not the copy tag information is correct.

When a parity error is detected, it is determined that the copy tag memory is faulty, the copy tag memory is turned off (the copy tag memory is not used), and the system is operated in the same manner as a system without a copy tag memory. Is operating the system normally.

However, when the copy tag memory is not used, all coherent transactions sent on the bus must be fetched into the processor, which greatly reduces the processing performance of the system. Therefore, it is desirable to realize a control method that does not turn off the copy tag memory in the case of a minor failure even when a failure occurs in the copy tag memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and when a failure occurs in a specific entry of the copy tag memory,
It is an object of the present invention to provide a tightly-coupled multiprocessor system in which the entire copy tag memory is prevented from being turned off by turning off only the failure entry, and a large reduction in processing performance of the system is avoided, and a control method thereof. .

[0016]

In order to achieve the above object, a method for controlling a tightly coupled multiprocessor system according to the present invention comprises: a plurality of processors each having a cache memory connected to a bus via a processor controller;
A method of controlling a tightly-coupled multiprocessor system including a copy tag memory in which tag information of the cache memory is stored in the processor controller, wherein the processor controller stores the tag information read from the copy tag memory. When a parity error is detected, the address of the tag information is held in a register, and when a parity error is detected again in the tag information read from the copy tag memory, the address of the tag information is held in the register. And when the two addresses do not match, the use of the copy tag memory is prohibited, and when the two addresses match, only the use of the copy tag memory is prohibited. .

A tightly-coupled multiprocessor comprising a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. A method of controlling a system, wherein when the processor controller detects a parity error in the tag information read from the copy tag memory, the processor controller holds an address of the tag information in a register, and stores a predetermined plurality of registers. To
In this method, the use of the copy tag memory is prohibited when the address of the tag information at which the parity error is detected is held. On the other hand, a tightly-coupled multiprocessor system according to the present invention provides a copy tag memory in which a plurality of processors each having a cache memory are connected to a bus via a processor controller, and the processor controller stores tag information of the cache memory. A tightly coupled multiprocessor system comprising: an error address storage register that holds an address of the tag information when the processor controller detects a parity error in the tag information read from the copy tag memory. When a parity error is detected again in the tag information read from the copy tag memory, an address comparison circuit that compares the address of the tag information with the address held in the error address storage register; A copy tag search result judging unit which prohibits use of the copy tag memory if not, and prohibits use of only data at the address of the copy tag memory when the two addresses match. is there.

A tightly-coupled multiprocessor having a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. A processor, wherein when the processor controller detects a parity error in the tag information read from the copy tag memory, a plurality of error address storage registers for holding an address of the tag information; A copy tag search result judging unit for prohibiting use of the copy tag memory when the address of the tag information for which the parity error is detected is held in the error address storage register.

Further, a recording medium according to the present invention is a copy tag memory in which a plurality of processors each having a cache memory are connected to a bus via a processor controller, and the processor controller stores tag information of the cache memory. A recording medium in which a control method of a tightly-coupled multiprocessor system is provided, wherein the processor controller detects a parity error in the tag information read from the copy tag memory, When a parity error is detected again in the tag information read from the copy tag memory, the address of the tag information is compared with the address held in the register, and the two addresses match. If not, the copy tag To prohibit the use of memory, if the two addresses match is obtained by recording a program to prohibit only the use of the address of said copy tag memory.

A tightly-coupled multiprocessor comprising a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. A recording medium in which a system control method is recorded, wherein the processor controller, when a parity error is detected in each of the tag information read from the copy tag memory, causes an address of the tag information to be held in a register, A program for prohibiting the use of the copy tag memory when the address of the tag information for which the parity error is detected is stored in a plurality of predetermined registers.

In the tightly-coupled multiprocessor system configured as described above, when each processor controller detects a parity error in the tag information read from the copy tag memory, it holds the address of the tag information in a register, When a parity error is detected again in the tag information read from the copy tag memory, the address of the tag information is compared with the address held in the register,
If the two addresses do not match, use of the copy tag memory is prohibited, and if the two addresses match, use of only the copy tag memory is prohibited.
In the case of a minor failure such as a single failure of a fixed entry, a copy tag memory can be used.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of a tightly coupled multiprocessor system. FIG. 1 shows a configuration of a tightly coupled multiprocessor system including two nodes each having a processor. The number of nodes in a tightly coupled multiprocessor system need not be limited to two, but may have more nodes.

In FIG. 1, a first node 100 includes a first processor 102 having a first cache memory 101 and a first processor 102 having a first copy tag memory 104 and a first recording medium 105. Processor controller 1
03.

The second node 110 has a second processor 107 having a second cache memory 106.
And a second processor controller 108 including a second copy tag memory 109 and a second recording medium 112.

The first processor 102 is connected to a system bus 111 via a first processor controller 103, and the second processor 107 is connected to the system bus 111 via a second processor controller 108.

The first copy tag memory 104 stores the tag information of the first cache memory 101 and the status value of the cache data.
Stores the tag information of the second cache memory 106 and the status value of the cache data.

The first processor controller 103 reads the program recorded on the first recording medium 105 by a processing device (not shown), and the processing device provided in the first processor controller 103 records the program on the first recording medium 105. The processing described later is executed in accordance with the executed program. Similarly, the second processor controller 108 reads the program recorded on the second recording medium 112 by a processing device (not shown), and the processing device provided in the second processor controller 108 is recorded on the second recording medium 112. The processing described below is executed according to the program.

The first recording medium 105 and the second recording medium 112 may be a magnetic disk, a semiconductor memory, or another recording medium.

In such a configuration, for example, when a coherent transaction is sent from the first node 100 to the system bus 111, the second node 110 sends the coherent transaction sent to the system bus 111 to the second processor controller. Receive at 108. The second processor controller 108 searches the contents of the second copy tag memory 109, and transmits the coherent transaction to the second processor 107 only when the received coherent transaction has performed an Exclusive Hit.

Next, the operations of the first processor controller and the second processor controller will be described in detail with reference to FIG. In the following, the operation of the second processor controller 108 will be described as an example.
Operate in the same manner. Also, in the case of a tightly coupled multiprocessor system including more nodes, the processor controllers of the respective nodes operate similarly. In addition, the second described below
The operation of each component of the processor controller 108 is controlled by a processing device (not shown).

FIG. 2 is a diagram showing a configuration of a tightly coupled multiprocessor system of the present invention, and is a block diagram showing an embodiment of a processor controller.

In FIG. 2, when a coherent transaction is sent out on the system bus 111, the processing device receives the coherent transaction on the system bus 111 and stores the address in the first address storage register 203.

Next, the first address storage register 203
The address stored in the second address storage register 2
04. Then, the tag information is read from the second copy tag memory 109 based on the address stored in the second address storage register 204, the read tag information is stored in the data storage register 205, and the parity check is performed by the parity check circuit 206. Do. Here, when a parity error is detected, the parity check circuit 206 causes the parity error flag 20 to be detected.
7 is set.

The processing device also copies the address of the tag information read from the second copy tag memory 109 from the first address storage register 203 to the error address storage register 209. At this time, the second copy tag memory 10 is stored in the error address storage register 209.
Each time the tag information is read out from the register 9, the value of the first address storage register 203 is written, and the address written when the parity error flag 207 is set by the parity check circuit 206 is held. Also, a valid bit 210 indicating valid data is set in the held address.

In this state, if a parity error occurs again in the tag information read from the second copy tag memory 109, the processing device switches to the address comparison circuit 211.
Then, the address in the first address storage register 203 and the address in the error address storage register 209 are compared.

Here, the first address storage register 20
If the address in No. 3 does not match the address in the error address storage register 209, the address comparison circuit 211 sets a copy tag off bit 212 for turning off the second copy tag memory 109.
Further, the copy tag search result determination unit 208 regards the received coherent transaction as an Exclusive Hit and transmits it to the second processor 107 regardless of the tag information read from the second copy tag memory 109 thereafter. On the other hand, if the address in the first address storage register 203 matches the address in the error address storage register 209, the second copy tag memory 1
09, it is determined that the corresponding address (fixed entry) has a failure, only the coherent transaction received at that time is treated as an Exclusive Hit, and the use of the second copy tag memory 109 is continued. Therefore, in the case of a minor failure such as a single failure of a fixed entry, the copy tag memory is continuously used, so that it is possible to avoid a significant decrease in processing performance due to the copy tag memory being turned off.

In the above description, the processor controller has one error address storage register 209, treats only the coherent transaction for one failed entry as Exclusive Hit, and continues to use the second copy tag memory 109. As described above, a plurality of error address storage registers 209 may be provided to hold a plurality of addresses of tag information in which a parity error has occurred. Then, the copy tag search result determining unit 208 turns off the copy tag memory when a predetermined plurality of parity errors occur. Even with such a configuration, the copy tag memory can be used until a predetermined number of single failures of the fixed entry occur, so that a significant decrease in processing performance due to the inability to use the copy tag memory can be avoided. . In such a configuration, the number of failure entries set for turning off the copy tag memory can be easily increased.

[0039]

Since the present invention is configured as described above, the following effects can be obtained.

When the processor controller detects a parity error in the tag information read from the copy tag memory, the processor controller holds the address of the tag information in the register and detects the parity error again in the tag information read from the copy tag memory. The address of the tag information is compared with the address held in the register,
If the two addresses do not match, use of the copy tag memory is prohibited, and if the two addresses match, only use of that address in the copy tag memory is prohibited. In the event of a failure, the copy tag memory can be used, so that a significant reduction in processing performance due to the inability to use the copy tag memory can be avoided.

When the processor controller detects a parity error in the tag information read from the copy tag memory, the processor controller holds the address of the tag information in a register, and stores the parity error in a predetermined plurality of registers. By prohibiting the use of the copy tag memory when the address of the detected tag information is held,
Since the copy tag memory can be used until a predetermined plurality of fixed entry failures occur, it is possible to avoid a significant decrease in processing performance due to the inability to use the copy tag memory. In such a configuration, the number of failure entries set for turning off the copy tag memory can be easily increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a tightly-coupled multiprocessor system.

FIG. 2 is a diagram showing a configuration of a tightly coupled multiprocessor system of the present invention, and is a block diagram showing an embodiment of a processor controller.

[Explanation of symbols]

 Reference Signs List 100 first node 101 first cache memory 102 first processor 103 first processor controller 104 first copy tag memory 105 first recording medium 106 second cache memory 107 second processor 108 second Processor controller 109 Second copy tag memory 110 Second node 111 System bus 112 Second recording medium 203 First address storage register 204 Second address storage register 205 Data storage register 206 Parity check circuit 207 Parity error flag 208 Copy tag search result determination unit 209 Error address storage register 210 Valid bit 211 Address comparison circuit 212 Copy tag off bit

Claims (6)

(57) [Claims] 1. A tightly-coupled multiprocessor having a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. A method of controlling a system, wherein, when a parity error is detected in the tag information read from the copy tag memory, the processor controller holds an address of the tag information in a register, and reads the address from the copy tag memory. If a parity error is detected again in the tag information, the address of the tag information is compared with the address held in the register. If the two addresses do not match, use of the copy tag memory is prohibited. The two addresses matched A method of controlling a tightly coupled multiprocessor system in which only use of said address in said copy tag memory is prohibited. 2. A tightly-coupled multiprocessor comprising a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. A method of controlling a system, wherein, when a parity error is detected in each of the tag information read from the copy tag memory, the processor controller holds an address of the tag information in a register; And a method of controlling a tightly coupled multiprocessor system in which use of the copy tag memory is prohibited when an address of tag information at which a parity error is detected is held. 3. A tightly-coupled multiprocessor having a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. An error address storage register that holds an address of the tag information when the processor controller detects a parity error in the tag information read from the copy tag memory; An address comparison circuit for comparing the address of the tag information with the address held in the error address storage register when a parity error is detected again in the tag information, and a copy tag memo when two addresses do not match. And a copy tag search result determination unit for prohibiting the use of the data in the copy tag memory and prohibiting only the use of the data of the address in the copy tag memory when the two addresses match. 4. A tightly-coupled multiprocessor having a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. A system, wherein the processor controller, when detecting a parity error in the tag information read from the copy tag memory, respectively, a plurality of error address storage registers holding an address of the tag information; A copy tag search result judging unit for prohibiting use of the copy tag memory when the address of the tag information at which the parity error is detected is held in the error address storage register. 5. A tightly-coupled multiprocessor having a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. A storage medium on which a system control method is recorded, wherein the processor controller causes a register to hold an address of the tag information when a parity error is detected in the tag information read from the copy tag memory. When a parity error is detected again in the tag information read from the copy tag memory, the address of the tag information is compared with the address held in the register. Prohibit the use of A storage medium storing a program for prohibiting only use of the address in the copy tag memory when the two addresses match. 6. A tightly-coupled multiprocessor having a plurality of processors each having a cache memory connected to a bus via a processor controller, and each processor controller having a copy tag memory in which tag information of the cache memory is stored. A storage medium on which a system control method is recorded, wherein the processor controller causes a register to hold an address of the tag information when a parity error is detected in the tag information read from the copy tag memory. A recording medium in which a program for prohibiting the use of the copy tag memory is recorded at a point in time when an address of tag information for which a parity error is detected is held in a plurality of predetermined registers.