JPH0217550A - Trouble processing system for multiprocessor system - Google Patents

Abstract

PURPOSE:To avoid system halt by constituting the system so that contents of a cache memory of a memory controller where trouble occurs are returned to a main storage device. CONSTITUTION:When trouble occurs in a memory controller 3, this occurrence is reported to a trouble processing device 5. After gathering trouble information of the memory controller 3 in response to this report, the trouble processing device 5 temporarily stops the system to read out contents of a data array 31-a and an address array 31-b of a cache memory 31 through a bus 103 when confirming it by said trouble information that contents of the cache memory 31 are reliable. When it is judged by effective bits and rewrite bits read out from the cache memory that read data is effective and rewritten data, the trouble processing device 5 requests the write of this data to a main storage device 1.

Description

TECHNICAL FIELD The present invention relates to a failure handling method for a multiprocessor system, and more particularly to a failure handling method for a memory control device having a store-in type cache memory.

Traditionally, when a memory control device uses a store-in type cache memory in an information processing device that causes problems in a multiprocessor system, when a failure occurs in the memory control device, the cache memory There was no way to write the contents of memory back to main memory.

Here, the store-in method requires the contents of the main memory, and if there is no free space in the cache memory, the contents of the cache memory are returned to the main memory to create a free space, and the free space is filled with the new content. This is to write the contents of the main memory, and since reading and writing are normally performed using only the contents of the cache memory, the contents of the cache memory and the contents of the main memory are different.

In such conventional information processing devices, even if a failure occurs in the memory control unit, there is no way to write the contents of the cache memory back to the main memory, so it is possible that the failure will occur in areas other than the cache memory section of the memory control unit. However, even if the contents of the cache memory are guaranteed, it is not possible to return the contents to the main memory and disconnect the memory control device to continue the system, resulting in a system stoppage.

Purpose of the Invention The present invention has been made to eliminate the above-mentioned drawbacks of the conventional system, and it is possible to restore the contents of the cache memory of a faulty memory control unit to the main storage, thereby preventing system stoppage. The purpose is to provide a failure handling method that can avoid this problem.

A failure handling method according to the present invention includes first and second cache memories, and a valid bit indicating whether data stored in each of the first and second cache memories is valid.
first and second memory control devices each having first and second storage means for storing a rewrite bit indicating whether or not the data has been rewritten; first and second main storage devices; A fault handling method for a multiprocessor system including first and second fault processing devices, wherein when a fault is detected in the first memory control device, a fault is stored in the first cache memory. Extracting means for extracting data in which the valid bit stored in the first storage means indicates validity of the data and the rewriting focus indicates rewriting of the data; and the data extracted by the extracting means. reading means for reading out the data from the first cache memory, and the data read by the reading means is sent to the first main cache memory via the second fault processing device and the second memory control device. It is characterized by writing to a storage device.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a multiprocessor system according to an embodiment of the present invention includes a main storage device 1.2, a memory control device 3.4 having a cache memory 31.41, a fault processing device 5.6, and an arithmetic processing unit. 7-i (i=1.・
...), 8-j (j-1, ...).

The main storage device 1.2 is normally connected to the memory control devices 3 and 4 via buses 101 and 201, respectively, but if the memory control devices 3 and 4 become unusable due to a failure or the like, for example, the memory control device 1.2 If device 3 becomes unavailable, main memory 1.2 is connected to memory controller 4 by bus 102.201; if memory controller 4 becomes unavailable, main memory 1.2 is connected to bus 101. , 202 to the memory control device 3. Furthermore, the memory control devices 3.4 are connected to each other via a bus 300.

The cache memories 3141 of the memory control devices 3 and 4 are connected to the arithmetic processing devices 7-i and 8-j, input/output processing devices (not shown),
Alternatively, it is the data buffer for the above fault access of the fault processing device 5.6, and a store-in method is adopted.

Further, the memory control devices 3 and 4 are connected to the fault handling device 5.6 via buses 103.203, respectively, and
It is connected to arithmetic processing units 7-i and 8-j via i and 204-j, respectively.

The failure processing device 5.6 performs failure information collection processing and failure relief processing for each device that constitutes the system.

FIG. 2 is a diagram for explaining reading of data from the cache memory 31 by the failure processing device 5 of FIG. 1. In FIG. The read address register 31-1 and the read data register 31-2 each form a chain in units of one flip-flop. Therefore, writing and reading of data from the fault processing device 5 to and from the read address register 31-1 and the read data register 31-2 is possible through scan-in and scan-out operations.

The cache memory 41 also has the same configuration as the cache memory 31, and the failure processing device 6 can write and read data to and from the cache memory 41 through scan-in and scan-out operations in the same manner as described above.

FIG. 3 is a diagram showing the configuration of the cache memory 31 of FIG. 1. In the figure, cache memory 31 is composed of data array 31-a and address array 31-st. The data array 31-a stores data in units of n+1 bytes, and the address array 31-b contains memory addresses, valid bits indicating whether the data stored in the data array 31a is valid or invalid, and the data array 31-b. A rewrite bit indicating whether the data stored in 31-a has been rewritten is stored. Furthermore, entries 0 to m of data array 31-a and address array 31-b correspond to each other, respectively.

Note that the cache memory 41 is the same as the cache memory 31 mentioned above.
Similarly, it consists of a data array and an address array.

The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

The main storage device 1.2 is connected to the memory control devices 3 and 4 through paths 101 and 201, respectively, and when the arithmetic processing device 7-i reads or writes to the main storage device 1, the memory control device 3. The cache memory 31 of the memory controller 4 is used, and when the arithmetic processing unit 8-j reads from or writes to the main storage device 2, the cache memory 41 of the memory control device 4 is used.

At this time, if the cache memory 31.41 is not hit, data is read into the cache memory 31.41 from the main storage device 1.2 in certain units, but there must be free space in the cache memory 31.41. For example, prior to reading data from the main memory 1.2, the contents of a certain unit from the cache memory 31.41 are transferred to the main memory 1.2.
is written back to.

In this way, normal operation takes place, and the cache memory 31.41 is used as a data buffer for the main memory 1.2.

A case will be described below in which a failure occurs in the memory control device 3 during the normal operation as described above. However, at this time, it is assumed that the contents of the cache memory 31 are guaranteed.

When a failure occurs in the memory control device 3, the failure processing device 5
will be notified of the failure.

The fault processing device 5 collects fault information of the memory control device 3 in response to this notification, and when it is confirmed that the contents of the cache memory 31 can be guaranteed from the fault information, the system is temporarily stopped and the cache memory 31 is The contents of data array 31a and address array 31-b are read out via path 103.

That is, the fault processing device 5 performs a scan-in operation so that a desired address is set in the read address register 31-1 of the cache memory 31, and then applies one machine clock to read the desired address in the cache memory 31. Data is read from the address and set in the read data register 31-2.

The data set in the read data register 31-2 is read by the failure processing device 5 in a scan-out operation.

In this way, the address array 31 of the cache memory 31
- From the valid bit and rewritten bit read from b,
If the read data is valid and the data of the rewritten entry, the fault processing device 5 sends the memory address of the entry and the data of the entry in the data array 31-a to the fault processing device 6 via the path 301. A request is made to write these data to the main storage device 1.

At this time, the main storage device 1 is connected to the memory control device 4 via the path 102, and memory access is performed using the cache memory 41, and the memory address of the entry and the data in the data array 3ia are damaged. The data is written back to the main storage device 1 via the processing device 6 and the memory control device "J!14."

In this way, data in all entries in the cache memory 31 is written back to the main storage device 1. Thereafter, the operation of the system is restarted, and operation continues with the configuration of one memory control device 4 and two main storage devices 1 and 2.

Even when a failure occurs in the memory control device 4, data in all entries in the cache memory 41 is written to the main storage device 2 in the same way as the process when a failure occurs in the memory control device 3 described above. Return processing is performed.

In this way, when a failure occurs in the memory control device 3.4, the data stored in the cache memory 31.41 is successively retrieved, and the valid bit and rewrite bit corresponding to the data are used to ensure that the data is valid and cannot be rewritten. When a fault has occurred, the data is written to the main memory 1.2 via the fault handler 6.5 and the memory controller 4.3. The contents of the cache memory 31.41 of the memory control device 3.4 can be written back to the main storage device 1.2.
The contents can be guaranteed continuously. Therefore, the memory control device 3 or 4 in which the fault has occurred can be disconnected from the system and the operation of the system can be continued, and a system stoppage can be avoided.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the first and second memory control devices, the first and second main storage devices, and the first
and a second failure processing device, when a failure is detected in the first memory control device, the data stored in the first cache memory provided in the first memory control device is When the corresponding valid bit indicates that the data is valid and the rewrite bit indicates that the data has been rewritten, the data is read from the first cache memory and sent via the second fault handling device and the second memory control device. By writing to the first main storage device, the contents of the cache memory of the memory control device in which a failure has occurred can be returned to the main storage device, and system stoppage can be avoided. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining reading of data from the cache memory by the fault handling device of FIG. 1, and FIG.
It is a figure which shows the structure of the cache memory of a figure. Explanation of symbols of main parts 1.2...Main storage device 3.4...Memory control device 5.6...Fault processing device 7-1.8-1. ... Arithmetic processing unit 31.41.
... Cache memory 31-1 ... Read address register 31-2 ... Read data register 31-b ... Address array

Claims (1)

[Claims] (1) First and second cache memories, a valid bit that indicates whether the data stored in each of the first and second cache memories is valid, and a rewrite bit that indicates whether or not the data has been rewritten. first and second memory control devices each having first and second storage means for storing, first and second main storage devices, and first and second fault processing devices. A fault handling method for a multiprocessor system, wherein when a fault is detected in the first memory control device, the data stored in the first storage means out of the data stored in the first cache memory is Extracting means for extracting data in which a valid bit indicates the validity of the data and the rewriting bit indicates rewriting of the data; and a reading means for reading out the data extracted by the extracting means from the first cache memory. and the data read by the reading means is transmitted to the second
A failure handling method characterized in that writing is performed in the first main storage device via the failure handling device and the second memory control device.