JP2009116681A - Multiprocessor system, microprocessor, and failure handling method of microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To safely disconnect a faulty processor from a system by executing cache sweeping in handling a failure of a microprocessor from a sound processor in which no fault occurs. <P>SOLUTION: A multiprocessor system constituted of two or more microprocessors each of which has a write back cache includes: a routing circuit 20 for storing cache states of all the microprocessors; a means for reading tag information stored in the routing circuit 20; a means for specifying a real address space cached in a write-back cache 10 in at least any one of the microprocessors on the basis of the tag information; and a means for reading a specified real address space by other sound microprocessor in which no fault occurs. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multiprocessor system including a microprocessor having a write-back cache.

In recent years, due to advances in technology related to microprocessors, a large number of microprocessors that implement a complicated address translation mechanism, memory cache, and the like that have been adopted in mainframes have appeared.
In addition, a large-scale multiprocessor system has been built against the background of the multi-core microprocessor.

On the other hand, the firmware for controlling the microprocessor has been abstracted independently from the microprocessor body in order to be able to operate on a wider variety of chipsets.
A control program called BIOS is mounted on a memory, and a method of realizing processor initialization and failure processing by combining microprocessor instruction sets is generalized.

  For example, the Intel Itanium 2 processor executes program code called MCA (Machine Check Abort) handler in the event of a processor failure, and takes over the processing that was being executed by the processor and releases resources to handle the failure. Realized.

  This Itanium2 processor employs a write-back cache. In the write back method, the CPU writes only to the cache at the time of writing, and when it becomes necessary to rewrite the contents of the cache, the contents of the cache are written to the main memory before rewriting.

  In general, in a microprocessor having a write-back cache such as an Itanium 2 processor, a cache flush instruction is executed in a program code such as an MCA handler to clean the write-back cache, and then the processor is disconnected. Execute.

However, if a failure that leads to a processor stall occurs and the failure handler is stopped in an inoperable state, the dirty block remains in the processor cache, so the entire system must be reinitialized. There was a problem that the processor could not be disconnected.
In other words, even if a failure occurs in the microprocessor, the conventional technology is based on the premise that the control program executed on the microprocessor operates completely. Insufficient consideration was given to the occurrence of cache flushing.

  Here, as prior arts related to microprocessor failure processing, for example, a memory failure recovery method for a computer system described in Patent Document 1, a multiprocessor system described in Patent Document 2, and file control described in Patent Document 3 A device write-back control method can be used.

JP 09-084464 A JP 2005-010995 A JP 63-045656 A

  In the computer system memory failure recovery method described in Patent Document 1, when the memory failure detection means detects a memory failure in the computer system, the memory page is first closed by the memory partial blocking means, and the update image output means is activated. Then, the update image output means outputs a copy of the failed page data lost in the memory from the memory update trace cache by the trace cache flush means to the secondary storage device by the virtual storage means to recover the failed page. It is.

  According to this method, in order to recover the faulty page, it is necessary that the control program for executing the fault processing operates correctly in the computer system having the memory in which the fault has occurred. For this reason, when a failure occurs in a part other than the cache control unit and the cache flushing process cannot be executed, the failed page cannot be recovered without reinitializing the entire system.

The multiprocessor system described in Patent Document 2 includes a system controller that performs failure processing of a write-back that occurs in a plurality of processors. This system controller issues a dirty hit signal control circuit and a system bus to each processor. A cache line state holding circuit for holding the state of the cache line corresponding to the read memory instruction.
The cache line that each processor holds in a dirty state is automatically transferred to the processor that issued the memory read command and the system controller. When a failure occurs during implicit write back, the transfer source The processor is configured to stop.

  However, this multiprocessor system cannot recover the system without completing the sweeping and initializing the entire system when a processor that has not been swept out of the dirty block fails. .

The file control device write-back control method described in Patent Document 3 includes a channel interface unit and a device interface unit each including a processor in addition to a cache memory, a cache control unit, and a resource management unit. Yes.
In the event of a failure of the cache control unit, a write back process is performed by a processor provided in the channel interface unit or device interface unit under the instruction of the resource management unit.

However, this write-back control device is simply related to the duplication of the cache control unit, and is configured to include a plurality of microprocessors in order to realize this. Further, when a failure occurs in the cache control unit, the contents of the cache cannot be swept out.
For this reason, when a failure other than the cache control unit occurs and the cache flushing process cannot be executed, the cache flushing process is properly completed and the system is restored without initializing the entire system. I can't do it.

  The present invention has been considered in view of the above circumstances, and the cache flushing process in the failure processing of the microprocessor is executed by a healthy processor in which no failure has occurred, so that the failed processor can be safely separated from the system. An object of the present invention is to provide a multiprocessor system, a microprocessor, and a failure processing method for the microprocessor.

  In order to achieve the above object, a multiprocessor system according to the present invention is a multiprocessor system composed of two or more microprocessors each having a write-back cache, and a routing for storing cache states of all the microprocessors. A circuit, a means for reading tag information stored in the routing circuit, a means for identifying a real address space cached in a write-back cache in at least one of the microprocessors based on the tag information, and a specification The real address space is read by another healthy microprocessor in which no failure has occurred.

  The microprocessor according to the present invention is a microprocessor having a write-back cache that constitutes a multiprocessor system, and is stored in a routing circuit that stores cache states of all the microprocessors in the multiprocessor system. Means for reading tag information, means for identifying the real address space cached in the write-back cache in at least one of the microprocessors based on the tag information, and identification in the other microprocessor in which the failure has occurred The real address space is read out by the microprocessor in which no failure has occurred.

  According to another aspect of the present invention, there is provided a failure processing method for a microprocessor having a write-back cache that constitutes a multiprocessor system, wherein all microprocessor caches are included in a routing circuit in the multiprocessor system. Store the state, read the tag information stored in the routing circuit, and identify the real address space cached in the write-back cache of at least one microprocessor in the multiprocessor system based on the tag information. In this method, the specified real address space is read by another microprocessor in which no failure has occurred.

According to the present invention, even if a processor is stalled in a state where a dirty block is left in the write-back cache of the microprocessor, the cache flush processing of the failed processor can be executed from another healthy processor. And the processor can be dynamically disconnected.
For this reason, the availability of the system can be improved.

Hereinafter, a preferred embodiment of a multiprocessor system according to the present invention will be described with reference to the drawings.
[First embodiment]
First, the configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the multiprocessor system of this embodiment.

As shown in FIG. 1, in the multiprocessor system of this embodiment, the microprocessors 1 a to 1 d are connected to a storage device 3 via a storage control device 2.
The microprocessors 1a to 1d constitute a multiprocessor and notify each other of the occurrence of a failure using the failure notification interrupt signal line 6.

This failure includes a hardware failure of the microprocessor and a software processing abnormality for executing processing in the microprocessor.
However, it is assumed that the cache control unit 11 described later is not affected by any of these hardware failures or software processing abnormalities.

The microprocessors 1 a to 1 d use the memory bus 4 to access the real address space 30 in the storage device 3.
The routing circuit 20 in the storage controller 2 is a chip set that stores the cache states of all the microprocessors.

The routing circuit 20 monitors which real address space in each storage device 3 is accessed by each microprocessor, and is cached in a write-back cache 10 (also referred to as a store-in cache) in each of the microprocessors 1a to 1d. Information of the memory block 31 (hereinafter sometimes referred to as routing information) is stored.
Further, the routing information stored in the routing circuit 20 can be read out by any of the microprocessors 1 a to 1 d using the routing information read signal line 5.

  FIG. 2 is a block diagram showing the write-back cache 10 and the routing circuit 20 in the microprocessor of this embodiment. The figure illustrates the write-back cache 10, the virtual address register 15, and the routing information read register 16 of the microprocessor 1a, but other microprocessors have the same configuration.

  Memory access (write operation) information from the arithmetic unit of the microprocessor 1a is stored in the virtual address register 15, and is decomposed into a tag field, an index field, and a line field associated with specific bits in the virtual address space. The

  Among these values, the values of the tag field and the index field are output from the virtual address register 15 to the write-back cache 10 and used in the processing in the comparison circuit 12, the cache control unit 11, and the like, respectively. The value of the line field is output to the real address register 13 in the write-back cache 10 without processing (no conversion).

The write-back cache 10 of this embodiment shown in FIG. 2 is a configuration example of a set associative mapping method cache.
The write-back cache 10 includes a cache control unit 11, a comparison circuit 12, a real address register 13, and a data register 14.

  The cache control unit 11 holds a part of the data in the storage device 3, tag information associated with the virtual address and the real address in the storage device 3, and a valid bit indicating whether or not the cache entry is valid ( V bit) and a status bit (S bit) indicating whether or not the data on the cache is updated from the microprocessor (dirty or clean).

  In general, when creating a cache, when a processor writes to the memory, the memory space in the main memory or the cache of another processor is taken into the cache of its own processor and updated. In order to clearly indicate that the only memory space is held and updated by the own processor, the status bit is set to “dirty”.

  On the other hand, if the processor is only reading into the memory and is cached in the processor, but the other processor caches the same real address space unless it is only referenced, the cache contents of its own processor There is no need to transfer it to the cache. Such a state is called a clean state, and the state bit is clean.

  In order to change the dirty state (updated) to the clean state (not updated), there is a method of sweeping the cache contents of the own processor to the main memory (storage device 3) as a spontaneous (active) method. . Further, as a passive method, there is a method of transferring to the cache by another processor.

  The cache flush process is performed for a cache whose valid bit is “valid” and whose status bit is “dirty”, and is not performed for a cache whose valid bit is “invalid” or whose status bit is “clean”.

The comparison circuit 12 compares the tag of the cache control unit 11 with the value of the tag field of the virtual address register 15.
The real address register 13 generates address information indicating the real address space on the storage device 3 when the cache is miss-hit.

The output information (at the time of a miss) by the real address register 13 is sent to the routing circuit 20 of the storage control device 2 via the memory bus 4.
The output information includes the same tag and index values as those in the cache control unit 11 as shown in FIG.
The data register 14 is a buffer that primarily stores data on the cache 11 or data in the storage device 3.

The routing circuit 20 is a chip set that stores routing information 21a to 21d corresponding to the microprocessors 1a to 1d, respectively.
The routing information 21a to 21d includes the same tag information as the cache control unit 11 of the write-back cache 10 and a valid bit (V bit) indicating whether or not the routing entry is valid.

The routing information 21a to 21d is connected to the routing information read register 16 of each microprocessor using the routing information read signal line 5, and refers to the cache state of all the microprocessors in the system by any microprocessor. be able to.
The multiprocessor system in the present embodiment is an example in which a conventionally known set associative mapping method is applied, but is not limited to this, and other mapping methods such as a direct mapping method and a complete associative mapping method are used. It may be replaced.

Next, the configuration and operation of the multiprocessor system of this embodiment will be described in more detail with reference to FIGS.
In FIG. 1, it is assumed that the multiprocessor system of this embodiment is operated by four microprocessors 1a to 1d, and a failure occurs in the microprocessor 1a and the failure processing is performed by the microprocessor 1b. explain.

The microprocessor 1 a has a write-back cache 10 and caches a specific memory block 31 in the real address space 30 when writing to the storage device 3 is performed.
The cached memory block is called a dirty block, and when another microprocessor accesses the same real address space, it performs a matching process with the data in the cache of the microprocessor 1a, thereby making the memory consistent. Operates to maintain (coherency).

  Memory consistency means that there is an entity in a copy of the memory scattered in the main memory (storage device 3) or the cache of each processor, and this entity is transferred between the main memory and the cache. This is the control that keeps up-to-date by transferring data.

Normally, a multiprocessor system having a dynamic detachment function has a mechanism for flushing the cache contents to the memory when the microprocessor is disconnected in order to maintain the consistency of the memory.
One example is a microprocessor cache flush instruction. The cache flush instruction is executed by software during the processing by the failure handler of the microprocessor or the disconnection processing.

For example, it is assumed that a failure that causes the processor to stall in the microprocessor 1a occurs and the failure processing handler of the microprocessor 1a stops in a state where it cannot operate.
In this state, if the microprocessor 1a is dynamically disconnected from the system, the dirty blocks left in the cache of the microprocessor 1a are lost from the system, and the consistency of the memory cannot be maintained.
Therefore, according to the present embodiment, a means for sweeping out dirty blocks left in the write-back cache of the microprocessor from the cache is provided.

  Specifically, as shown in FIG. 2, routing information 21a to 21d for managing the cache states of all the microprocessors provided in the routing circuit 20, and routing information for reading tag information and valid bits of the routing circuit by an arbitrary microprocessor. An information read register 16, a microprogram for identifying a real address space cached in a write-back cache of an arbitrary microprocessor based on the read tag information, and the cache real address space in which no failure has occurred Dirty block sweeping processing is realized by means of reading (dummy reading) by a healthy microprocessor.

  A sound microprocessor issues a dummy read to the memory bus 4 and if the entity is in the cache of the failed microprocessor, it stores from the cache of the failed microprocessor if it is on the storage device. Reading (transfer) from the device can be performed.

  In this embodiment, since only the information in the cache of the failed microprocessor can be selected from the tag information of the routing circuit 20 in the storage control device 2 and dummy read can be performed, it is not read from the storage device. Reading from the cache of the failed microprocessor is performed.

  Further, the data transfer is performed by the dummy read in the path of the cache control unit 11 of the failed microprocessor → the memory bus 4 → the cache control unit 11 of the healthy microprocessor → the internal register of the healthy microprocessor.

The storage location of the microprogram is not particularly limited and is not shown in FIG.
That is, the storage location of the microprogram depends on the platform. If the control program (firmware) is built in the processor, it is stored in the RAM or ROM in the processor. It can also be stored in the main memory (storage device) as part of the OS read from the hard disk.

Before the failure occurs, the microprocessor 1a performs memory access according to the following procedure.
First, memory access information from the arithmetic unit of the microprocessor 1 a is stored in the virtual address register 15.

The lower bits of the virtual address register 15 constitute a line field.
This lower bit corresponds to the memory access size to the cache line and the storage device 3, and data transfer is performed with this size as one block.

The upper bits of the virtual address register 15 are broken down into a tag field and an index field.
The tag includes the upper bits of the real address space of the storage device 3 and is stored in the cache control unit 11 together with the data.
The index indicates an offset address in the cache. When referring to memory data, this index can be used to access a line in the cache.

  Next, the tag associated with the cache line is read, and the comparison circuit 12 compares the tag field with the value in the virtual address register 15. As a result of the comparison, if there is a mismatch (mishit), access to the storage device 3 is executed via the real address register 13 and data is written.

The high-order bits of the real address register 13 indicate the high-order bits of the real address space of the storage device 3 in the same way as the tag field of the virtual address register 15 and the tag of the cache control unit 11, and are stored simultaneously with the memory access of the microprocessor 1a. It is stored in routing information 21 a corresponding to the processor 1 a provided in the routing circuit 20 of the control circuit 2.
By the processing as described above, the same tag information and the valid bit (V bit) of the tag are recorded in the cache control unit 11 of the microprocessor 1a and the routing information 21a of the storage control circuit 20.

Next, when a failure occurs in the microprocessor 1a, the failure of the microprocessor 1a is notified to another healthy microprocessor 1b using the failure notification interrupt signal line 6.
The microprocessor 1 b uses the routing information read signal line 5 to read the routing information 21 a of the failed microprocessor 1 a into its own routing information read register 16.

The microprocessor 1b changes the index, that is, checks the tags in order from the top, checks the tag and the valid bit of the routing information 21a, and the cache of the microprocessor 1a caches which memory block in the real address space. Make sure that
The tag information includes the start address of the cached memory block, and the real address space is defined as the memory space for the block size from the start address of the memory block based on the tag value, the index value, and the memory block size. Can be calculated.

Using the data register 14 in the microprocessor 1b as a data transfer path, a block size read (dummy read) is executed for the real address calculated by the above procedure.
This process maintains the cache consistency between the microprocessors 1b and 1a, and the dirty blocks left in the microprocessor 1a cache are swept out to the storage device 3 (actually the microprocessor 1b cache). It will be in a clean state.

The microprocessor 1a can be safely disconnected from the system by flushing all dirty blocks from the cache.
Note that hot-line insertion / removal processing and the like are well-known for the dynamic disconnection processing of the microprocessor, but the processing is a general technique, and the configuration and mechanism thereof are the same as the conventional one, so the description thereof is omitted. .

As described above, according to the multiprocessor system of this embodiment, even when a failure such as a stall occurs in the microprocessor, a dirty block is left in the write-back cache, and a control program such as BIOS does not operate. As long as there is no failure in the cache control unit, the dirty block can be appropriately swept out from the cache control unit by executing the cache flushing process of the processor in which the failure has occurred by another healthy processor.
For this reason, while maintaining the consistency of the memory, the failed processor can be safely separated from the system, and the availability of the system can be improved.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the multiprocessor system of this embodiment.
This embodiment is different from the first embodiment in that the multiprocessor system has two or more storage devices 3. The other points are the same as in the first embodiment, and the failure processing procedure of the microprocessor in the multiprocessor system of this embodiment can be the same as that in the first embodiment.

That is, the multiprocessor system of the present embodiment is configured to share the real address space among a plurality of storage devices 3 as shown in FIG.
The microprocessor fault processing method of the present invention can be suitably used for such a multiprocessor system as in the first embodiment.

It goes without saying that the present invention is not limited to the above embodiment, and that various modifications can be made within the scope of the present invention.
For example, a failure occurs not in the microprocessor 1a but in the other microprocessors 1b to 1d, and the cache flushing process is performed by the microprocessor 1a or the other microprocessors 1b to 1d in which no failure occurs. Or other methods such as a direct mapping method or a complete associative mapping method can be used as the cache method.

  INDUSTRIAL APPLICABILITY The present invention can be suitably used for a multiprocessor system that is highly required to perform fault processing without stopping the entire system when a fault occurs in the multiprocessor system.

It is a block diagram which shows the structure of the multiprocessor system of 1st embodiment of this invention. It is a block diagram which shows the structure of the microprocessor and routing circuit in the multiprocessor system of 1st embodiment of this invention. It is a block diagram which shows the structure of the multiprocessor system of 2nd embodiment of this invention.

Explanation of symbols

1 (1a, 1b, 1c, 1d) Microprocessor 2 Storage controller 3 (3-1, 3-2,..., 3-n) Storage device 4 Memory bus 5 Routing information read signal line 6 Fault notification interrupt signal Line 10 Write-back cache 11 Cache control unit 12 Comparison circuit 13 Real address register 14 Data register 15 Virtual address register 16 Routing information read register 20 Routing circuit 21 (21a, 21b, 21c, 21d) Routing information 30 Real address space 31 Memory block

Claims (10)

A multiprocessor system comprising two or more microprocessors each having a write-back cache,
A routing circuit for storing a cache state of all the microprocessors;
Means for reading tag information stored in the routing circuit;
Means for identifying a real address space cached in a write-back cache in at least one of the microprocessors based on the tag information;
Means for reading out the specified real address space by another healthy microprocessor in which no failure has occurred. The multiprocessor system according to claim 1, further comprising a storage device.
Each of the microprocessors includes a virtual address register for storing memory access information from a computing unit in each microprocessor;
The write-back cache in each microprocessor is
A part of the data in the storage device is stored as a cache, tag information associated with a virtual address and a real address in the storage device, validity determination information indicating whether each cache entry is valid, and on the cache A cache control unit that stores state determination information indicating whether or not the data from the microprocessor is updated,
A comparison circuit for comparing tag information of the cache control unit and tag information of the virtual address register;
If the result of the comparison does not match, address information indicating a real address space on the storage device is generated, and a real address register that outputs tag information of the cache control unit to the routing circuit;
A multiprocessor system, comprising: a data register that primarily stores data on the cache or data of the storage device and performs a read process of the specified real address space. The specified real address space is read from a microprocessor that has failed and is one of the microprocessors by any one of the microprocessors that has not failed, and the failure has occurred. The multiprocessor system according to claim 2, wherein the cache control unit is stored in a non-microprocessor. The specified real address space is read from a microprocessor that has failed and is one of the microprocessors by any one of the microprocessors that has not failed, and is stored in the storage device. The multiprocessor system according to claim 2, wherein: The failure includes a hardware failure of the microprocessor and a software processing abnormality for executing processing in the microprocessor, and the cache control unit includes a hardware failure or a software processing abnormality. The multiprocessor system according to claim 2, wherein none of the influences are exerted. A microprocessor with a write-back cache that constitutes a multiprocessor system,
Means for reading tag information stored in a routing circuit for storing cache states of all microprocessors in the multiprocessor system;
Means for identifying a real address space cached in a write-back cache in at least one of the microprocessors based on the tag information;
Means for reading out the specified real address space in another microprocessor in which a failure has occurred by means of the microprocessor in which a failure has not occurred. The microprocessor includes a virtual address register for storing memory access information from a computing unit in the microprocessor;
The write-back cache is
A part of data in the storage device in the multiprocessor system is stored as a cache, tag information associated with a virtual address and a real address in the storage device, validity determination information indicating whether each cache entry is valid, And a cache control unit for storing state determination information indicating whether or not the data on the cache is updated from the microprocessor;
A comparison circuit for comparing tag information of the cache control unit and tag information of the virtual address register;
If the result of the comparison does not match, the address information indicating the actual address space on the storage device is generated, and the tag information of the cache control unit is output to the routing circuit; and
The microprocessor according to claim 6, further comprising: a data register that temporarily stores data on the cache or data of the storage device and performs a read process of the specified real address space. 8. The specified real address space is read from another failed microprocessor by the data register in the microprocessor and stored in a cache control unit in the microprocessor. Microprocessor. A method of handling a failure of a microprocessor having a write-back cache that constitutes a multiprocessor system,
Storing the cache state of all the microprocessors in a routing circuit in the multiprocessor system;
Read tag information stored in the routing circuit,
Based on the tag information, identify a real address space cached in a write-back cache of at least one of the microprocessors in the multiprocessor system;
A failure processing method for a microprocessor, wherein the specified real address space is read by another microprocessor in which no failure has occurred. Storing memory access information from a computing unit in the microprocessor in a virtual address register;
A part of the data in the storage device in the multiprocessor system is stored as a cache in the write-back cache, and the tag information associated with the virtual address and the real address in the storage device, and whether each cache entry is valid Storing valid discrimination information indicating whether or not, and status determination information indicating whether or not the data on the cache is updated from the microprocessor,
Compare the tag information of the cache control unit and the tag information of the virtual address register,
If the result of the comparison does not match, generate address information indicating a real address space on the storage device,
While executing access to the storage device, the tag information of the cache control unit is output to the routing circuit,
When a failure occurs in at least one of the microprocessors constituting the multiprocessor system, the microprocessor in which no failure has occurred reads the tag information stored in the routing circuit,
Based on the tag information, the real address space cached in the write-back cache in the failed microprocessor is specified,
The failure processing method for a microprocessor according to claim 9, wherein the specified real address space is read.

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