JPH06250933A - Access control method for information processor and main storage - Google Patents

Abstract

PURPOSE:To economically back up memory in a defective place by exchanging the defective memory of a main storage device in an information processor by a cache storage device. CONSTITUTION:The information processor provided with a central processing unit 1, the main storage device 2 and the cache storage device 3 is provided with tag information storage parts 11a-11d accumulating at least more than one piece of tag information showing the defective place of the main storage device 2 and data storage parts 12a-12d corresponding to the tag information storage parts in the cache storage device 3. When an address at the time of memory access coincides with defective tag information, the central processing unit 1 does not access memory to the main storage device 1 and accesses memory to the data storage parts which are prepared in accordance with the tag information parts is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a function of replacing a defective portion when a memory failure occurs in a main memory used for a computer and the like, and an access control method for the main memory.

[0002]

2. Description of the Related Art In recent years, the circuit configuration of computers has become large-scale integration (LSI), and the number of parts is decreasing. on the other hand,
The memory capacity required by application programs is increasing rapidly, and improvement in memory integration is not always catching up. For this reason, the number of memory ICs accounts for a large proportion of the total number of components of the device, and the possibility of component failure tends to concentrate on the memory section.

A temporary error (for example, a soft error) in the memory can be remedied by correction with an error correction code.
On the other hand, when there is a memory failure, particularly a failure of some cells in the memory chip, but a failure such that one memory chip cannot operate, there is a high possibility that the system will stop. Then, once such a failure occurs, the system becomes inoperable until the board on which the memory is mounted is replaced. In order to prevent such a system stop, or at least as a means for preventing a system stop for a long time, a method of memory duplication has been adopted.

In addition, instead of duplicating the entire memory, there has been considered a method of duplicating only the memory area in which important programs and data are stored particularly in terms of system operation.

[0005]

When the entire area of the memory is duplicated as described above, especially in a system using a large-capacity memory, the cost is greatly increased, and
A large memory installation space is also required. Although it is extremely unlikely that a plurality of memories will fail at the same time, the utilization efficiency of the duplicated portion is also poor because it is necessary to prepare for the failure of all the memories.

Further, the method of duplicating only a part of the important memory area is an incomplete measure because the operation that the system should originally have may not be expected. The present invention has been made in view of the above points, and an object thereof is to solve the above-mentioned problems and provide an information processing device with a defective memory replacement function to economically perform memory backup of a defective portion. It is to provide a processing device and an access control method for a main storage device used in an information processing device.

[0007]

In order to achieve the above object, an information processing apparatus having a defective memory replacement function of the present invention is an information processing apparatus including a central processing unit, a main storage unit and a cache storage unit. In the cache memory device, a tag information storage unit for storing at least one piece of tag information indicating a defective portion of the main storage device and a data storage unit corresponding to the tag information storage unit are provided, and an address at the time of a memory access request is provided. If the tag information matches the tag information, the memory access to the main storage device is not performed, but the memory access is performed to the data storage unit prepared corresponding to the tag information storage unit.

Further, in the access control method for the main memory used in the information processing apparatus having the above-mentioned configuration, a tag information storage section for storing at least one piece of tag information indicating a defective portion of the main memory in the cache storage, A data storage unit corresponding to this tag information storage unit is provided, and when the system is started up, the cache use instruction signal of the cache storage device and the valid bit of the tag information storage unit are all set to be invalid, and the diagnostic program of the main storage device is set. When executed and a test error occurs, the diagnostic program enables the valid bit in the unused tag information storage unit to record the tag information and the valid bit indicating the memory block in which the error has occurred, and the main memory device When the diagnostic program of is finished, set the cache use instruction signal of the cache storage device to valid and If the address at the time of the access request matches the tag information, without performing memory access to main memory, it is assumed that the memory access data storage portion that is provided in response to the tag information storage unit.

[0009]

With the above configuration, when a part of the memory of the main storage device fails, the system is restarted, at this time, the diagnostic program of the main storage device is executed, and the defective memory block is tagged as tag information in advance. When the central processing unit accesses a defective memory block when the system is operating, it detects this and prohibits access to the main storage device, and the data storage unit of the cache storage device stores it. The system operates normally by substituting the function of the defective memory block of the main storage device.

[0010]

1 is a block circuit diagram showing the concept of an information processing apparatus having a defective memory replacement function according to an embodiment of the present invention. In FIG. 1, a cache storage device 3 connects an address bus 4 and a data bus 5 to an information processing device in which a central processing unit (CPU) 1 and a main storage device 2 are connected via an address bus 4 and a data bus 5. Connected to each other via. Address bus 4 is assumed to consist of m + n addressing bits. The inside of the cache storage device 3 is roughly classified into a tag information storage unit (four 11a to 11d in the illustrated example) for storing tag information, and a data storage unit (12a to 12d) prepared corresponding to the tag information storage unit.
It is divided into two blocks of d). Each tag information storage unit 11
Each of a to 11d is composed of m-bit tag information indicating a defective portion of the main storage device 2 and a valid bit (indicated by V in the figure) indicating that the content of this tag information is valid.

The tag information is the upper m bits of the address information indicating the defective portion of the main storage device 2, and is the information indicating the defective memory block having the size represented by the lower n bits of the address information. The contents of the tag information in the respective tag information storage units 11a to 11d are compared with the upper m-bit address information on the address bus 4 by the comparators 13a to 13d. Now, it is assumed that the tag information indicating the defective portion of the main storage device 2 is stored in any of the tag information storage units 11a to 11d, and the central processing unit (CPU) 1 accesses the defective portion of this memory. When performed, the output of the comparator (13a) corresponding to the corresponding tag information storage unit (for example, 11a) becomes valid.

The outputs of the comparators 13a to 13d are connected to the chip select inputs cs of the corresponding data storage units 12a to 12d, respectively. The output of each comparator 13a to 13d is connected to the OR gate 14, and the output of this OR gate 14 is
This is one input of the ND gate 15. The cache use instruction signal 16 of the cache storage device is connected to the other input of the AND gate 15, and when the cache use instruction signal 16 is valid, the logical sum information of the outputs of the comparators 13a to 13d, that is, the defective memory location. The information indicating whether or not the access is to the hit input signal hit from the output of the AND gate 15 as the hit signal 17 to the hit input signal hit of the data storage units 12a to 12d.
And the main memory 2 is notified. Hit signal 17
Is invalid, the operation of the main storage device 2 is permitted and the operation of the data storage units 12a to 12d is prohibited. When the hit signal 17 is valid, the operation of the main storage device 2 is prohibited, and the comparators 13a to 13d of the data storage units 12a to 12d.
The data storage portion selected by any of the outputs of 13d becomes operable in place of the main storage device 2.

A practical application method of the present invention having the above configuration will be described. First, when the system is started up, the cache use instruction signal 16 of the cache storage device 3
Is set to invalid, and in this state the tag information storage units 11a to 11d
All valid bits are set to be invalid, and the diagnostic program of the main storage device 2 is executed. If a memory access error such as a parity error or an ECC (error correction code) error, or a data collation error when the test data is read out after the test data is written during execution of the diagnostic program, this diagnostic program is executed. At the same time as writing the tag information indicating the memory block in which the error has occurred into the unused tag information storage units 11a to 11d (the valid bit is invalid), the valid bit corresponding to this tag information is set valid. Here, tentatively, the main storage device 2 has one defect, and this defect information is used as the tag information storage unit 11.
It is assumed that tag information indicating the location is registered in a. When the diagnosis of the main storage device 2 is completed, the cache use instruction signal 16 is set to be valid.

Now, after the normal program is started, when the address area corresponding to the defective portion of the main memory 2 is accessed by the central processing unit (CPU) 1, the upper m bits of the address bus 4 and the tag Since the tag information in the information storage unit 11a matches, the output of the comparator 13a becomes valid, and then the hit signal 17 becomes valid through the OR gate 14 and AND gate 15, so that the data storage unit of the cache storage device 3 becomes effective. 12a becomes accessible, while access to the main storage device 2 is prohibited. In this way, the cache storage device 3 fulfills the function of replacing the defective portion of the main storage device 2.

[0015]

As described above, according to the configuration of the present invention, when a defective portion occurs in the main storage device, access to the defective portion is prohibited, and instead, the cache storage device performs the function of the defective portion. As a result, even if the system temporarily stops due to a memory failure in the main storage device, it is possible to restart the system without replacing it with a replacement memory board. Therefore, it is possible to prevent the system from stopping for a long period of time when a random memory failure occurs in a system using a large capacity memory, and it is possible to provide a system with excellent operability. Compared to the case where all the memories are duplicated, by adding a very small capacity memory to the cache storage device, it is possible to efficiently deal with the memory failure of the main storage device. Even if the memory to be replaced is random access memory (RAM), it is a read-only memory.
It may be (ROM), regardless of its type.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing the concept of an embodiment according to the present invention.

[Explanation of symbols]

 1 central processing unit 2 main storage unit 3 cache storage unit 4 address bus 5 data bus 11a, 11b, 11c, 11d tag information storage unit 12a, 12b, 12c, 12d data storage unit 13a, 13b, 13c, 13d comparator 14 OR gate 15 AND gate 16 Cache use instruction signal 17 Hit signal V Valid bit cs Chip select signal input terminal hit Hit signal input terminal

Claims (2)

[Claims] 1. An information processing apparatus comprising a central processing unit, a main storage device and a cache storage device, wherein the cache storage device stores at least one or more tag information indicating a defective portion of the main storage device. An information storage unit and a data storage unit corresponding to this tag information storage unit are provided, and when the address at the time of the memory access request matches the tag information, the memory access to the main storage device is not executed and the tag is stored. Information processing apparatus characterized by performing memory access to a data storage section prepared corresponding to the information storage section 2. A tag information storage unit comprising a central processing unit, a main storage unit, and a cache storage unit, wherein the cache storage unit stores at least one or more tag information indicating a defective portion of the main storage unit. A data storage unit corresponding to the tag information storage unit is provided, and when the system is started up, the cache use instruction signal of the cache storage device and the valid bit of the tag information storage unit are all set to invalid, and the diagnostic program of the main storage device is executed. Then, when a test error occurs, the diagnostic program enables the valid bit in the unused tag information storage unit to record the tag information and the valid bit indicating the memory block in which the error has occurred, and the main storage device When the diagnostic program of the above is finished, the cache use instruction signal of the cache storage device is set to be valid, and the memory When the address at the time of the access request matches the tag information, the memory access to the main memory is not performed, but the memory access is performed to the data storage unit prepared corresponding to the tag information storage unit. Access control method for main storage device.