CN117037884B

CN117037884B - Fuse unit used in memory array, processing method thereof and memory array

Info

Publication number: CN117037884B
Application number: CN202311306618.6A
Authority: CN
Inventors: 俞剑; 杨子岳; 蒋冰倩
Original assignee: Zhejiang Liji Storage Technology Co ltd
Current assignee: Zhejiang Liji Storage Technology Co ltd
Priority date: 2023-10-10
Filing date: 2023-10-10
Publication date: 2024-02-23
Anticipated expiration: 2043-10-10
Also published as: CN117037884A

Abstract

Embodiments of the present disclosure provide a fuse cell for use in a memory array, a processing method thereof, and a memory array. The fuse unit includes: k fuse subunits. Each fuse subunit includes a plurality of fuse groups. K is equal to 2 ^M . Each bit of the default value for each fuse set is 0. When the value of the fuse set is not equal to the default value, the redundant memory address associated with the fuse set is used to replace the defective memory address stored by the fuse set. The i-th fuse subunit does not store a defective memory address designating that the value of M bits is equal to i and that the remaining bits are all 0. The target bit of the defective memory address is inverted before the defective memory address is stored in the j-th fuse subunit. When the value of any fuse set in the jth fuse subunit is not equal to the default value, the target bit of the value of the fuse set is inverted to obtain the output value of the fuse set. j is greater than 0 and less than K. The target bit is a bit corresponding to a bit equal to 1 of j among the designated M bits.

Description

Fuse unit used in memory array, processing method thereof and memory array

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor device technology, and in particular, to a fuse unit used in a memory array, a processing method thereof, and a memory array.

Background

The memory typically includes a memory array. The memory array includes a plurality of memory cells. In a memory array of a conventional memory-like chip, each piece of information is stored separately in a memory cell of the array, the memory cell having a unique row address and column address. When reading data, only the corresponding row/column address is found. To avoid the inability to write/read data when a certain row/column of memory cells is damaged, a "spare" row or column (corresponding to redundant memory cells) may be used. When damage occurs somewhere in the original storage array and the access is not possible, a standby row/column address prepared in advance is started, and data is written into the standby address. Similarly, data is read from the "spare" address, allowing the memory function to proceed normally.

Address information to be replaced in the original memory array (the address of the defective memory cell, which may also be referred to as a "defective memory address") is stored in fuse sets, each fuse set being in one-to-one correspondence with a spare row or column. When the selected address corresponds to the address stored in the fuse set, the line or column corresponding to the address is damaged, and the fuse set is switched to the standby address corresponding to the fuse set.

However, the fuse set has a default value. If the input address corresponds to the default value, it cannot be distinguished whether or not the replacement is needed. Thus, one main fuse is provided in each fuse set to indicate whether the fuse set is used or not. If the input address corresponds to the default value, but the main fuse is not set to be 'used', no replacement is needed; and otherwise, replacing. Thus, a fuse set is generally composed of N fuses for recording addresses and 1 master fuse, N being equal to the number of bits of the address to be stored at maximum.

Since each fuse set requires N fuses recording addresses and an additional 1 master fuse to record whether the fuse set is used, the number of fuses required for the fuse set used in the memory array is large, resulting in a large chip area of the memory array.

Disclosure of Invention

Embodiments described herein provide a fuse cell for use in a memory array, a processing method thereof, and a memory array.

According to a first aspect of the present disclosure, a fuse cell for use in a memory array is provided. The fuse unit includes: k fuse subunits. Each fuse subunit includes a plurality of fuse groups. Each fuse set includes N fuses. K is equal to 2 ^M . M is a positive integer. N is equal to the number of bits of the memory address of the memory array. Wherein each fuse set is capable of storing one defective memory address of the memory array. Each fuse set is associated with one redundant memory address of the memory array. Each bit of the default value of each fuse set is0. In the event that the value of the fuse set is not equal to the default value, the redundant memory address associated with the fuse set is used to replace the defective memory address stored by the fuse set. The i-th fuse subunit of the K fuse subunits is configured to not store a defective memory address designating M bits equal in value to i and the remaining bits are all 0. Wherein the remaining bits are bits of the defective memory address other than the designated M bits. i is greater than or equal to 0 and less than K. The j-th fuse subunit of the K fuse subunits further includes a plurality of inverters. The target bit of the defective memory address is inverted by an inverter before the defective memory address is stored in the j-th fuse subunit. In the case where the value of any fuse group in the jth fuse subunit is not equal to the default value, the target bit of the value of the fuse group is inverted by an inverter to obtain the output value of the fuse group. Wherein j is greater than 0 and less than K. The target bit is a bit corresponding to a bit equal to 1 of j among the designated M bits.

In some embodiments of the present disclosure, for each fuse set, in the event that the redundant memory address associated with that fuse set is corrupted, the value of that fuse set is set to a corruption indication value. Each bit of the damage indication value is 1. In the event that the value of any fuse set is equal to the damage indication value, the redundant memory address associated with that fuse set is not used to replace the defective memory address of the memory array. The i-th fuse subunit is further configured to not store a defective memory address designating the M bits as having a value equal to the inversion of i and the remaining bits as 1. In the case where the value of any fuse group in the jth fuse subunit is equal to the damage instruction value, the output value of the fuse group is set equal to the value of the fuse group.

In some embodiments of the present disclosure, the number of fuse groups in each fuse subunit is not equal.

In some embodiments of the present disclosure, the number of fuse groups in each fuse subunit is equal.

In some embodiments of the present disclosure, the designated M bits are the lowest M bits of the defective memory address.

In some embodiments of the present disclosure, the designated M bits are discontinuous M bits of the defective memory address.

According to a second aspect of the present disclosure, there is provided a processing method for processing a fuse unit according to the first aspect of the present disclosure. The processing method comprises the following steps: receiving a defective memory address of a memory array; acquiring a value of a designated M bit of a defect memory address as an allocation reference value; determining whether the remaining bits of the defective memory address are all 0, the remaining bits being bits of the defective memory address other than the designated M bits; and storing the defective memory address to an unused one of the p-th fuse subcells of the K fuse subcells in response to the remaining bits of the defective memory address being all 0. Wherein p is not equal to the assigned reference value. The value of the unused fuse set is equal to the default value. Each bit of the default value is 0.

In some embodiments of the present disclosure, the processing method further comprises: in response to the storage array being accessed, taking each fuse set as a target fuse set and performing the following operations: determining whether the value of the target fuse set is equal to a default value; in response to the value of the target fuse set not being equal to the default value, comparing the access address of the access storage array with the output value of the target fuse set; and in response to the access address matching the output value of the target fuse set, linking the access to the access address to a redundant memory address associated with the target fuse set.

In some embodiments of the present disclosure, the processing method further comprises: determining whether the remaining bits of the defective memory address are all 1; storing the defective memory address to an unused one of the q-th fuse subcells of the K fuse subcells in response to the remaining bits of the defective memory address being 1, wherein the inverse of q is not equal to the assigned reference value; and for each fuse set, setting a value of the fuse set to a damage indication value in response to the redundant memory address associated with the fuse set being damaged. Each bit of the damage indication value is 1.

In some embodiments of the present disclosure, the processing method further comprises: in response to the storage array being accessed, taking each fuse set as a target fuse set and performing the following operations: determining whether the value of the target fuse set is equal to a default value or a damage indication value; comparing an access address of the access storage array with an output value of the target fuse set in response to the value of the target fuse set not being equal to the default value and not being equal to the damage indication value; and in response to the access address matching the output value of the target fuse set, linking the access to the access address to a redundant memory address associated with the target fuse set.

According to a third aspect of the present disclosure, a memory array is provided. The memory array includes: a fuse unit according to the first aspect of the present disclosure.

According to a fourth aspect of the present disclosure, a semiconductor device is provided. The semiconductor device comprises a memory array according to the third aspect of the present disclosure.

According to a fifth aspect of the present disclosure, a processing apparatus is provided. The processing means is for processing the fuse unit according to the first aspect of the present disclosure. The processing device includes at least one processor; and at least one memory storing a computer program. The computer program, when executed by at least one processor, causes the processing device to perform the processing method according to the second aspect of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

FIG. 1 is an exemplary block diagram of a fuse cell for use in a memory array;

FIG. 2 is an exemplary block diagram of a fuse cell for use in a memory array according to an embodiment of the present disclosure;

FIG. 3 is a schematic operational schematic of the 0 th fuse subunit shown in FIG. 2;

FIG. 4 is a schematic operational schematic of the 1 st fuse subunit shown in FIG. 2;

FIG. 5 is a schematic operational schematic of the 2 nd fuse subunit shown in FIG. 2;

FIG. 6 is a schematic operational schematic diagram of the 3 rd fuse subunit shown in FIG. 2;

FIG. 7 is a schematic operational schematic diagram of the 0 th fuse subunit shown in FIG. 2 handling redundant damage;

FIG. 8 is a schematic operational schematic diagram of the 1 st fuse subunit shown in FIG. 2 handling redundant damage;

FIG. 9 is a schematic operational schematic diagram of the 2 nd fuse subunit shown in FIG. 2 handling redundant damage;

FIG. 10 is a schematic operational schematic diagram of the 3 rd fuse subunit shown in FIG. 2 handling redundant damage;

FIG. 11 is a schematic flow chart diagram of a processing method for processing a fuse unit according to an embodiment of the disclosure;

FIG. 12 is a schematic flow chart of further steps of a processing method for processing a fuse unit according to an embodiment of the present disclosure;

FIG. 13 is a schematic flow chart of further steps of a processing method for processing a fuse unit according to an embodiment of the disclosure;

FIG. 14 is a schematic block diagram of a memory array according to an embodiment of the present disclosure;

Fig. 15 is a schematic block diagram of a processing device according to an embodiment of the present disclosure.

It is noted that the elements in the drawings are schematic and are not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

As described above, addresses of rows or columns in the memory array where bad pixels occur need to be stored in the fuse set. One fuse set is associated with one redundant memory address. When an address to which the memory array is accessed corresponds to an address stored by the fuse bank, indicating that the row or column to which the address corresponds is defective, it is necessary to replace the address stored by the fuse bank with a redundant memory address associated with the fuse bank. However, the fuse set has a default value. If the address to which the storage array is accessed corresponds to a default value for the fuse set, it cannot be distinguished whether address replacement is required. Thus, a main fuse may be added to each fuse set to indicate whether the fuse set is used (i.e., whether address replacement is required). If the address at which the storage array is accessed corresponds to the default value of the fuse set, but the master fuse is not set to "used", then no address replacement is required; and otherwise, address replacement is carried out. The set of all fuse groups in a storage array may be referred to herein as fuse cells. Fig. 1 shows an exemplary structural diagram of such a fuse unit 100.

As shown in fig. 1, the fuse unit 100 includes S fuse groups Fu1, fu2, fu3, … …, fuS. Each fuse set includes one main fuse 11 and N address fuses (fuses recording addresses) 12.N is equal to the number of bits of the address that is most needed to be stored. In the example of fig. 1, N is equal to 7. For ease of illustration, the description hereinafter will be mainly given by way of example with n=7.

When the memory array is operating normally, the addresses of the S fuse sets are initialized to a default value, typically "0000000,0". The first 7 bits represent address bits, and the last additional 1 bit represents the usage of the group (0 represents unused, 1 represents used). Once the current fault can not be read and written normally, the row address information of the fault can be stored in the fuse set in the repairing process. Assuming that redundant row 1 is used to repair the failed row address 0101110, the fuse set corresponding to redundant row 1 (e.g., fuse set Fu1 in fig. 1) is written to "0101110,1". In "0101110,1", the first 7 bits represent the row address 0101110, and the last additional 1 bit represents that the set has been used.

The content recorded in the fuse set is loaded into the corresponding circuit structure during the fuse loading process. When the recorded fault line is ready to be accessed next time, the corresponding redundant line is directly jumped to be accessed, so that the completeness of the read-write process of the storage array is ensured.

For a memory array having a redundancy structure, it is generally necessary to prepare a fuse set corresponding to the number of redundant rows. Assuming that the memory array has S redundant row structures and that the number of row addressing bits is N under normal operation of the memory array, then the addition of the master fuse representing the use state requires the use of (n+1) ×s fuse resources. If the fuse resources required to be used can be reduced, hardware costs can be saved and the area of the memory array can be reduced.

The present disclosure proposes a fuse unit for use in a memory array that saves hardware costs and reduces the area of the memory array by removing a main fuse. The fuse unit includes: k fuse subunits. Each fuse subunit includes a plurality of fuse groups. Each fuse set includes N fuses. K is equal to 2 ^M . M is a positive integer. N is equal to the number of bits of the memory address of the memory array.

Wherein each fuse set is capable of storing one defective memory address of the memory array. Each fuse set is associated with one redundant memory address of the memory array. Each bit of the default value for each fuse set is 0. In the event that the value of the fuse set is not equal to the default value, the redundant memory address associated with the fuse set is used to replace the defective memory address stored by the fuse set. In the event that the value of the fuse set is equal to the default value, the redundant memory address associated with the fuse set is not used to repair the memory array.

The i-th fuse subunit of the K fuse subunits is configured to not store a defective memory address designating M bits equal in value to i and the remaining bits are all 0. Wherein the remaining bits are bits of the defective memory address other than the designated M bits. i is greater than or equal to 0 and less than K. In other words, the i-th fuse subunit refers to each of the K fuse subunits, each of which is subject to the above-described configuration. The value of i may be converted into an M-bit binary number for comparison with the value of the designated M-bit of the defective memory address. In the example where M is equal to 2 and i is equal to 0, the 0 th fuse subunit is configured to not store a defective memory address designating that the value of 2 bits is equal to binary 00 and the remaining bits are all 0. In the example where M is equal to 2 and i is equal to 1, the 1 st fuse subunit is configured to not store a defective memory address designating that the value of 2 bits is equal to binary 01 and the remaining bits are all 0. In the example where M is equal to 2 and i is equal to 2, the 2 nd fuse subunit is configured to not store a defective memory address designating that the value of 2 bits is equal to binary 10 and the remaining bits are all 0. In the example where M is equal to 2 and i is equal to 3, the 3 rd fuse subunit is configured to not store a defective memory address designating 2 bits equal in value to binary number 11 and the remaining bits are all 0.

The j-th fuse subunit of the K fuse subunits further includes a plurality of inverters. Wherein j is greater than 0 and less than K. That is, the jth fuse subunit refers to each of the K fuse subunits except for the 0 th fuse subunit. The target bit of the defective memory address is inverted by an inverter before the defective memory address is stored in the j-th fuse subunit. In the case where the value of any fuse group in the jth fuse subunit is not equal to the default value, the target bit of the value of the fuse group is inverted by an inverter to obtain the output value of the fuse group. The target bit is a bit corresponding to a bit equal to 1 of j among the designated M bits. In the example where the designated M bits are the lowest 2 bits of the defective memory address and j is equal to 1, the target bit is the lowest 1 bit of the defective memory address. The lowest 1 bit of the defective memory address is inverted by an inverter before the defective memory address is stored in the 1 st fuse subunit. Assuming that the defective memory address is "XXXXX10", the lowest 1 bit of the defective memory address is inverted by an inverter to obtain an address "XXXXX11", and the address "XXXXX11" is stored in an unused fuse group in the 1 st fuse subunit. In the case where the value of any fuse group in the 1 st fuse subunit is not equal to the default value "0000000", the lowest 1 bit of the value of the fuse group is inverted by an inverter to obtain the output value of the fuse group. Thus, the output value of the fuse set having the value "XXXXX11" is equal to "XXXXX10", in agreement with the defective memory address "XXXXX10" stored in the fuse set. Thus, although the defective memory address is changed before being stored in the fuse set, the output value of the fuse set is kept identical to the defective memory address, and the defective memory address to be repaired can be correctly identified. In this context, "X" means any binary value (i.e., X may be 0 or 1).

An exemplary structural diagram of a fuse cell 200 used in a memory array according to an embodiment of the present disclosure is described below with reference to fig. 2. In the example of fig. 2, M equals 2,K equals 4 and n equals 7. The fuse unit 200 includes: 4 fuse subunits GP0, GP1, GP2 and GP3. Each of the fuse subunits GP0, GP1, GP2 and GP3 comprises a plurality of fuse groups Fu. Each fuse set Fu includes 7 fuses 12.

Each fuse set Fu is capable of storing one defective memory address of the memory array. Herein, the "defective memory address" refers to failed row address information or column address information. In one example, the defective memory address may be a failed row address in a memory array. In another example, the defective memory address may be a failed column address in a memory array. Each fuse set Fu is associated with one redundant memory address of the memory array. In the case where the defective memory address is a row address, the redundant memory address is a row address for replacing the defective memory address. In the case where the defective memory address is a column address, the redundant memory address is a column address for replacing the defective memory address. For ease of illustration, the defective memory address is hereinafter described as a "row address".

Each bit of the default value of each fuse set Fu is 0. In the example of n=7, the default value of each fuse group Fu is "0000000". In the case where the value of the fuse set Fu is not equal to the default value, the redundant memory address associated with the fuse set Fu is used to replace the defective memory address stored by the fuse set Fu. In the event that the value of the fuse set Fu is equal to the default value, the fuse set Fu is not used and the redundant memory address associated with the fuse set Fu is not used to repair the memory array.

The operation principle of the 4 fuse subunits GP0, GP1, GP2 and GP3 in fig. 2 will be described below with reference to fig. 3 to 6 by taking the example of designating M bits as the lowest 2 bits of the defective memory address. Fig. 3 shows a schematic operating diagram of the 0 th fuse subunit GP0 shown in fig. 2. Fig. 4 shows a schematic operation schematic diagram of the 1 st fuse subunit shown in fig. 2. Fig. 5 shows a schematic operating diagram of the 2 nd fuse subunit shown in fig. 2. Fig. 6 shows a schematic operation of the 3 rd fuse subunit shown in fig. 2.

In the example of fig. 3, the 0 th fuse subunit is configured to not store a defective memory address whose value of the lowest 2 bits is equal to binary number 00 and whose remaining bits are all 0, i.e., "0000000". In the case where the repair-required address (i.e., the defective memory address) is "0000000", repair is performed by fuse sub-units other than the 0 th fuse sub-unit. Thus, when the intra-fuse address (i.e., the value of the fuse set) is "0000000", it is indicated that the fuse set is not used, and the fuse set is not used to repair the memory array. In the case where the repair required address is "XXXXXXX", the "XXXXXXX" may be stored in an unused one of the fuse sets (fuse set having a value of "0000000") in the 0 th fuse subunit. The output value (i.e., output address) of each fuse group in the 0 th fuse subunit is the same as the intra-fuse address. When "XXXXXXX" matches (is identical to) the external access address, the access to "XXXXXXX" is linked to the redundant address associated with the fuse set storing "XXXXXXX". In the example of fig. 3, "XXXXXXX" indicates all values except "0000000".

In the example of fig. 4, the 1 st fuse subunit is configured to not store a defective memory address whose value of the lowest 2 bits is equal to binary number 01 and the remaining bits are all 0, i.e., "0000001". As described above, the target bit is a bit corresponding to a bit equal to 1 of j among the specified M bits. In the example of fig. 4, j=1 (binary 01), designating M bits as the lowest 2 bits and the target bit as the lowest 1 bit. The lowest 1 bit of the defective memory address is inverted by an inverter before the defective memory address is stored in the 1 st fuse subunit. In the case where the value of any fuse group in the 1 st fuse subunit is not equal to the default value "0000000", the lowest 1 bit of the value of the fuse group is inverted by an inverter to obtain the output value (i.e., output address) of the fuse group.

Referring to fig. 4, in the case where the repair required address (i.e., the defective memory address) is "0000001", repair is performed by fuse sub-units other than the 1 st fuse sub-unit. If the lowest 1 bit of "0000001" is inverted by the inverter, "0000000" is obtained. Since the 1 st fuse subunit does not repair address "0000001", when the intra-fuse address (i.e., the value of the fuse set) is "0000000", it is indicated that the fuse set is not used and is not used for repairing the memory array. In the case where the repair-required address is "XXXXX", the least significant 1 bit of "XXXXX" is inverted by an inverter, resulting in "XXXXP". Wherein P represents the inverse of X. P equals 1 when X equals 0 and P equals 0 when X equals 1. "XXXXXXP" may be stored in an unused one of the fuse sets in fuse subunit 1 (the fuse set having a value of "0000000"). Before the fuse set storing "XXXXXXP" is read, the lowest 1 bit of "XXXXP" is inverted by an inverter, resulting in "XXXXX". When "XXXXXXX" matches (is identical to) the external access address, the access to "XXXXXXX" is linked to the redundant address associated with the fuse bank storing "XXXXXXP". In the example of fig. 4, "XXXXXXX" indicates all values except "0000001". In the case where the repair required address is "0000000", the lowest 1 bit of "0000000" is inverted by the inverter, resulting in "0000001". "0000001" is stored in an unused one of the 1 st fuse subunits to distinguish from the default value "0000000" of the fuse group. The output address corresponding to "0000001" is "0000000", and therefore, when the external access address is "0000000", the access to "0000000" can be linked to the redundant address associated with the fuse group storing "0000001".

In the example of fig. 5, the 2 nd fuse subunit is configured to not store a defective memory address whose value of the lowest 2 bits is equal to binary number 10 and whose remaining bits are all 0, i.e., "0000010". As described above, the target bit is a bit corresponding to a bit equal to 1 of j among the specified M bits. In the example of fig. 5, j=2 (binary number 10), designating M bits as the lowest 2 bits and the target bit as the 2 nd bit. The 2 nd bit of the defective memory address is inverted by an inverter before the defective memory address is stored in the 2 nd fuse subunit. In the case where the value of any fuse group in the 2 nd fuse subunit is not equal to the default value "0000000", the 2 nd bit of the value of the fuse group is inverted by the inverter to obtain the output value of the fuse group.

Referring to fig. 5, in the case where the repair required address (i.e., the defective memory address) is "0000010", repair is performed by fuse sub-units other than the 2 nd fuse sub-unit. If the 2 nd bit of "0000010" is inverted by the inverter, then "0000000" is obtained. Since the 2 nd fuse subunit does not repair the address "0000010", when the intra-fuse address (i.e., the value of the fuse set) is "0000000", it is indicated that the fuse set is not used and is not used for repairing the memory array. In the case where the repair required address is "XXXXX", the 2 nd bit of "XXXXX" is inverted by the inverter, resulting in "XXXXXPX". "XXXXXPX" may be stored in an unused one of the fuse sub-units of the 2 nd fuse (the fuse set having a value of "0000000"). Before the fuse set storing "XXXXXPX" is read, the 2 nd bit of "XXXXXPX" is inverted by an inverter, resulting in "XXXXX". When "XXXXXXX" matches (is identical to) the external access address, the access to "XXXXXXX" is linked to the redundant address associated with the fuse set storing "XXXXXPX". In the example of fig. 5, "XXXXXXX" indicates all values except "0000010". In the case where the repair required address is "0000000", the 2 nd bit of "0000000" is inverted by the inverter, resulting in "0000010". "0000010" is stored in an unused one of the fuse subunits of the 2 nd fuse to be distinguished from the default value "0000000" of the fuse group. The output address corresponding to "0000010" is "0000000", and therefore, when the external access address is "0000000", the access to "0000000" can be linked to the redundant address associated with the fuse group storing "0000010".

In the example of fig. 6, the 3 rd fuse subunit is configured to not store a defective memory address whose value of the lowest 2 bits is equal to binary number 11 and the remaining bits are all 0, i.e., "0000011". As described above, the target bit is a bit corresponding to a bit equal to 1 of j among the specified M bits. In the example of fig. 6, j=3 (binary number 11), designating M bits as the lowest 2 bits and the target bit as the lowest 2 bits. The lowest 2 bits of the defective memory address are inverted by an inverter before the defective memory address is stored in the 3 rd fuse subunit. In the case where the value of any fuse group in the 3 rd fuse subunit is not equal to the default value "0000000", the lowest 2 bits of the value of the fuse group are inverted by an inverter to obtain the output value of the fuse group.

Referring to fig. 6, in the case where the repair required address (i.e., the defective memory address) is "0000011", repair is performed by fuse subunits other than the 3 rd fuse subunit. If the least significant 2 bits of "0000011" are inverted by an inverter, "0000000" is obtained. Since the 3 rd fuse subunit does not repair address "0000011", when the intra-fuse address (i.e., the value of the fuse bank) is "0000000", this fuse bank is indicated as unused and is not used to repair the memory array. In the case where the repair required address is "XXXXX", the least significant 2 bits of "XXXXX" are inverted by an inverter, resulting in "XXXXXPP". "XXXXXPP" may be stored in an unused one of the fuse sets in the 3 rd fuse subunit (the fuse set having a value of "0000000"). Before the fuse set storing "XXXXXPP" is read, the lowest 2 bits of "XXXXXPP" are inverted by an inverter, resulting in "XXXXX". When "XXXXXXX" matches (is identical to) the external access address, the access to "XXXXXXX" is linked to the redundant address associated with the fuse set storing "XXXXXPP". In the example of fig. 6, "XXXXXXX" indicates all values except "0000011". In the case where the repair required address is "0000000", the least significant 2 bits of "0000000" are inverted by the inverter, resulting in "0000011". "0000011" is stored into an unused one of the 3 rd fuse subunits to distinguish it from the default value "0000000" of the fuse group. The output address corresponding to "0000011" is "0000000", and therefore, when the external access address is "0000000", an access to "0000000" can be linked to a redundant address associated with the fuse group storing "0000011".

The fuse unit 200 according to the embodiment of the present disclosure distinguishes whether a fuse set is used through grouping repair, and in the case where a value of any fuse set is equal to a default value (e.g., "0000000"), it indicates that the fuse set is not used. When the defective memory address is equal to a default value (e.g., "000000") of the fuse group, the defective memory address is stored in the fuse sub-units other than the 0 th fuse sub-unit. The fuse subunits invert the target bit of the defective memory address and then store the same, so that the fuse subunits can be distinguished from the default value of the fuse group. In this way, the fuse unit 200 can accurately distinguish whether or not each fuse set is used without providing a main fuse, and correctly repair a defective memory address.

In the example of fig. 1, (n+1) ×s=n×s+s fuse resources are required, where S represents the number of redundant addresses. In the example of fig. 2, only n×s fuse resources are needed, so that S fuse resources can be saved. Although the fuse cell according to the embodiment of the present disclosure requires arranging several inverters, the number of inverters required per fuse subunit is small (in the example of m=2, only 6 inverters are required), and the hardware cost and area of the inverters are negligible compared to the saved S fuse resources. Thus, the manner in which fuse cells according to embodiments of the present disclosure cancel the primary fuses through packet repair may significantly reduce the fuse resources that need to be used, thereby saving hardware costs and reducing the area of the memory array.

Embodiments of the present disclosure further contemplate situations where the redundant memory cells themselves may be damaged. If a redundant memory location at a redundant memory address is corrupted, the value of the fuse set associated with the redundant memory address is set to a corrupted indication value. Each bit of the damage indication value is 1. In the event that the value of any fuse set is equal to the damage indication value, the redundant memory address associated with that fuse set is not used to replace the defective memory address of the memory array. In consideration of redundancy damage, the i-th fuse subunit is configured to: a defective memory address where the value of the designated M bit is equal to i and the remaining bits are all 0 is not stored, and a defective memory address where the value of the designated M bit is equal to the inversion of i and the remaining bits are all 1 is not stored. Wherein i is greater than or equal to 0 and less than K. In other words, the i-th fuse subunit refers to each of the K fuse subunits, each of which is subject to the above-described configuration. The value of i may be converted into an M-bit binary number for comparison with the value of the designated M-bit of the defective memory address. In the example where M is equal to 2 and i is equal to 0, the 0 th fuse subunit is configured to not store a defective memory address designating 2 bits as a binary number 00 and the remaining bits as 0, and to not store a defective memory address designating 2 bits as a binary number 11 (an inverse of 00) and the remaining bits as 1. In the example where M is equal to 2 and i is equal to 1, the 1 st fuse subunit is configured to not store a defective memory address designating 2 bits as a binary number 01 and the remaining bits as 0, and to not store a defective memory address designating 2 bits as a binary number 10 (an inverse of 01) and the remaining bits as 1. In the example where M is equal to 2 and i is equal to 2, the 2 nd fuse subunit is configured to not store a defective memory address designating 2 bits as a binary number 10 and the remaining bits as 0, and to not store a defective memory address designating 2 bits as a binary number 01 (the inverse of 10) and the remaining bits as 1. In the example where M is equal to 2 and i is equal to 3, the 3 rd fuse subunit is configured to not store a defective memory address designating 2 bits as a binary number 11 and the remaining bits as 0, and to not store a defective memory address designating 2 bits as a binary number 00 (the inverse of 11) and the remaining bits as 1.

In the case where the value of any fuse group in the jth fuse subunit is equal to the damage instruction value, the output value of the fuse group is set equal to the value of the fuse group. That is, in this case, the target bit of the value of the fuse set is not inverted by the inverter to obtain the output value of the fuse set.

The operation principle of the 4 fuse subunits GP0, GP1, GP2 and GP3 in fig. 2 will be described below with reference to fig. 7 to 10 by taking the example of designating M bits as the lowest 2 bits of the defective memory address. Fig. 7 shows a schematic operation schematic diagram of the 0 th fuse subunit GP0 shown in fig. 2. Fig. 8 shows a schematic operation of the 1 st fuse subunit shown in fig. 2. Fig. 9 shows a schematic operating diagram of the 2 nd fuse subunit shown in fig. 2. Fig. 10 shows a schematic operation of the 3 rd fuse subunit shown in fig. 2.

In the example of fig. 7, the 0 th fuse subunit is configured to not store a defective memory address (i.e., "0000000") whose value of the lowest 2 bits is equal to binary number 00 and whose remaining bits are 0, and to not store a defective memory address (i.e., "1111111") whose value of the lowest 2 bits is equal to binary number 11 and whose remaining bits are 1. In the case where the repair-required address (i.e., the defective memory address) is "0000000", repair is performed by fuse sub-units other than the 0 th fuse sub-unit. Thus, when the intra-fuse address (i.e., the value of the fuse set) is "0000000", it is indicated that the fuse set is not used, and the fuse set is not used to repair the memory array. In the case where the repair required address is "1111111", repair is performed by fuse subunits other than the 0 th fuse subunit. Thus, when the intra-fuse address is "1111111", it is indicated that the redundant memory cell associated with the fuse set is damaged and is not used to repair the memory array. In the case where the repair required address is "XXXXXXX", the "XXXXXXX" may be stored in an unused one of the fuse sets (fuse set having a value of "0000000") in the 0 th fuse subunit. The output value (i.e., output address) of each fuse group in the 0 th fuse subunit is the same as the intra-fuse address. When "XXXXXXX" matches (is identical to) the external access address, the access to "XXXXXXX" is linked to the redundant address associated with the fuse set storing "XXXXXXX". In the example of fig. 7, "XXXXXXX" indicates all values except "0000000" and "1111111".

In the example of fig. 8, the 1 st fuse subunit is configured to not store a defective memory address (i.e., "0000001") whose value of the lowest 2 bits is equal to binary 01 and whose remaining bits are all 0, and to not store a defective memory address (i.e., "1111110") whose value of the lowest 2 bits is equal to binary 10 and whose remaining bits are all 1. The lowest 1 bit of the defective memory address is inverted by an inverter before the defective memory address is stored in the 1 st fuse subunit. In the case where the value of any fuse group in the 1 st fuse subunit is not equal to the default value "0000000" and is not equal to the damage instruction value "1111111", the lowest 1 bit of the value of the fuse group is inverted by the inverter to obtain the output value of the fuse group.

Referring to fig. 8, in the case where the repair required address (i.e., the defective memory address) is "0000001", repair is performed by fuse sub-units other than the 1 st fuse sub-unit. If the lowest 1 bit of "0000001" is inverted by the inverter, "0000000" is obtained. Since the 1 st fuse subunit does not repair address "0000001", when the intra-fuse address (i.e., the value of the fuse set) is "0000000", it is indicated that the fuse set is not used and is not used for repairing the memory array. In the case where the repair required address is "1111110", repair is performed by fuse subunits other than the 1 st fuse subunit. If the least significant 1 bit of "1111110" is inverted by an inverter, then "1111111" is obtained. Since the 1 st fuse subunit does not repair address "1111110", when the intra-fuse address (i.e., the value of the fuse bank) is "1111111", it is indicated that the redundant memory cell associated with the fuse bank is damaged and is not used to repair the memory array. In the case where the repair-required address is "XXXXX", the least significant 1 bit of "XXXXX" is inverted by an inverter, resulting in "XXXXP". Wherein P represents the inverse of X. P equals 1 when X equals 0 and P equals 0 when X equals 1. "XXXXXXP" may be stored in an unused one of the fuse sets in fuse subunit 1 (the fuse set having a value of "0000000"). Before the fuse set storing "XXXXXXP" is read, the lowest 1 bit of "XXXXP" is inverted by an inverter, resulting in "XXXXX". When "XXXXXXX" matches (is identical to) the external access address, the access to "XXXXXXX" is linked to the redundant address associated with the fuse bank storing "XXXXXXP". In the example of fig. 8, "XXXXXXX" indicates all values except "0000001" and "1111110". In the case where the repair required address is "0000000", the lowest 1 bit of "0000000" is inverted by the inverter, resulting in "0000001". "0000001" is stored in an unused one of the 1 st fuse subunits to distinguish from the default value "0000000" of the fuse group. The output address corresponding to "0000001" is "0000000", and therefore, when the external access address is "0000000", the access to "0000000" can be linked to the redundant address associated with the fuse group storing "0000001". In the case where the repair required address is "1111111", the least significant 1 bit of "1111111" is inverted by the inverter, resulting in "1111110". "1111110" is stored in an unused one of the 1 st fuse subunits to distinguish it from the damage indicator "1111111" of the fuse bank. The output address corresponding to "1111110" is "1111111", and thus, when the external access address is "1111111", the access to "1111111" can be linked to the redundant address associated with the fuse set storing "1111110".

In the example of fig. 9, the 2 nd fuse subunit is configured to not store a defective memory address (i.e., "0000010") whose value of the lowest 2 bits is equal to binary number 10 and whose remaining bits are all 0, and to not store a defective memory address (i.e., "1111101") whose value of the lowest 2 bits is equal to binary number 01 and whose remaining bits are all 1. The 2 nd bit of the defective memory address is inverted by an inverter before the defective memory address is stored in the 2 nd fuse subunit. In the case where the value of any fuse group in the 2 nd fuse subunit is not equal to the default value "0000000" and is not equal to the damage instruction value "1111111", the 2 nd bit of the value of the fuse group is inverted by the inverter to obtain the output value of the fuse group.

Referring to fig. 9, in the case where the repair required address (i.e., the defective memory address) is "0000010", repair is performed by fuse sub-units other than the 2 nd fuse sub-unit. If the 2 nd bit of "0000010" is inverted by the inverter, then "0000000" is obtained. Since the 2 nd fuse subunit does not repair the address "0000010", when the intra-fuse address (i.e., the value of the fuse set) is "0000000", it is indicated that the fuse set is not used and is not used for repairing the memory array. In the case where the repair required address is "1111101", repair is performed by fuse subunits other than the 2 nd fuse subunit. If the 2 nd bit of "1111101" is inverted by an inverter, then "1111111" is obtained. Since the 2 nd fuse subunit does not repair address "1111101", when the intra-fuse address (i.e., the value of the fuse bank) is "1111111", it is indicated that the redundant memory cell associated with the fuse bank is damaged and is not used to repair the memory array. In the case where the repair required address is "XXXXX", the 2 nd bit of "XXXXX" is inverted by the inverter, resulting in "XXXXXPX". "XXXXXPX" may be stored in an unused one of the fuse sub-units of the 2 nd fuse (the fuse set having a value of "0000000"). Before the fuse set storing "XXXXXPX" is read, the 2 nd bit of "XXXXXPX" is inverted by an inverter, resulting in "XXXXX". When "XXXXXXX" matches (is identical to) the external access address, the access to "XXXXXXX" is linked to the redundant address associated with the fuse set storing "XXXXXPX". In the example of fig. 9, "XXXXXXX" indicates all values except "0000010" and "1111101". In the case where the repair required address is "0000000", the 2 nd bit of "0000000" is inverted by the inverter, resulting in "0000010". "0000010" is stored in an unused one of the fuse subunits of the 2 nd fuse to be distinguished from the default value "0000000" of the fuse group. The output address corresponding to "0000010" is "0000000", and therefore, when the external access address is "0000000", the access to "0000000" can be linked to the redundant address associated with the fuse group storing "0000010". Under the condition that the repair address is '1111111', the 2 nd bit of '1111111' is inverted by an inverter, and '1111101' is obtained. "1111101" is stored in an unused one of the 2 nd fuse subunits to distinguish it from the damage indicator "1111111" of the fuse bank. The output address corresponding to "1111101" is "1111111", and thus, when the external access address is "1111111", the access to "1111111" can be linked to the redundant address associated with the fuse group storing "1111101".

In the example of fig. 10, the 3 rd fuse subunit is configured to not store a defective memory address (i.e., "0000011") having a value of the lowest 2 bits equal to binary number 11 and the remaining bits are all 0, and to not store a defective memory address (i.e., "1111100") having a value of the lowest 2 bits equal to binary number 00 and the remaining bits are all 1. The lowest 2 bits of the defective memory address are inverted by an inverter before the defective memory address is stored in the 3 rd fuse subunit. In the case where the value of any fuse group in the 3 rd fuse subunit is not equal to the default value "0000000" and is not equal to the damage instruction value "1111111", the lowest 2 bits of the value of the fuse group are inverted by the inverter to obtain the output value of the fuse group.

Referring to fig. 10, in the case where the repair required address (i.e., the defective memory address) is "0000011", repair is performed by fuse sub-units other than the 3 rd fuse sub-unit. If the least significant 2 bits of "0000011" are inverted by an inverter, "0000000" is obtained. Since the 3 rd fuse subunit does not repair address "0000011", when the intra-fuse address (i.e., the value of the fuse bank) is "0000000", this fuse bank is indicated as unused and is not used to repair the memory array. In the case where the repair required address is "1111100", repair is performed by fuse subunits other than the 3 rd fuse subunit. If the least significant 2 bits of "1111100" are inverted by an inverter, then "1111111" is obtained. Since the 3 rd fuse subunit does not repair address "1111100", when the intra-fuse address (i.e., the value of the fuse bank) is "1111111", it is indicated that the redundant memory cell associated with the fuse bank is damaged and is not used to repair the memory array. In the case where the repair required address is "XXXXX", the least significant 2 bits of "XXXXX" are inverted by an inverter, resulting in "XXXXXPP". "XXXXXPP" may be stored in an unused one of the fuse sets in the 3 rd fuse subunit (the fuse set having a value of "0000000"). Before the fuse set storing "XXXXXPP" is read, the lowest 2 bits of "XXXXXPP" are inverted by an inverter, resulting in "XXXXX". When "XXXXXXX" matches (is identical to) the external access address, the access to "XXXXXXX" is linked to the redundant address associated with the fuse set storing "XXXXXPP". In the example of fig. 10, "XXXXXXX" indicates all values except "0000011" and "1111100". In the case where the repair required address is "0000000", the least significant 2 bits of "0000000" are inverted by the inverter, resulting in "0000011". "0000011" is stored into an unused one of the 3 rd fuse subunits to distinguish it from the default value "0000000" of the fuse group. The output address corresponding to "0000011" is "0000000", and therefore, when the external access address is "0000000", an access to "0000000" can be linked to a redundant address associated with the fuse group storing "0000011". In the case where the repair required address is "1111111", the least significant 2 bits of "1111111" are inverted by an inverter, resulting in "1111100". "1111100" is stored in an unused one of the 3 rd fuse subunits to distinguish it from the damage indicator "1111111" of the fuse bank. The output address corresponding to "1111100" is "1111111", and thus, when the external access address is "1111111", the access to "1111111" can be linked to the redundant address associated with the fuse set storing "1111100".

By further configuring the i-th fuse subunit to not store a defective memory address in which the value of the designated M bit is equal to the complement of i and the remaining bits are all 1, the fuse unit 200 can accurately determine whether the redundant memory address associated with the fuse group has been damaged and correctly repair the defective memory address without setting the main fuse.

In some embodiments of the present disclosure, the number of fuse groups in each fuse subunit may be equal. In some alternative embodiments of the present disclosure, the number of fuse groups in each fuse subunit may not be equal.

In some embodiments of the present disclosure, the designated M bits may be consecutive M bits of the defective memory address. For example, the designated M bits are the lowest M bits of the defective memory address. In other embodiments of the present disclosure, the designated M bits may be discontinuous M bits of the defective memory address. Embodiments of the present disclosure do not limit the position of each of the M bits. Furthermore, embodiments of the present disclosure also do not limit the value of M.

Fig. 11 shows a schematic flow chart of a processing method 1100 for processing a fuse unit according to an embodiment of the disclosure.

At block S1102 of fig. 11, a defective memory address of a memory array is received. The defective memory address may be a row address or a column address.

At block S1104, a value of a specified M bit of the defective memory address is acquired as an allocation reference value. Assuming that the designated M bit is the lowest 2 bits, the allocation reference value obtained from the defective memory address "xxxx 00" is 00, the allocation reference value obtained from the defective memory address "xxxx 01" is 01, the allocation reference value obtained from the defective memory address "xxxx 10" is 10, and the allocation reference value obtained from the defective memory address "xxxx 11" is 11.

At block S1106, it is determined whether the remaining bits of the defective memory address are all 0. The remaining bits are bits of the defective memory address other than the designated M bits. If the remaining bits of the defective memory address are all 0 (yes at block S1106), then at block S1108, the defective memory address is stored to an unused one of the p-th fuse sub-units of the K fuse sub-units. Wherein p is not equal to the assigned reference value. In an example in which the M bit is designated as the lowest 2 bits, the defect memory address "0000000" may be stored to any fuse sub-unit other than the 0 th fuse sub-unit, the defect memory address "0000001" may be stored to any fuse sub-unit other than the 1 st fuse sub-unit, the defect memory address "0000010" may be stored to any fuse sub-unit other than the 2 nd fuse sub-unit, and the defect memory address "0000011" may be stored to any fuse sub-unit other than the 3 rd fuse sub-unit.

In embodiments where damage to the redundant memory cells themselves is considered, although not shown, the processing method 1100 shown in FIG. 11 further includes: for each fuse set, the value of the fuse set is set to a corruption indication value in response to the redundant memory address associated with the fuse set being corrupted. Each bit of the damage indication value is 1. In the example of n=7, the damage instruction value is "1111111".

Referring to fig. 11, if the remaining bits of the defective memory address are not all 0 (no at block S1106), it is determined whether the remaining bits of the defective memory address are all 1 at block S1110. If the remaining bits of the defective memory address are all 1 (yes at block S1110), then at block S1112 the defective memory address is stored to an unused one of the q-th fuse sub-units of the K fuse sub-units. Wherein the inverse of q is not equal to the assigned reference value. In an example in which the M bit is designated as the lowest 2 bits, the defect memory address "1111111" may be stored to any fuse sub-unit other than the 0 th fuse sub-unit, the defect memory address "1111110" may be stored to any fuse sub-unit other than the 1 st fuse sub-unit, the defect memory address "1111101" may be stored to any fuse sub-unit other than the 2 nd fuse sub-unit, and the defect memory address "1111100" may be stored to any fuse sub-unit other than the 3 rd fuse sub-unit.

If the remaining bits of the defective memory address are not all 1 (no at block S1110), then at block S1114 the defective memory address is stored to any unused fuse group of the K fuse subunits.

Embodiments of the present disclosure also provide a way of determining the status of individual fuse groups in a fuse cell. Fig. 12 shows a schematic flow chart of a determination process of the states of the respective fuse groups in the fuse unit in an embodiment in which damage to the redundant memory cells themselves is not considered.

At block S1202 of fig. 12, in the case where the storage array is accessed, each fuse set is taken as a target fuse set.

At block S1204, it is determined whether the value of the target fuse set is equal to a default value. If it is determined that the value of the target fuse set is equal to the default value (yes at block S1204), it indicates that the target fuse set is not used, i.e., the redundant memory address corresponding to the target fuse set is not used, and the process returns to block S1202 to continue with the next fuse set as the target fuse set.

If it is determined that the value of the target fuse set is not equal to the default value (no at block S1204), then at block S1206 the access address of the access storage array is compared to the output value of the target fuse set, determining if the access address matches (is identical or equal to) the output value of the target fuse set. If the access address matches the output value of the target fuse set ("yes" at block S1206), then the access to the access address is linked to a redundant memory address associated with the target fuse set at block S1208. If the access address does not match the output value of the target fuse set (no at block S1206), the process returns to block S1202 to continue with the next fuse set as the target fuse set.

Fig. 13 shows a schematic flowchart of a determination process of the states of the respective fuse groups in the fuse unit in consideration of the possibility that the redundant memory cell itself may be damaged.

At block S1302 of fig. 13, in a case where the storage array is accessed, each fuse set is taken as a target fuse set.

At block S1304, it is determined whether the value of the target fuse set is equal to a default value or a damage indication value. If it is determined that the value of the target fuse set is equal to the default value or the damage indication value ("yes" at block S1304), it indicates that the redundant memory address corresponding to the target fuse set is not used or has been damaged, and the process returns to continue with the next fuse set as the target fuse set at block S1302.

If it is determined that the value of the target fuse set is not equal to the default value and is not equal to the damage indication value ("no" at block S1304), then the access address of the access storage array is compared to the output value of the target fuse set at block S1306 to determine whether the access address matches (is identical or equal to) the output value of the target fuse set. If the access address matches the output value of the target fuse set (yes at block S1306), then at block S1308 the access to the access address is linked to a redundant memory address associated with the target fuse set. If the access address does not match the output value of the target fuse set (no at block S1306), the process returns to block S1302 to continue with the next fuse set as the target fuse set.

Fig. 14 shows a schematic block diagram of a memory array 1400 according to an embodiment of the disclosure. The memory array 1400 may include fuse cells 200 as shown in fig. 2. Embodiments of the present disclosure also provide a semiconductor device. The semiconductor device includes a memory array 1400 as shown in fig. 14.

Fig. 15 shows a schematic block diagram of a processing device 1500 according to an embodiment of the disclosure. The processing device 1500 is used to process a fuse unit according to an embodiment of the present disclosure. As shown in fig. 15, the processing device 1500 may include a processor 1510 and a memory 1520 storing a computer program. The computer programs, when executed by the processor 1510, enable the processing device 1500 to perform the steps of the processing methods as shown in fig. 11-13. In one example, the processing apparatus 1500 may be a computer device or a central processor. The processing device 1500 may receive a defective memory address of a memory array. The processing apparatus 1500 may acquire a value of a designated M bit of the defective memory address as an allocation reference value. The processing device 1500 may determine whether the remaining bits of the defective memory address are all 0. The remaining bits are bits of the defective memory address other than the designated M bits. In response to the remaining bits of the defective memory address being all 0, the processing device 1500 may store the defective memory address to an unused one of the p-th fuse sub-units of the K fuse sub-units. Wherein p is not equal to the assigned reference value.

In some embodiments of the present disclosure, in response to the storage array being accessed, processing device 1500 may treat each fuse set as a target fuse set and perform the following operations: determining whether the value of the target fuse set is equal to a default value; in response to the value of the target fuse set not being equal to the default value, comparing the access address of the access storage array with the output value of the target fuse set; and in response to the access address matching the output value of the target fuse set, linking the access to the access address to a redundant memory address associated with the target fuse set.

In some embodiments of the present disclosure, the processing device 1500 may determine whether the remaining bits of the defective memory address are all 1. In response to the remaining bits of the defective memory address being all 1, processing device 1500 may store the defective memory address to an unused one of the q-th fuse subcells of the K fuse subcells. Wherein the inverse of q is not equal to the assigned reference value. For each fuse set, the processing device 1500 may set the value of the fuse set to a corruption indication value in response to the redundant memory address associated with the fuse set being corrupted. Each bit of the damage indication value is 1.

In some embodiments of the present disclosure, in response to the storage array being accessed, processing device 1500 may treat each fuse set as a target fuse set and perform the following operations: determining whether the value of the target fuse set is equal to a default value or a damage indication value; comparing an access address of the access storage array with an output value of the target fuse set in response to the value of the target fuse set not being equal to the default value and not being equal to the damage indication value; and in response to the access address matching the output value of the target fuse set, linking the access to the access address to a redundant memory address associated with the target fuse set.

In an embodiment of the present disclosure, the processor 1510 may be, for example, a Central Processing Unit (CPU), a microprocessor, a Digital Signal Processor (DSP), a processor of a multi-core based processor architecture, or the like. Memory 1520 may be any type of memory implemented using data storage technology including, but not limited to, random access memory, read only memory, semiconductor-based memory, flash memory, disk storage, and the like.

Furthermore, in an embodiment of the present disclosure, the apparatus 1500 may also include an input device 1530 for inputting a defective memory address. Additionally, apparatus 1500 may also include an output device 1540 for outputting output values of the fuse set.

In other embodiments of the present disclosure, there is also provided a computer-readable storage medium storing a computer program, wherein the computer program is capable of implementing the steps of the processing method as shown in fig. 11 to 13 when being executed by a processor.

In summary, by means of packet repair, the fuse unit used in the memory array according to the embodiments of the present disclosure can still repair the memory array normally without the main fuse, so as to reduce the fuse resources required to be used, save the hardware cost, and reduce the area of the memory array. The fuse cells used in the memory array according to the embodiments of the present disclosure can also handle the case where redundant memory cells are damaged, and accurately reflect the states of the respective fuse groups.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A fuse unit for use in a memory array, the fuse unit comprising: k fuse subunits, each fuse subunit comprising a plurality of fuse groups, each fuse group comprising N fuses, K being equal to 2 ^M M is a positive integer, N is equal to the number of bits of the memory address of the memory array,

wherein each fuse bank is capable of storing a defective memory address of the memory array, each fuse bank is associated with a redundant memory address of the memory array, each bit of a default value of each fuse bank is 0, and the redundant memory address associated with the fuse bank is used to replace the defective memory address stored by the fuse bank if the value of the fuse bank is not equal to the default value;

an i-th fuse subunit of the K fuse subunits is configured to not store a defective memory address having a value of a specified M bit equal to i and remaining bits each being 0, wherein i is greater than or equal to 0 and less than K in the defective memory address except the specified M bit;

the j-th fuse subunit of the K fuse subunits further includes a plurality of inverters; the target bit of the defective memory address is inverted by the inverter before the defective memory address is stored in the j-th fuse subunit; in the case that the value of any fuse group in the jth fuse subunit is not equal to the default value, the target bit of the value of the fuse group is inverted by the inverter to obtain an output value of the fuse group, where j is greater than 0 and less than K, and the target bit is a bit corresponding to a bit equal to 1 of j in the specified M bits.

2. A fuse unit as claimed in claim 1, wherein for each fuse bank, in the event of a redundant memory address associated with that fuse bank being corrupted, the value of that fuse bank is set to a corrupted indication value, each bit of the corrupted indication value being 1;

in the event that the value of any fuse set is equal to the damage indication value, the redundant memory address associated with that fuse set is not used to replace the defective memory address of the memory array;

the i-th fuse subunit is further configured to not store a defective memory address for which the value of the specified M bits is equal to the complement of i and the remaining bits are all 1;

in the case where the value of any fuse group in the j-th fuse subunit is equal to the damage instruction value, the output value of the fuse group is set equal to the value of the fuse group.

3. A fuse unit as claimed in claim 1 or claim 2, wherein the number of fuse groups in each fuse subunit is unequal.

4. A fuse unit as claimed in claim 1 or 2, wherein the designated M bits are the lowest M bits of the defective memory address.

5. A fuse unit as claimed in claim 1 or 2, wherein the designated M bits are discrete M bits of the defective memory address.

6. A processing method for processing the fuse unit according to claim 1, characterized in that the processing method comprises:

receiving a defective memory address of the memory array;

acquiring the value of the designated M bit of the defect memory address as an allocation reference value;

determining whether remaining bits of the defective memory address are all 0, the remaining bits being bits of the defective memory address other than the specified M bits; and

in response to the remaining bits of the defective memory address being all 0, the defective memory address is stored to an unused one of the p-th fuse sub-units of the K fuse sub-units, where p is not equal to the assigned reference value, and the unused fuse group has a value equal to a default value, each bit of the default value being 0.

7. The method of processing according to claim 6, further comprising:

in response to the storage array being accessed, taking each fuse set as a target fuse set and performing the following operations:

determining whether the value of the target fuse set is equal to the default value;

in response to the value of the target fuse set not being equal to the default value, comparing an access address to access the storage array with an output value of the target fuse set; and

In response to the access address matching the output value of the target fuse set, an access to the access address is linked to a redundant memory address associated with the target fuse set.

8. The method of processing according to claim 6, further comprising:

determining whether the remaining bits of the defective memory address are all 1;

storing the defective memory address to an unused one of the q-th fuse sub-units of the K fuse sub-units in response to the remaining bits of the defective memory address being all 1, wherein an inverse of q is not equal to the allocation reference value; and

for each fuse set, in response to a redundant memory address corruption associated with the fuse set, the value of the fuse set is set to a corruption indication value, each bit of the corruption indication value being 1.

9. The processing method according to claim 8, characterized in that the processing method further comprises:

determining whether the value of the target fuse set is equal to the default value or the damage indication value;

In response to the value of the target fuse set not being equal to the default value and not being equal to the damage indication value, comparing an access address to access the storage array with an output value of the target fuse set; and

10. A memory array, the memory array comprising: a fuse unit according to any one of claims 1 to 5.