JPS63279347A - Memory device - Google Patents

Abstract

PURPOSE:To improve the overall reliability of a system by checking the detecting history of errors by a flag bit for each word where an error is detected. CONSTITUTION:The flag bits F showing the error correcting or detecting histories are added to memory units A-C for each word. In case the data bit errors excluding the bits F are detected with the units A-C respectively or the bits F are kept turned on, the subflag signals are turned on for each word. At the same time, the bit F of the address is turned on for such a memory unit where the general output is not coincident with each output of the units A-C. Then the output of the memory unit whose subflag signal is not turned on yet is defined as the general output. Thus it is possible to check later the miscorrection of errors even in case those units A-C are once corrected wrong and then to prevent such a case where the wrong data which is unable to detect the miscorrection of a 3-bit error, for example, is delivered as a general output.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a memory device particularly suitable for application to satellite-borne systems.

``Prior art'' In a system composed of N units, the output is determined by the majority decision method (TMR), regardless of the type of abnormality, if the number of abnormal units (K<N/2) or less is abnormal. Because it can be suppressed, it is often used as a redundant configuration in systems that require high reliability. However, since three or more units are required for majority decision, the reliability of the system as a whole is not necessarily higher than that of a standby redundant configuration such as a duplex system. For this reason, several modified TMR methods are being considered, such as reconfiguring the redundant configuration and transitioning to standalone operation or a duplex method when the number of surviving units becomes two or less due to unit failure (IEEE Transac'tion
on Reliability, Vol-R-23
+Ni12 +p66~74, JUNE 197
4).

However, all of these modified TMR systems only consider failure as an abnormality mode of the unit, and treat partial error occurrences in the same way as failures. On the other hand, in satellite onboard memory, bit flips (soft errors) occur due to cosmic rays and heavy particles. The soft error rate caused by cosmic rays is much higher than the hard error rate, and the probability that multiple bits will be erroneous at the same time is much higher than on the ground. However, soft errors themselves can be easily repaired by rewriting the memory, just like on the ground.

When the modified TMR method described above is applied to a satellite-mounted memory device, when the number of surviving units becomes 2 or less, the overall abnormality occurrence probability is dominated by the soft error occurrence rate, and the cylindrical degree is obtained. There was a drawback that there was no In order to alleviate this problem, it is possible to apply a block error detection code to each unit, and if an error is detected in either of the two units, select the output of the other unit. If erroneous error correction is performed in each memory unit (for example, in the 1-error correction 2-error detection method, 3 errors are mistakenly recognized as 1 errors, and thus erroneous correction is performed), when two units are operated in parallel, 3 After an error occurs, even though the outputs of the two units do not match, it is not possible to determine which unit is in error, and even if either unit has normal data, the incorrect data will be output as the overall output. The disadvantage is that there is a greater possibility that it will be selected as In addition, if we try to apply an error correction/detection method with high error detection ability to this, the circuit becomes more complex and the number of check bits required increases, which conversely increases the hardware scale and reduces the reliability. There was a problem with lower back. For this reason, there has been a desire for a redundant unit operation method that can be implemented with a simpler circuit and has large error detection and correction capabilities with a small amount of required check bits.

For example, the present invention can be applied to the modified TMR method, and when it becomes impossible to determine the overall output by majority judgment of a plurality of memory units, that is, when there are only two effective memory units, the probability of abnormal output due to soft error is increased. It is an object of the present invention to provide a memory device that can convert the overall system into a cylindrical structure by suppressing this with a smaller amount of hardware.

"Means for Solving Problems" The present invention provides a memory device having two memory units and one output as a total output, in which the memory unit stores a history of error correction or error detection for each word. If an error is detected in the data bits other than the flag bit in each memory unit, or if the flag bit is ON, the sub-flag signal is turned ON in word units, and the total output and each memory unit are The flag bit of the address of the memory unit whose output does not match is turned ON. The memory unit output for which the sub-flag signal is not turned on is set as the total output.

In this way, in this invention, the history of error detection can be checked using the flag bit for each word in which an error has been detected, so even if incorrect error correction has been performed once in each memory unit, it can be detected after the fact. For example, it is possible to prevent erroneous data from being outputted as a total output due to error correction due to a 3-bit error, resulting in erroneous correction and errors that cannot be detected.

The flag focus required in this invention is because when using a memory with a K-bit/word configuration, it is possible to use surplus bits that become redundant due to a mismatch between the number of bits per word and the number of error correction unit bits. , there is no increase in hardware scale due to the addition of flag bits. Furthermore, if one error correction and two error detection circuits are used for each unit, the system as a whole can detect three errors, so the detection circuit is simpler than the conventional three error detection circuit.

Furthermore, since the flag bit is saved, you can check the data address for which the flag focus is ON at an appropriate time, read out the total output data of that address, and rewrite that data. Data can be repaired. By adding this procedure, it is possible to substantially prevent two or more units of the same address from being mistaken at the same time.

"Example" Embodiments of the invention will be described with reference to the drawings.

FIG. 1 is an example of the block configuration of the memory device of the present invention, FIG. 2 is an example of the internal configuration of the selection circuit 16 in FIG. 1, and FIG. 3 is an example of the internal configuration of the selection circuit 16 in FIG. An inventive memory storage format. Characteristic parts of this embodiment are the OR circuit 15 in FIG. 1, the part surrounded by a broken line in FIG. 2, and the flag bit F in FIG. 3. In this embodiment, as error correction for each memory unit, the data bit length is 10 bits B0 to Be, and the check bit length is 5 bits).
A Co-C4 one-error correction and two-error detection circuit is used, and two 8-bit/word memories are used in parallel for one word of 16 bits, as shown in Part 3.

Data writing of the external input signal S to the memory is performed by the write control circuit 11 shown in FIG.

Data (BO to Bq) is distributed in parallel to each memory unit A to C, and check bits (CO to C4) as shown in FIG.
and flag bit F are added and written into the memory circuit 12. When reading data, data bits (Bo to B9
) and check bits (CO to C4) are input to the 1 error correction 2 error detection circuit 14, and the 1 error correction 2 error detection circuit 14 sends the data bits with 1 error correction to the write control circuit 11. , the correction signal G and the detection signal G are turned on when one error is corrected or two errors are detected. These signals are logically summed with the flag signal F from the read control circuit 13 by the OR circuit 15, and sent to the selection circuit 16 as control signals Ti (i=a, b, c, these are units A, B, C, respectively). (indicates each signal).

As shown in FIG. 2, the selection circuit 16 selects the memory unit by turning on any one of the memory unit selection signals Ma''Mc.

Furthermore, when Ma = Mb = Mc = ON, circuit 2
1, a majority vote is taken, and the result is output as the overall output Q. If any one of Ma=Mc is OFF,
Back of data input Qa to Qc from memory unit, M
The input where i is ON and the sub-flag signal Ti is not ON is selected and output as the overall output Q. In other words, M
The AND of i is ON and Ti is OFF is taken in the circuit 22,
When the output is turned ON, the corresponding Qi is output from the circuit 23.

Further, for data output Qa''Qc from each memory unit that does not match the total output, the corresponding error signal EaxEc is turned ON in the circuit 24.

On the other hand, the write control circuit 1 of each memory unit in FIG.
In 1, a check bit is generated and added to the external input signal S, and the flag pin (F) is written as OFF, but if there is no external input signal S, Ei is set according to the error signal IF,i. When Ei is ON, the flag bit F at that address in the own memory circuit 12 is written as ON, and when Ei is OFF, the flag bit F is turned OFF.
Write as.

As a result, if one error occurs in the specific address data of the memory circuit 12 of each memory unit, error correction data is written to the memory circuit 12, and the flag bit F remains OFF. Furthermore, if two or three errors occur, the flag bit F of that address is turned ON. If a 3 error occurs, an error correction operation is performed by mistake, so although the written correction data is erroneous, the selection circuit 16 sets the sub-flag signal Ti of that memory unit to O.
N, the overall output is selected from other memory unit outputs, and since the address data does not match the selection circuit output Q, the flag bit F is turned ON, and from then on, the flag bit F is not corrected to OFF. As far as possible, even if the error correction circuit 14 of each memory unit does not detect an error in the data at that address, the address data in that memory unit will not be selected and will not be erroneously output.

When an error is detected in the error detection circuit 14 of each memory unit A, B, or C, an error correction operation is performed and written to the error detection data address of the memory circuit 12, and , B, C data output Q
a+Qb and Qc are compared, and if the outputs match, the flag bit F of that data address is turned OFF.

Also, if the total output data Q is stored in the address of the memory unit whose flag bit is ON, and the data outputs Qa, Qb, and Qc of memory units A, B, and C are compared, the outputs match. , the flag bit F of that data address is turned OFF.

The most distinctive feature of this invention is that in the case where there are two normal memory units in the above example, when a 3-bit error occurs, a correction operation is performed as a 1-bit error.
Although an erroneous correction is made, in this invention the flag bit F
is turned on, and subsequently the sub-flag signal Ti of that memory unit is turned on, so there is no possibility that the output of this memory unit will be output as the total output Q. As understood from this description, the present invention is not limited to the modified TMR method, but is applicable to the case where one total output is output from two memory units.

As an error detection circuit, there is also a m-error correction (m+1) error detection circuit that performs a computation correction operation in the case of (m+2) error detection, and the present invention can also be applied when using such an error detection circuit. .

"Effects of the Invention" As explained above, the present invention enables the detection of three errors by using a one-error correction, two-error detection circuit that can be easily implemented in, for example, a satellite-mounted memory device. The probability of erroneous output due to simultaneous error occurrence can be sufficiently suppressed. This not only makes it possible to minimize the hardware scale of the error correction circuit, but also suppresses an increase in check focus for error correction, thereby improving the hardware reliability of the memory device.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a memory device that is an embodiment of the present invention, FIG. 2 is an example of the internal configuration of the selection circuit 1 in FIG. 1 of the present invention, and FIG. 3 is a storage format in the memory of the present invention. It is.

Claims (1)

[Claims] (1) In a memory device that has two memory units and has one output as the total output, flag bits are added to each memory unit in units of words, and each memory unit has a flag bit added to it in unit word bits. means for detecting errors in data bits other than flag bits, and means for turning on sub-flag signals in units of words when an error is detected by the error detecting means or when the flag bits are ON; means for turning on a flag bit of a word address of a memory unit whose output does not match the output of each memory unit; and means for setting the output of a memory unit for which the sub-flag signal is not turned on as the overall output. memory device.