WO1998029814A1 - Ic card - Google Patents

Ic card Download PDF

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Publication number
WO1998029814A1
WO1998029814A1 PCT/JP1997/004691 JP9704691W WO9829814A1 WO 1998029814 A1 WO1998029814 A1 WO 1998029814A1 JP 9704691 W JP9704691 W JP 9704691W WO 9829814 A1 WO9829814 A1 WO 9829814A1
Authority
WO
WIPO (PCT)
Prior art keywords
error
data
data stored
storage means
spare
Prior art date
Application number
PCT/JP1997/004691
Other languages
French (fr)
Japanese (ja)
Inventor
Yoshihiro Ikefuji
Shigemi Chimura
Haruo Taguchi
Original Assignee
Rohm Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP34822596A external-priority patent/JPH10187550A/en
Priority claimed from JP8348226A external-priority patent/JPH10187551A/en
Application filed by Rohm Co., Ltd. filed Critical Rohm Co., Ltd.
Priority to AU78928/98A priority Critical patent/AU7892898A/en
Publication of WO1998029814A1 publication Critical patent/WO1998029814A1/en

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Classifications

    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07FCOIN-FREED OR LIKE APPARATUS
    • G07F7/00Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06QINFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00Payment architectures, schemes or protocols
    • G06Q20/30Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06QINFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00Payment architectures, schemes or protocols
    • G06Q20/30Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/357Cards having a plurality of specified features
    • G06Q20/3576Multiple memory zones on card
    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07FCOIN-FREED OR LIKE APPARATUS
    • G07F7/00Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0806Details of the card
    • G07F7/0833Card having specific functional components
    • G07F7/084Additional components relating to data transfer and storing, e.g. error detection, self-diagnosis
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/74Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies

Definitions

  • the present invention relates to an IC card, and more particularly, to an IC card that has a built-in nonvolatile memory for storing various data and that exchanges data with a control unit called an interrogator. . Background art
  • the ⁇ is a device that obtains power from radio waves transmitted from an antenna and transmits information stored in a nonvolatile memory inside it. It is used for ski lift lifts, railway ticket gates, and sorting of luggage. It's being used.
  • the IC force is structurally vulnerable to external stress, and the data stored in the non-volatile memory may change due to static electricity or the like. is there. Conventionally, such a change in data cannot be detected as an error in the non-volatile memory of the IC card, and moreover, error correction of the data and the like cannot be performed. Disclosure of the invention
  • a main object of the present invention is to provide an IC card which has a built-in spare nonvolatile memory and can cope with a data error.
  • Another object of the present invention is to provide an IC card capable of detecting an error in data stored when a nonvolatile memory is not operating.
  • the present invention relates to an IC card for exchanging data by interrogating with an interrogator, a non-volatile storage circuit for storing data given from the interrogator, and a pair of data stored in the non-volatile storage circuit. Spare to store data that can be handled by 1 And a non-volatile memory circuit.
  • an error detection circuit for detecting an error in data stored in the nonvolatile storage circuit, and a non-volatile memory in response to no error being detected by the error detection circuit.
  • a selection circuit for selecting data stored in the storage circuit and selecting data stored in the spare nonvolatile storage circuit in response to detection of an error.
  • an error detection circuit for detecting an error of data stored in the spare nonvolatile memory circuit, and a spare nonvolatile memory circuit in response to no error being detected.
  • a selection circuit for selecting stored data and selecting data stored in the nonvolatile storage circuit in response to detection of an error.
  • Two or more spare nonvolatile memory circuits are provided, and a majority decision is made between the data stored in the nonvolatile memory circuit and the data stored in each of the two or more spare nonvolatile memory circuits.
  • a selection circuit for selecting data stored in the non-volatile storage circuit indicated by the majority decision.
  • the non-volatile storage circuit and the spare non-volatile storage circuit are configured such that physical addresses for storing the same data are different. Further, the nonvolatile storage circuit and the spare nonvolatile storage circuit have different storage capacities.
  • the error detection circuit performs an error detection for each byte or a plurality of bytes, and a detection result of the error detection circuit is stored in a nonvolatile storage circuit. Then, the data error is corrected based on the error detection result.
  • an IC card for exchanging data with an interrogator comprising: a nonvolatile memory circuit for storing data from the interrogator; and a nonvolatile memory when the nonvolatile memory circuit is not selected.
  • An error detection circuit for detecting an error in the data stored in the storage circuit.
  • the embodiment of the present invention includes a spare nonvolatile memory circuit that stores the same data as the data stored in the nonvolatile memory circuit or data that can be corresponded one-to-one. Detects an error in data stored in the storage circuit or the non-volatile storage circuit for backup. Then, based on the error detection result, the error detection circuit stores the data stored in the nonvolatile storage circuit or the spare nonvolatile storage circuit. Data. BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a block diagram showing an embodiment of the present invention.
  • FIG. 2 is a block diagram showing an example of the error detection circuit shown in FIG.
  • FIG. 3 is a block diagram showing another embodiment of the present invention.
  • FIG. 4 is a diagram showing an embodiment in which the physical locations for storing data in the main memory 10 and the sub memory 11 are changed.
  • FIG. 5 is a diagram showing a sequence of an interrogator and an IC card according to still another embodiment of the present invention.
  • FIG. 6 is a flowchart for explaining the operation of still another embodiment of the present invention.
  • FIG. 1 is a block diagram showing an embodiment of the present invention. I C force shown in Fig. 1
  • a tuning circuit 1 composed of a coil L and a capacitor C tunes to a modulation signal sent from an interrogator (not shown), and supplies the sent carrier to a rectifier circuit 2.
  • the rectifier circuit 2 rectifies the carrier and supplies a voltage to each part as a DC power supply.
  • the tuning circuit 1 supplies the modulation signal to the amplification / demodulation unit 3, and the amplification / demodulation unit 3 demodulates data from the modulation signal. Since the demodulated output data is sent serially, it is converted into parallel data by the S / P converter 5 and given to the main controller 7.
  • the main control unit 7 When returning a response to the interrogator, the main control unit 7 uses non-volatile storage means; the data from the main memory 10 of r is supplied to the PZS converter 6 to be converted into serial data, and the serial data is modulated and amplified.
  • the modulation and amplification section 4 amplifies the data and modulates when the unmodulated wave is supplied to the tuning circuit 1.
  • the main control unit 7 The main memory 10 and the sub-memory 11 as spare nonvolatile storage means are connected via selectors 8 and 9.
  • main memory 10 and the sub memory 11 for example, an E 2 ROM, a flash memory, a ferroelectric memory, or the like is used.
  • the sub-memory 11 is used as a backup of the main memory 10 and writes data that can correspond to the main memory 10 on a one-to-one basis.
  • Error detection circuits 12 and 13 are provided to detect errors in the data written corresponding to the main memory 10 and the sub memory 11 respectively.
  • a parity check circuit, a CRC check circuit, and the like are used. Further, when an error is detected by the error detection circuits 12 and 13, error correction circuits 16 and 17 are provided to correct the error.
  • the tuning circuit 1 tunes to the modulation signal, the data is demodulated by the amplification / demodulation unit 3, and the serial data is converted to parallel data by the S / P conversion unit 5. And is given to the main control unit 7.
  • the main controller 7 stores the data in the main memory 10 and the sub memory 11 via the selectors 8 and 9.
  • the error detection circuits 12 and 13 detect whether there is an error in the data stored in the main memory 10 and the sub memory 11 respectively. If there is no error in the main memory 10, the error detection circuit 12 controls the selector 8 so that data is read from the main memory 10 to the main control unit 7, and the sub memory 11 reads data.
  • the selector 9 is controlled so that is not read.
  • the error detection circuit 12 detects that there is a data error in the main memory 10, it controls the selector 8 so that data is not read from the main memory 10, and the data is read from the sub memory 11. Control the selector 9 so that it is read.
  • the error detection circuit 13 detects whether there is an error in the data stored in the sub memory 11. If there is an error in data not only in the main memory 10 but also in the sub memory 11, data is not supplied from the main memory 10 and the sub memory 11 to the main controller 7. In this case, the main control unit 7 re-requests data transmission to the interrogator or specifies that there is an error in the data. After reading data from the main memory 10 or the sub memory 11, the error correction circuits 16 and 17 correct data errors. Note that the error detection circuit 13 is omitted, and the main memory Only the error detection of the data of the data 10 may be performed.
  • FIG. 2 is a block diagram showing an example of the error detection circuit shown in FIG.
  • the error detection circuit 12 shown in FIG. 2 performs a CRC check, and includes a 5-bit shift register 121, a 7-bit shift register 122, and a 4-bit shift register 123. These are serially connected by EXOR gates 124, 125, and 126.
  • FIG. 3 is a block diagram showing another embodiment of the present invention, and does not show a circuit between the tuning circuit 1 and the SZP converter 5 and the PZS converter 6 shown in FIG.
  • a sub memory 14 is further provided in addition to the main memory 10 and the sub memory 11, and the majority decision of the data stored in the main memory 10 and the sub memories 11 and 14 is performed by a majority circuit.
  • step 15 it is determined whether the data stored in the main memory 10 or the sub memory 11 is correct, and the selectors 8 and 9 are switched accordingly.
  • FIG. 4 is a diagram showing an embodiment in which the physical locations for storing data in the main memory 10 and the sub memory 11 are changed. In this way, by changing the physical location where data is stored, even if the data changes due to stress applied to the IC card, the data storage location is not close, The probability that such data remains normal will increase.
  • the provision of the sub-memory 11 greatly enhances the resistance to data changes and errors due to externally applied forces such as stress and static electricity, and increases the reliability of the nonvolatile memory block. Can be enhanced.
  • the content of the memory having the error may be corrected.
  • the main memory 10 and the sub-memory 11 store the same data.
  • the main memory 12 has the information of a certain data value Q
  • the sub-memory has the information of the reciprocal of Q. You can.
  • any data such as a complement can be applied as long as the data can correspond one-to-one.
  • the sub memory 11 may be a memory having a different capacity from the main memory 10. Further, the error detection by the error detection circuits 12 and 13 is performed for one or more bytes. It is better to do it every time. Further, the result of the error detection may be stored in either the main memory 10 or the sub memory 11.
  • FIG. 5 is a diagram for explaining the operation of still another embodiment of the present invention
  • FIG. 6 is a flowchart for explaining the operation of still another embodiment of the present invention.
  • FIGS. 1, 2, 5, and 6 the operation of still another embodiment of the present invention will be described. I.
  • Fig. 5 when the card is activated, data is transmitted from the interrogator, which is recognized by the main control unit 7, and the main control unit 7 exchanges data with the interrogator when The main memory 10 and the sub memory 11 are not operating. Therefore, in the embodiment of the present invention, error detection of data stored in the main memory 10 and sub-memory 11 and correction of data are performed during this period.
  • the main control unit 7 determines whether or not data is being exchanged. If the data is being exchanged, the main controller 7 does not perform the memory error detection operation. The main control unit 7 performs error detection unless data is being exchanged, and records the detection result in the main memory 10 or the sub memory 11. This allows you to deal with multiple errors. The main control unit 7 determines whether error detection has been performed for all bytes of the main memory 10 or the sub memory 11 and performs error detection for all bytes. If no error is detected, the main control unit 7 ends the error detection operation and waits for data exchange with the interrogator.
  • the main control unit 7 determines whether to exchange data with the interrogator, and corrects the data if it is not operating. Do. Then, it is determined whether or not the data has been corrected for all errors. If the actual program is running during the process, the correction result is stored, and a series of operations is completed.
  • the present invention when data is not exchanged with the interrogator at the time of activation, data error detection is performed.
  • the present invention is not limited to this. It is also possible to perform error detection and correction of data in the main memory 10 or the sub memory 11 during a period in which only exchange is performed. Further, in the above-described embodiment, the present invention is applied to a non-contact type IC card, but may be applied to a contact type IC card.
  • the present invention by adding a spare nonvolatile memory, it is possible to increase the reliability against data changes and errors due to externally applied forces such as stress and static electricity, and to improve the reliability of the nonvolatile memory. Errors in data stored during operation can be detected, and a highly reliable Ic card can be provided.

Abstract

A sub-memory (11) is provided in addition to a main memory (10) so as to store data from a main control section (7) in the main memory (10) and the sub-memory (11), and error detecting circuits (12 and 13) respectively detect the errors of the data stored in the memories (10 and 11) and control selectors (8 and 9) so that data can be read out from the error-free memories.

Description

明細書  Specification
I cカード 技術の分野 Field of Ic card technology
この発明は I Cカードに関し、 特に、 各種データを記憶するための不揮発性メ モリを内蔵していて、 質問器と称される制御部との問でデータのやり取りを行な うような I Cカードに関する。 背景技術  The present invention relates to an IC card, and more particularly, to an IC card that has a built-in nonvolatile memory for storing various data and that exchanges data with a control unit called an interrogator. . Background art
I Cカードには、 端子を制御部に電気的に接続してデータのやり取りを行なう ものと、 非接触でデータのやり取りを行なうものがある。 この非接触式の I C力 There are IC cards that exchange data by electrically connecting terminals to the control unit, and IC cards that exchange data without contact. This non-contact I C force
—ドは、 アンテナから送信されてくる電波から電力を得て、 内部の不揮発性メモ リに記憶している情報を送信するものであり、 スキー場のリフトゃ鉄道の改札や 荷物の仕分けなどに利用されている。 The ド is a device that obtains power from radio waves transmitted from an antenna and transmits information stored in a nonvolatile memory inside it. It is used for ski lift lifts, railway ticket gates, and sorting of luggage. It's being used.
上述の接触式, 非接触式を問わず、 I C力一ドはその構造上外部からの応力に 弱く、 静電気などによって不揷発性メモリに記憶しているデータが変化してしま う可能性がある。 従来は、 I cカードの不揮発性メモリでは、 そのようなデータ の変化を誤りとして検知することができず、 ましてやデータの誤り訂正などを行 なうことができなかった。 発明の開示  Regardless of the contact type and non-contact type described above, the IC force is structurally vulnerable to external stress, and the data stored in the non-volatile memory may change due to static electricity or the like. is there. Conventionally, such a change in data cannot be detected as an error in the non-volatile memory of the IC card, and moreover, error correction of the data and the like cannot be performed. Disclosure of the invention
それゆえに、 この発明の主たる目的は、 予備用の不揮発性メモリを内蔵して、 データの誤りに対応できるような I Cカードを提供することである。  Therefore, a main object of the present invention is to provide an IC card which has a built-in spare nonvolatile memory and can cope with a data error.
この発明の他の目的は、 不揮発性メモリの非動作時に記憶しているデータの誤 りを検出できるような I Cカードを提供することである。  Another object of the present invention is to provide an IC card capable of detecting an error in data stored when a nonvolatile memory is not operating.
この発明は、 質問器との問でデータのやり取りを行なう I Cカードにおいて、 質問器から与えられるデータを記憶するための不揮発性記憶回路と、 不揮発性記 憶回路に記憶されているデータと 1対 1で対応を行なえるデータを記憶する予備 用不揮発性記憶回路とを含む。 The present invention relates to an IC card for exchanging data by interrogating with an interrogator, a non-volatile storage circuit for storing data given from the interrogator, and a pair of data stored in the non-volatile storage circuit. Spare to store data that can be handled by 1 And a non-volatile memory circuit.
この発明の好ましい実施例では、 さらに、 不揮発性記憶回路に記憶されている データの誤りを検出する誤り検出回路と、 誤り検出回路によつて誤りが検出され 'なかったことに応じて、 不揮発性記憶回路に記憶されているデ一タを選択し、 誤 りが検出されたことに応じて予備用不揮発性記憶回路に記憶されているデータを 選択する選択回路とを含む。  According to a preferred embodiment of the present invention, there is further provided an error detection circuit for detecting an error in data stored in the nonvolatile storage circuit, and a non-volatile memory in response to no error being detected by the error detection circuit. A selection circuit for selecting data stored in the storage circuit and selecting data stored in the spare nonvolatile storage circuit in response to detection of an error.
この発明のより好ましい実施例では、 さらに予備用不揮発性記憶回路に記憶さ れているデータの誤りを検出する誤り検出回路と、 誤りが検出されなかつたこと に応じて予備用不揮発性記憶回路に記憶されているデータを選択し、 誤りが検出 されたことに応じて不揮発性記憶回路に記憶されているデータを選択する選択回 路とを含む。 予備用不揮発性記憶回路は 2個以上設けられていて、 不揮発性記憶 回路に記憶されているデータと 2個以上の予備用不揮発性記憶回路のそれぞれに 記憶されているデータとの内容の多数決をとるための多数決回路と、 多数決の示 された不揮発性記憶回路に記憶されているデータを選択するための選択回路とを 含む。  In a more preferred embodiment of the present invention, an error detection circuit for detecting an error of data stored in the spare nonvolatile memory circuit, and a spare nonvolatile memory circuit in response to no error being detected. A selection circuit for selecting stored data and selecting data stored in the nonvolatile storage circuit in response to detection of an error. Two or more spare nonvolatile memory circuits are provided, and a majority decision is made between the data stored in the nonvolatile memory circuit and the data stored in each of the two or more spare nonvolatile memory circuits. And a selection circuit for selecting data stored in the non-volatile storage circuit indicated by the majority decision.
不揮発性記憶回路と予備用不揮発性記憶回路は同一のデータを格納する物理的 アドレスが異なるように構成される。 また、 不揮発性記憶回路と予備用不揮発性 記憶回路はそれぞれの記憶容量が異なる。 誤り検出回路は 1バイ トまたは複数バ ィ ト毎に誤り検出を行ない、 誤り検出回路の検出結果は不揮発性記憶回路に記憶 される。 そして、 その誤り検出結果に基づいてデータの誤りが訂正される。 この発明の他の局面は、 質問器との間でデータのやり取りを行なう I C力一ド において、 質問器からのデータを記憶する不揮発性記憶回路と、 不揮発性記憶回 路の非選択時に不揮発性記憶回路に記憶しているデータの誤りを検出する誤り検 出回路とを備えて構成される。  The non-volatile storage circuit and the spare non-volatile storage circuit are configured such that physical addresses for storing the same data are different. Further, the nonvolatile storage circuit and the spare nonvolatile storage circuit have different storage capacities. The error detection circuit performs an error detection for each byte or a plurality of bytes, and a detection result of the error detection circuit is stored in a nonvolatile storage circuit. Then, the data error is corrected based on the error detection result. According to another aspect of the present invention, there is provided an IC card for exchanging data with an interrogator, comprising: a nonvolatile memory circuit for storing data from the interrogator; and a nonvolatile memory when the nonvolatile memory circuit is not selected. An error detection circuit for detecting an error in the data stored in the storage circuit.
この発明の実施例では、 不揮発性記憶回路に記憶されているデータと同じデー タまたは 1対 1に対応が行なえるデータを記憶する予備用不揮発性記憶回路を含 み、 誤り検出回路は不揮発性記憶回路または予備用不揮発性記憶回路に記憶され ているデータの誤りを検出する。 そして、 誤り検出回路は、 その誤り検出結果に 基づいて、 不揮発性記憶回路または予備用不揮発性記憶回路に記憶しているデ一 タを補正する。 図面の簡単な説明 The embodiment of the present invention includes a spare nonvolatile memory circuit that stores the same data as the data stored in the nonvolatile memory circuit or data that can be corresponded one-to-one. Detects an error in data stored in the storage circuit or the non-volatile storage circuit for backup. Then, based on the error detection result, the error detection circuit stores the data stored in the nonvolatile storage circuit or the spare nonvolatile storage circuit. Data. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 この発明の一実施形態を示すプロック図である。  FIG. 1 is a block diagram showing an embodiment of the present invention.
図 2は、 図 1に示した誤り検出回路の一例を示すブロック図である。  FIG. 2 is a block diagram showing an example of the error detection circuit shown in FIG.
図 3は、 この発明の他の実施形態を示すプロック図である。  FIG. 3 is a block diagram showing another embodiment of the present invention.
図 4は、 メインメモリ 1 0とサブメモリ 1 1のデータを格納する物理的な場所 を変えるようにした実施形態を示す図である。  FIG. 4 is a diagram showing an embodiment in which the physical locations for storing data in the main memory 10 and the sub memory 11 are changed.
図 5は、 この発明のさらに他の実施例の質問器と I Cカードのシーケンスを示 す図である。  FIG. 5 is a diagram showing a sequence of an interrogator and an IC card according to still another embodiment of the present invention.
図 6は、 この発明のさらに他の実施例の動作を説明するためのフローチヤ一ト である。 発明を実施するための最良の形態  FIG. 6 is a flowchart for explaining the operation of still another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
図 1はこの発明の一実施例を示すプロック図である。 この図 1に示した I C力 FIG. 1 is a block diagram showing an embodiment of the present invention. I C force shown in Fig. 1
―ドは、 データの送受および非接触式カードへの電力の供給を 1つの周波数の信 号で行なう信号重畳方式を例にとつて説明するが、 データの送受と電力供給を 別々の周波数の信号を使用して行なう信号分離方式の I cカードであってもよレ、。 図 1において、 コイル Lとコンデンサ Cとからなる同調回路 1は質問器 (図示 せず) から送られて来る変調信号に同調し、 送られて来るキャリアを整流回路 2 に与える。 整流回路 2はそのキャリアを整流し、 直流電源として各部に電圧を供 給する。 また、 同調回路 1は変調信号が送られて来たときには、 その変調信号を 増幅復調部 3に与え、 増幅復調部 3はその変調信号からデータを復調する。 この 復調出力のデータはシリアルに送られて来ているので、 S / P変換部 5によって パラレルなデータに変換されて、 主制御部 7に与えられる。 The following describes an example of a signal superimposition method in which data transmission and reception and power supply to the contactless card are performed using a single frequency signal.However, data transmission and reception and power supply are performed using different frequency signals. A signal separation type IC card may be used. In FIG. 1, a tuning circuit 1 composed of a coil L and a capacitor C tunes to a modulation signal sent from an interrogator (not shown), and supplies the sent carrier to a rectifier circuit 2. The rectifier circuit 2 rectifies the carrier and supplies a voltage to each part as a DC power supply. When a modulation signal is sent, the tuning circuit 1 supplies the modulation signal to the amplification / demodulation unit 3, and the amplification / demodulation unit 3 demodulates data from the modulation signal. Since the demodulated output data is sent serially, it is converted into parallel data by the S / P converter 5 and given to the main controller 7.
また、 主制御部 7は質問器へ応答を返すときには、 不揮発性記憶手段とし; rの メインメモリ 1 0からのデータを P Z S変換器 6に与えてシリアルデータに変換 し、 シリアルデータを変調増幅部 4に与え、 変調増幅部 4はそのデータを増幅し かつ同調回路 1に無変調波が与えられたときに変調する。 さらに、 主制御部 7に は、 セレクタ 8, 9を介してメインメモリ 1 0と予備用不揮発性記憶手段として のサブメモリ 1 1とが接続される。 When returning a response to the interrogator, the main control unit 7 uses non-volatile storage means; the data from the main memory 10 of r is supplied to the PZS converter 6 to be converted into serial data, and the serial data is modulated and amplified. The modulation and amplification section 4 amplifies the data and modulates when the unmodulated wave is supplied to the tuning circuit 1. In addition, the main control unit 7 The main memory 10 and the sub-memory 11 as spare nonvolatile storage means are connected via selectors 8 and 9.
メインメモリ 1 0とサブメモリ 1 1はたとえば E 2 R O Mやフラッシュメモリ や強誘電体メモリなどが用いられる。 サブメモリ 1 1はメインメモリ 1 0のバッ クアップ用として用いられ、 メインメモリ 1 0と 1対 1で対応できるデータを書 込む。 メインメモリ 1 0とサブメモリ 1 1のそれぞれに対応して書込んだデータ の誤りを検出するために誤り検出回路 1 2, 1 3が設けられる。 誤り検出回路 1 2, 1 3としてはパリティチェック回路や C R Cチェック回路などが用いられる。 さらに、 誤り検出回路 1 2 , 1 3によって誤りが検出されたとき、 その誤りを補 正するために、 誤り補正回路 1 6, 1 7が設けられる。 As the main memory 10 and the sub memory 11, for example, an E 2 ROM, a flash memory, a ferroelectric memory, or the like is used. The sub-memory 11 is used as a backup of the main memory 10 and writes data that can correspond to the main memory 10 on a one-to-one basis. Error detection circuits 12 and 13 are provided to detect errors in the data written corresponding to the main memory 10 and the sub memory 11 respectively. As the error detection circuits 12 and 13, a parity check circuit, a CRC check circuit, and the like are used. Further, when an error is detected by the error detection circuits 12 and 13, error correction circuits 16 and 17 are provided to correct the error.
質問器からデータが変調信号として送信されると、 同調回路 1がその変調信号 に同調し、 増幅復調部 3によってデータが復調され、 シリアルなデータが S / P 変換部 5によってパラレルなデータに変換され、 主制御部 7に与えられる。 主制 御部 7はそのデータを、 セレクタ 8, 9を介してメインメモリ 1 0とサブメモリ 1 1に記憶させる。 誤り検出回路 1 2, 1 3はそれぞれメインメモリ 1 0とサブ メモリ 1 1に記憶されているデータに誤りがあるか否かを検出する。 誤り検出回 路 1 2はメインメモリ 1 0に誤りがなければ、 セレクタ 8によってメインメモリ 1 0からデータが主制御部 7に読出されるように制御し、 サブメモリ 1 1力ゝらデ —タが読出されないようにセレクタ 9を制御する。  When data is transmitted as a modulation signal from the interrogator, the tuning circuit 1 tunes to the modulation signal, the data is demodulated by the amplification / demodulation unit 3, and the serial data is converted to parallel data by the S / P conversion unit 5. And is given to the main control unit 7. The main controller 7 stores the data in the main memory 10 and the sub memory 11 via the selectors 8 and 9. The error detection circuits 12 and 13 detect whether there is an error in the data stored in the main memory 10 and the sub memory 11 respectively. If there is no error in the main memory 10, the error detection circuit 12 controls the selector 8 so that data is read from the main memory 10 to the main control unit 7, and the sub memory 11 reads data. The selector 9 is controlled so that is not read.
誤り検出回路 1 2は、 もしメインメモリ 1 0にデータの誤りがあることを検出 した場合には、 メインメモリ 1 0からデータが読出されないようにセレクタ 8を 制御し、 サブメモリ 1 1からデータが読出されるようにセレクタ 9を制御する。 誤り検出回路 1 3はサブメモリ 1 1に記憶したデータに誤りがあるかを検出する。 もし、 メインメモリ 1 0のみならずサブメモリ 1 1にもデータの誤りがあれば、 メインメモリ 1 0およびサブメモリ 1 1からデータが主制御部 7に与えられない。 この場合、 主制御部 7は質問器に対してデータの送信を再要求するまたはデータ に誤りがあることを明示することになる。 メインメモリ 1 0またはサブメモリ 1 1からデータを読出した後、 誤り補正回路 1 6, 1 7はデータの誤りを補正する。 なお、 誤り検出回路 1 3を省略し、 誤り検出回路 1 2のみによってメインメモ リ 1 0のデータの誤りの検出のみを行なうようにしてもよい。 If the error detection circuit 12 detects that there is a data error in the main memory 10, it controls the selector 8 so that data is not read from the main memory 10, and the data is read from the sub memory 11. Control the selector 9 so that it is read. The error detection circuit 13 detects whether there is an error in the data stored in the sub memory 11. If there is an error in data not only in the main memory 10 but also in the sub memory 11, data is not supplied from the main memory 10 and the sub memory 11 to the main controller 7. In this case, the main control unit 7 re-requests data transmission to the interrogator or specifies that there is an error in the data. After reading data from the main memory 10 or the sub memory 11, the error correction circuits 16 and 17 correct data errors. Note that the error detection circuit 13 is omitted, and the main memory Only the error detection of the data of the data 10 may be performed.
図 2は図 1に示した誤り検出回路の一例を示すプロック図である。 この図 2に 示した誤り検出回路 1 2は C R Cチェックを行なうものであり、 5ビッ 卜のシフ トレジスタ 1 2 1 と 7ビットのシフトレジスタ 1 2 2と 4ビッ トのシフトレジス タ 1 2 3を、 E X O Rゲート 1 2 4, 1 2 5 , 1 2 6によってシリアルに接続し たものである。  FIG. 2 is a block diagram showing an example of the error detection circuit shown in FIG. The error detection circuit 12 shown in FIG. 2 performs a CRC check, and includes a 5-bit shift register 121, a 7-bit shift register 122, and a 4-bit shift register 123. These are serially connected by EXOR gates 124, 125, and 126.
図 3はこの発明の他の実施形態を示すブロック図であり、 図 1に示した同調回 路 1から S Z P変換部 5と P Z S変換部 6との問の回路の図示を省略している。 この実施形態は、 メインメモリ 1 0とサブメモリ 1 1の他にさらにサブメモリ 1 4を設け、 これらのメインメモリ 1 0とサブメモリ 1 1および 1 4に記憶したデ —タの多数決を多数決回路 1 5でとり、 メインメモリ 1 0とサブメモリ 1 1のい ずれに記憶したデータが正しいかを判断し、 それによつてセレクタ 8 , 9を切換 えるようにしたものである。  FIG. 3 is a block diagram showing another embodiment of the present invention, and does not show a circuit between the tuning circuit 1 and the SZP converter 5 and the PZS converter 6 shown in FIG. In this embodiment, a sub memory 14 is further provided in addition to the main memory 10 and the sub memory 11, and the majority decision of the data stored in the main memory 10 and the sub memories 11 and 14 is performed by a majority circuit. In step 15, it is determined whether the data stored in the main memory 10 or the sub memory 11 is correct, and the selectors 8 and 9 are switched accordingly.
図 4はメインメモリ 1 0とサブメモリ 1 1のデータを格納する物理的な場所を 変えるようにした実施形態を示す図である。 このように、 データを格納する物理 的な場所を変えることにより、 I Cカードに応力が加えられたことによるデータ の変化が起きてしまった場合でも、 データ格納場所が近い場所でないため、 どち らかのデータが正常で残る確率が高くなる。  FIG. 4 is a diagram showing an embodiment in which the physical locations for storing data in the main memory 10 and the sub memory 11 are changed. In this way, by changing the physical location where data is stored, even if the data changes due to stress applied to the IC card, the data storage location is not close, The probability that such data remains normal will increase.
上述の如く、 サブメモリ 1 1を設けたことによって、 応力や静電気などの外部 から加えられる力によるデータの変化や誤りへの耐性も非常に高めることができ、 不揮発性記憶プロックとしての信頼性を高めることができる。  As described above, the provision of the sub-memory 11 greatly enhances the resistance to data changes and errors due to externally applied forces such as stress and static electricity, and increases the reliability of the nonvolatile memory block. Can be enhanced.
なお、 メインメモリ 1 0とサブメモリ 1 1のいずれか一方のデータが正しいと 判断した場合、 誤りがある方のメモリの内容を補正するようにしてもよい。  When it is determined that one of the data in the main memory 10 and the data in the sub memory 11 is correct, the content of the memory having the error may be corrected.
また、 メインメモリ 1 0とサブメモリ 1 1は同じデータを記憶するようにした 、 メインメモリ 1 2はあるデータ値 Qという情報を持たせ、 サブメモリには Q の逆数という情報を持たせるようにしてもよレ、。 その他、 1対 1に対応が行なえ るデ一タであれば補数のようなどのようなデータであっても適用できる。  The main memory 10 and the sub-memory 11 store the same data.The main memory 12 has the information of a certain data value Q, and the sub-memory has the information of the reciprocal of Q. You can. In addition, any data such as a complement can be applied as long as the data can correspond one-to-one.
さらに、 サブメモリ 1 1はメインメモリ 1 0と異なる容量のメモリであっても よレ、。 さらに、 誤り検出回路 1 2, 1 3による誤り検出は 1バイ トまたは複数バ ィ ト毎に行なうようにすればよレ、。 さらに、 誤り検出の結果をメインメモリ 1 0 またはサブメモリ 1 1のいずれかに記憶させるようにしてもよい。 Further, the sub memory 11 may be a memory having a different capacity from the main memory 10. Further, the error detection by the error detection circuits 12 and 13 is performed for one or more bytes. It is better to do it every time. Further, the result of the error detection may be stored in either the main memory 10 or the sub memory 11.
図 5はこの発明のさらに他の実施例の動作を説明するための図であり、 図 6は この発明のさらに他の実施例の動作を説明するためのフローチャートである。 次に、 図 1, 図 2, 図 5および図 6を参照して、 この発明のさらに他の実施例 の動作について説明する。 I。カードは、 図 5に示すように、 起動時は質問器か らデータが送信され、 それを主制御部 7が認識しており、 その問は主制御部 7は 質問器とデータのやりとりを行なっておらず、 メインメモリ 1 0, サブメモリ 1 1も非動作となっている。 そこで、 この発明の実施例では、 この期間内にメイン メモリ 1 0とサブメモリ 1 1に記憶しているデータの誤り検出およびデータの補 正を行なう。  FIG. 5 is a diagram for explaining the operation of still another embodiment of the present invention, and FIG. 6 is a flowchart for explaining the operation of still another embodiment of the present invention. Next, with reference to FIGS. 1, 2, 5, and 6, the operation of still another embodiment of the present invention will be described. I. As shown in Fig. 5, when the card is activated, data is transmitted from the interrogator, which is recognized by the main control unit 7, and the main control unit 7 exchanges data with the interrogator when The main memory 10 and the sub memory 11 are not operating. Therefore, in the embodiment of the present invention, error detection of data stored in the main memory 10 and sub-memory 11 and correction of data are performed during this period.
すなわち、 図 6に示すように、 主制御部 7はデータのやりとり中であるか否か を判別し、 データのやりとり中であればメモリの誤り検出動作を行なわない。 主 制御部 7はデータのやりとり中でなければ誤り検出を行ない、 その検出結果をメ インメモリ 1 0またはサブメモリ 1 1に記億する。 これにより、 誤りが複数あつ ても対処できる。 主制御部 7はメインメモリ 1 0またはサブメモリ 1 1のすベて のバイ トについて誤り検出を行なつたかを判別し、 すべてのバイ トについて誤り 検出を行なう。 もし、 誤りを検出しなければ、 主制御部 7は誤り検出動作を終了 し、 質問器とデータのやりとりを行なうのを待つ。  That is, as shown in FIG. 6, the main control unit 7 determines whether or not data is being exchanged. If the data is being exchanged, the main controller 7 does not perform the memory error detection operation. The main control unit 7 performs error detection unless data is being exchanged, and records the detection result in the main memory 10 or the sub memory 11. This allows you to deal with multiple errors. The main control unit 7 determines whether error detection has been performed for all bytes of the main memory 10 or the sub memory 11 and performs error detection for all bytes. If no error is detected, the main control unit 7 ends the error detection operation and waits for data exchange with the interrogator.
メインメモリ 1 0またはサブメモリ 1 1のいずれかのメモリで誤りを検出した 場合には、 主制御部 7は質問器とデータのやりとりを行なうかを判別し、 動作中 でなければデータの補正を行なう。 そして、 すべてのエラ一についてデータの補 正をしたかを判別し、 その途中で実プログラムが動作中になると補正結果を記憶 し、 一連の動作を終了する。  If an error is detected in either the main memory 10 or the sub memory 11, the main control unit 7 determines whether to exchange data with the interrogator, and corrects the data if it is not operating. Do. Then, it is determined whether or not the data has been corrected for all errors. If the actual program is running during the process, the correction result is stored, and a series of operations is completed.
なお、 上述の実施例では、 起動時の質問器とデータのやりとりを行なっていな レ、ときに、 データの誤り検出を行なうようにしたが、 これに限ることなく起動時 以外の質問器とデータのみやりとりを行なっていない期間に、 メインメモリ 1 0 またはサブメモリ 1 1のデータの誤り検出およびデータの補正を行なうようにし てもよい。 さらに、 上述の実施例では、 非接触式の I Cカードにこの発明を適用するよう にしたが、 接触式の I Cカードに適用してもよレ、。 In the above-described embodiment, when data is not exchanged with the interrogator at the time of activation, data error detection is performed. However, the present invention is not limited to this. It is also possible to perform error detection and correction of data in the main memory 10 or the sub memory 11 during a period in which only exchange is performed. Further, in the above-described embodiment, the present invention is applied to a non-contact type IC card, but may be applied to a contact type IC card.
以上のように、 この発明によれば、 予備の不揮発性メモリを追加することによ り、 応力や静電気などの外部から加えられる力によるデータの変化や誤りに対し て信頼性を高めることができる。 しかも、 この発明によれば、 本来の不揮発性記 憶手段の非選択時にデータの誤り検出およびデータの補正を行なうようにしたの で、 実際の通信時間を変更することなく行なうことができ、 実時間を短縮できる。 産業上の利用可能性  As described above, according to the present invention, by adding a spare nonvolatile memory, it is possible to increase the reliability against data changes and errors due to externally applied forces such as stress and static electricity. . Moreover, according to the present invention, data error detection and data correction are performed when the original non-volatile storage means is not selected, so that the actual communication time can be changed without any change. You can save time. Industrial applicability
本発明によれば、 予備の不揮発性メモリを追加することにより、 応力や静電気 などの外部から加えられる力によるデータの変化や誤りに対して信頼性を高める ことができ、 しかも不揮発性メモリの非動作時に記憶しているデータの誤りを検 出でき、 信頼性の高い I cカードを提供できる。  According to the present invention, by adding a spare nonvolatile memory, it is possible to increase the reliability against data changes and errors due to externally applied forces such as stress and static electricity, and to improve the reliability of the nonvolatile memory. Errors in data stored during operation can be detected, and a highly reliable Ic card can be provided.

Claims

請求の範囲 The scope of the claims
1 . 質問器との間でデータのやり取りを行なう I Cカードであって、 1. An IC card that exchanges data with the interrogator.
前記質問器から与えられるデータを記憶するための不揮発性記憶手段と、 前記不揮発性記憶手段に記憶されるデータと 1対 1で対応を行なえるデータを 記憶する予備用不揮発性記憶手段とを備えた、 I Cカード。  Non-volatile storage means for storing data given from the interrogator, and spare non-volatile storage means for storing data that can correspond one-to-one with data stored in the non-volatile storage means The IC card.
2 . さらに、 前記不揮発性記憶手段に記憶されているデータの誤りを検出する誤 り検出手段と、  2. Error detecting means for detecting an error in data stored in the nonvolatile storage means;
前記誤り検出手段によって誤りが検出されなかつたことに応じて、 前記不揮発 性記憶手段に記憶されているデータを選択し、 誤りが検出されたことに応じて前 記予備用不揮発性記憶手段に記憶されているデータを選択する選択手段を備えた、 請求項 1に記載の I Cカード。  When the error is not detected by the error detecting means, the data stored in the non-volatile storage means is selected, and when the error is detected, the data is stored in the spare non-volatile storage means. 2. The IC card according to claim 1, further comprising a selection unit for selecting data stored therein.
3 . さらに、 前記予備用不揮発性記憶手段に記憶されているデータの誤りを検出 する誤り検出手段と、  3. Further, an error detecting means for detecting an error of data stored in the spare nonvolatile storage means,
前記誤り検出手段によって誤りが検出されなかったことに応じて、 前記予備用 不揮発性記憶手段に記憶されているデータを選択し、 誤りが検出されたことに応 じて前記不揮発性記憶手段に記憶されているデータを選択する選択手段を備えた、 請求項 1に記載の I Cカード。  When the error is not detected by the error detecting unit, the data stored in the spare nonvolatile storage unit is selected, and is stored in the nonvolatile storage unit in response to the detection of the error. 2. The IC card according to claim 1, further comprising a selection unit for selecting data stored therein.
4 . 前記予備用不揮発性記憶手段は 2個以上設けられていて、  4. Two or more spare nonvolatile storage means are provided,
前記不揮発性記憶手段に記憶されているデータと前記 2個以上の予備用不揮発 性記憶手段のそれぞれに記憶されているデータとの内容の多数決をとるための多 数決手段と、  Majority decision means for taking a majority decision on the contents of the data stored in the nonvolatile storage means and the data stored in each of the two or more spare nonvolatile storage means;
前記多数決手段によつて多数決の示された不揮発性記憶手段に記憶されている データを選択するための選択手段とを備えた、 請求項 1に記載の I Cカード。  2. The IC card according to claim 1, further comprising: selection means for selecting data stored in the non-volatile storage means indicated by the majority decision by the majority decision means.
5 . 前記不揮発性記憶手段と前記予備用不揮発性記憶手段は同一のデータを格納 する記憶素子の I Cチップ上の配置において距離を離したことを特徴とする、 請 求項 1に記載の I Cカード。 5. The IC card according to claim 1, wherein the non-volatile storage means and the spare non-volatile storage means are separated by a distance in an arrangement of storage elements for storing the same data on an IC chip. .
6 . 前記不揮発性記憶手段と前記予備不揮発性記憶手段は、 それぞれの記憶容量 が異なることを特徴とする、 請求項 1に記載の I cカード。 6. The Ic card according to claim 1, wherein the nonvolatile storage means and the spare nonvolatile storage means have different storage capacities.
7 . 前記誤り検出手段は 1バイ トまたは複数バイ ト毎に誤り検出を行なうことを 特徴とする、 請求項 2に記載の I Cカード。 7. The IC card according to claim 2, wherein the error detection means performs error detection for each byte or every plural bytes.
8 . 前記誤り検出手段の検出結果が前記不揮発性記憶手段に記憶されることを特 とする、 請求項 2または 7に記載の I Cカード。  8. The IC card according to claim 2, wherein a detection result of the error detection unit is stored in the nonvolatile storage unit.
9 . さらに、 前記誤り検出手段の検出結果に基づいてデータの誤りを訂正するこ とを特徴とする、 請求項 2に記載の I Cカード。  9. The IC card according to claim 2, further comprising correcting a data error based on a detection result of the error detection unit.
1 0 . 質問器とデータのやり取りを行なう I Cカードにおいて、  10. In an IC card that exchanges data with the interrogator,
前記質問器からのデータを記憶する不揮発性記憶手段と、  Non-volatile storage means for storing data from the interrogator,
前記不揮発性記憶手段の非選択時に前記不揮発性記憶手段に記憶されているデ ータの誤りを検出する誤り検出手段を備えた、 I Cカード。  An IC card comprising: an error detection unit configured to detect an error in data stored in the nonvolatile storage unit when the nonvolatile storage unit is not selected.
1 1 . さらに、 前記不揮発性記憶手段に記憶されているデータと同じデータまた は 1対 1に対応が行なえるデータを記憶する予備不揮発性記憶手段を含み、 前記誤り検出手段は前記不揮発性記憶手段または前記予備不揮発性記憶手段に 記憶されているデータの誤りを検出することを特徴とする、 請求項 1 0に記載の I Cカード。  11. A spare non-volatile storage unit for storing the same data as the data stored in the non-volatile storage unit or data that can be made to correspond one-to-one, wherein the error detection unit is a non-volatile storage unit. 10. The IC card according to claim 10, wherein an error of data stored in the means or the spare nonvolatile storage means is detected.
1 2 . 前記誤り検出手段は誤り検出結果に基づいて、 前記不揮発性記憶手段また は前記予備不揮発性記憶手段に記憶しているデータを補正することを特徴とする、 請求項 1 1に記載の I Cカード。 12. The method according to claim 11, wherein the error detection means corrects data stored in the nonvolatile storage means or the spare nonvolatile storage means based on an error detection result. IC card.
補正書の請求の範囲 Claims of amendment
[ 1 9 9 8年 5月 7日 (0 7 . 0 5 . 9 8 ) 国際事務局受理:出願当初の請求の範囲 2は取 り下げられた;出願当初の請求の範囲 1, 3, 4及び 7— 9は補正された;他の請求の 囲 は変更なし。 (2頁) ] [May 7, 1980 (07.0.9.8) Accepted by the International Bureau: Claim 2 originally filed was withdrawn; Claims 1, 3, 4 originally filed And 7-9 have been amended; other claims are unchanged. (2 pages)]
1 . (補正後) 贯問器との問でデータのやり取りを行なう I 力一ドであって、 前記質問器から与えられるデ一タを記憶すろための不^発性記憶手段と、 前記不揮発性記億手段に記憶されるデータと 1対 1で対応を行なえろデータを 記憶する予備用不师発性記憶手段と、 1. (After correction) An I-force for exchanging data with the interrogator, the non-volatile memory means for storing data given from the interrogator, and the nonvolatile memory A spare non-volatile storage means for storing data so that the data stored in the storage means can be made one-to-one correspondence;
前記不俾究性記憶手段に記憶されているデータの誤りを前記不师 ¾性¾憶手段 の更新前に検出可能に構成された り検出手段と、  An error detecting unit configured to detect an error in data stored in the non-volatile storage unit before updating the non-volatile storage unit;
前記誤り検出手段によって誤りが検出されなかつたことに応じて、 前記不揮発 性記憶手段に;! 億されているデータを選択し、 誤りが検出されたことに応じて前 記予備用不揷発性記憶手段に記憶されているデータを選択する選択手段とを備え た、 I C力一ド。  If the error is not detected by the error detecting means, the data stored in the non-volatile storage means is selected; and if the error is detected, the non-volatile memory is reserved. Selecting means for selecting data stored in the storage means.
2 . (削除)  2. (Delete)
3 . (補正後) ϊίΠί器との問でデータのやり取りを行なう I Cカードであって、 前記 ΚίίΠ器から与えられるデータを記憶すろための不揮発性記憶手段と、 前記不^発性 itd怠手段に;†L息されるデータと 1対 1で対応を行なえるデータを 記憶すろ予備用不揮発性記 tS手段と、  3. (After Correction) An IC card for exchanging data with a printer, wherein the non-volatile storage means for storing data given from the printer and the non-volatile memory means ; A non-volatile nonvolatile storage tS means for storing data that can be made to correspond one-to-one with data to be breathed;
前記予備 ffl不 発性記憶手段に; Ki されているデータの誤りを前記不揮¾性記 憶手段の更新前に検出可能に稱成された誤り検出手段と、  An error detection unit configured to be able to detect an error in the data stored in the spare ffl non-volatile storage unit before updating the non-volatile storage unit;
前記誤り検出手段によって誤りが検出されなかったことに応じて、 前記予備用 不揮発性記憶手段に記億されているデータを選択し、 , りが検出されたことに応 じて前記不^発性記 t'S手段に記憶されているデ一タを選択する選択手段を侦1えた、 請求项 1に; ¾載の〖 cカード。  When the error is not detected by the error detecting means, the data stored in the spare nonvolatile storage means is selected, and when the error is detected, the non-volatile memory is selected. The claim 1 further includes a selecting means for selecting data stored in the t'S means. The claim 1;
4 . (補正後) 前記予備用不揮¾性記†S手段は' 2 以上設けられていて、 さらに 前記不揮発性記憶手段に記億されているデータと前記 2個以上の予備用不揮発 性記憶手段のそれぞれに記憶されているデータとの内容の多数決をとるための多 数決手段を含み、  4. (After Correction) The spare nonvolatile storage means S is provided at least 2 and the data stored in the nonvolatile storage means and the two or more spare nonvolatile storage means are further provided. A majority vote means for taking a majority vote of the contents with the data stored in each of the means,
前記選択手段は前記多数決手段によって多数決の示された不师発性記億手段に 記憶されているデータを選択すろ、 , ι'ί求项 1に記戟の I Cカード。  The selecting means selects the data stored in the non-volatile storage means indicated by the majority vote by the majority means.
10 補正された用紙 (条約第 19条) 10 Amended paper (Article 19 of the Convention)
5 . 前記不揮発性記 I 手段と前記予備用不^ ¾性記 手段は同一のデータを格納 する記憶素子の I cチッブ上の配^にぉレ、て距離を離したことを特徴とする、 - 求項 1に記載の I C力一ド。 5. The nonvolatile memory I means and the spare nonvolatile memory means are arranged apart from each other by disposing the storage elements for storing the same data on the I c chip. -IC force as described in claim 1.
6 . 前記不渖発性記憶手段と前記予備不揮 ¾性記惚手段は、 それぞれの ¾' 容¾ δ が異なることを特徴とする、 諮-求項 1に記救の I C力一ド::  6. The non-volatile memory means and the preliminary non-volatile memory means are different from each other in ¾ 'capacity δ. :
7 . (補正後) 前記誤り検出手段は 1バイ 卜または複数バイ ト ¾に り検出を行 なうことを特徴とする、 'ί求项 1に記載の I Cカードつ  7. (After Correction) The IC card according to claim 1 is characterized in that the error detecting means detects one or more bytes.
8 . (補正後) 前記誤り検出手段の検出結果が前記不 ¾性記憶手段に記憶され ることを特徴とする、 ^求項 1に記載の I C力一ド。 8. (After correction) The IC force according to claim 1, wherein a detection result of the error detecting means is stored in the non-volatile storage means.
0 9 . (袖正後) さらに、 前記誤り検出手段の検出結果に ¾づいてデータの誤りを 訂正することを特徴とする、 請求項 1に記救の〖 C力一ド 0 9. (After Sode Masaru) Further, a data error is corrected based on a detection result of the error detection means, wherein the error is corrected.
1 0 . 質問器とデータのやり取りを行なう I C力一ドにおいて、  1 0. In the I C mode that exchanges data with the interrogator,
前記 Κ問器からのデータを記憶する不揮発性記憶手段と、  Non-volatile storage means for storing data from the interrogator;
前記不揮究性記憶手段の非選択時に前記不邢発性記 t 手段に, ditされているデ5 —タの誤りを検出する誤り検出^段を備えた、 I Cカード:  When the non-volatile memory means is not selected, the non-volatile memory means has an error detection step for detecting an error in ditted data.
1 1 . さらに、 前記不 段に;!億されているデータと同じデ一タまた は 1対 1に対応が行なえるデータを記憶する予備不^ ¾性記億 段を含み、 前記誤り検出^段は前記不^発性記¾手段または ί)ίί¾予備不^発性記憶^段に 記憶されているデータの誤りを検出することを特徴とする、 ^求项1 ()に記載の0 I Cカード。 1 1. In addition, irregularly; And a spare memory for storing the same data or data that can be made to correspond one-to-one with the data stored in the memory. and detecting an error in data stored in ί) ίί¾ preliminary non ^ nonvolatile memory ^ stage, 0 IC card according to ^ Motome项1 ().
1 2 . 前記誤り検出手段は誤り検出結¾に&づいて、 Πί了記不^¾性記 t'ST-段また は前記予備不揮発性記' I 手段に ¾憶しているデータを補正することを特徴とする、 請求項 1 1に記載の〖 C力一ドっ  1 2. The error detecting means corrects the data stored in the end non-permanence t'ST-stage or the spare non-volatile memory I based on the error detection result. 11. The method according to claim 11, wherein:
11 11
捕正された用紙 (条約第 19条)  Paper captured (Article 19 of the Convention)
PCT/JP1997/004691 1996-12-26 1997-12-18 Ic card WO1998029814A1 (en)

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JP34822596A JPH10187550A (en) 1996-12-26 1996-12-26 Ic card
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JP8/348226 1996-12-26

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5940398A (en) * 1982-08-30 1984-03-06 Toshiba Corp Memory control system
JPS61211786A (en) * 1985-03-16 1986-09-19 Hitachi Maxell Ltd Ic card
JPS63279347A (en) * 1987-05-11 1988-11-16 Nippon Telegr & Teleph Corp <Ntt> Memory device
JPS63288383A (en) * 1987-05-20 1988-11-25 Nec Corp Integrated circuit card
JPH0358743U (en) * 1989-06-09 1991-06-07
JPH04115340A (en) * 1990-09-05 1992-04-16 Koufu Nippon Denki Kk Duplex storage circuit
JPH06214890A (en) * 1993-01-14 1994-08-05 Mitsubishi Electric Corp Computer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5940398A (en) * 1982-08-30 1984-03-06 Toshiba Corp Memory control system
JPS61211786A (en) * 1985-03-16 1986-09-19 Hitachi Maxell Ltd Ic card
JPS63279347A (en) * 1987-05-11 1988-11-16 Nippon Telegr & Teleph Corp <Ntt> Memory device
JPS63288383A (en) * 1987-05-20 1988-11-25 Nec Corp Integrated circuit card
JPH0358743U (en) * 1989-06-09 1991-06-07
JPH04115340A (en) * 1990-09-05 1992-04-16 Koufu Nippon Denki Kk Duplex storage circuit
JPH06214890A (en) * 1993-01-14 1994-08-05 Mitsubishi Electric Corp Computer

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