JPS5940398A - Memory control system - Google Patents

Abstract

PURPOSE:To prevent previously the generation of an error of >=2 bits, by carrying out the full-word reading of a main memory by making use of the idle time of a CPU for each certain time and rewriting the data corrected by an ECC circuit in a memory read mode. CONSTITUTION:In a general operation mode where the data is read out of a prescribed address of a memory with a request given from a CPU, a read request is set to a function register FUNC9. Then a memory address is set to a memory address register MAR10. Thus a memory request is delivered to set the data to a memory read register MRR3 from a main memory MEM1 via a write buffer register WBR7 and a memory write register MWR2. A check bit obtained at that moment is set to a check bit register CBR4. Then both data are supplied to an ECC circuit 5, and the data with a correction given to a single bit error, if any, is set to a read buffer register RBR8.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a storage control system for a main memory of an electronic computer [Technical Background of Defense] In recent years, dynamic RA
The tendency to use M is decreasing, but this element is
There is also the so-called ft error problem, which causes malfunctions due to the influence of wires. Therefore, the main memory itself is generally corrected by l-bit error correction and automatic rewriting by the FCC circuit, thereby reducing the rate at which errors occur.

[Problems with background technology]

However, in the above case, an error of 2 or more bits may occur for addresses in the main memory that are not accessed/written for a long period of time, which has the disadvantage of causing serious accidents such as system down. .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control method that does not cause errors of two or more bits, which are the cause of the above-mentioned drawbacks.

[Minority of invention]

In order to achieve the above-mentioned object, the present invention periodically performs empty reading of the memory by using the idle time of the CPU, and when an error is detected by the FCC, the correction data is re-committed. When a memory write request occurs from the DMA device when writing data, the memory write request interrupts between the memory read and the B] positive data write, and the memory write request from the DMA device occurs. Since the data will be rewritten by the corrected data, an interlock is established to prohibit priority interrupts until the rewriting is completed, so that normal memory correction can be performed.

[Embodiments of the invention]

Figure 1 shows an ECC with FCC added only to the lead side.
This shows the memory control circuit diagram with circuit; hF), <1
) td main memory MEM, (2) is memory write register MWR, (3) is memory read register MRR.

(4) is the check pit register CB used in ECC
R1(5) is an ECC circuit. (6) is the ECC circuit (
5) This is a syndrome signal detected by the CPU.If this syndrome signal is a logic 10# signal, it means that the read data is normal, and if it is a logic '''l# signal, it means that the read data is abnormal, and the CPU is notified. (7) is the write bumper register WBR, (81 is the read buffer register RBR. (9) has the function of specifying memory read or write with the function register FUNC. (kl is the memory address register MAR
Specify the memory address to access with . ■ is the memory data register MDR.

A is a controller circuit 5RCNT which receives the syndrome signal (6) and notifies the CPU. (1) CPU and 1) Memory request from MA device α4 and EC
Firmware F/W control circuit MRQ that locks the ink-lock of corrected data rewrite timing from C(5)
It is INT.

In FIG. 1, in a general operation of reading data from a desired address in memory in response to a request from the CPU, a read request is set in function register FUNC (9), and memory address register M A R is set in function register FUNC (9).
(When the memory address is set to IQI, a memory request is issued and the write/(7 register W B R (7
), the data read from the main memory MEM (11) is set to the memory read register MRR (3) via the memory write register MWR (2), and the check pit at that time is set to the check pit register CB R (4). Both data are input to the ECC circuit (5), and if there is a single bit error, the corrected data is set to the read buffer register RB R (8).
) Syndrome signal output from (6)K υCPU
An abnormality is notified.

FIG. 2 shows the operation of the invention in FIG. In the present invention, in order to avoid the risk of the above-mentioned 2-bit error occurring when a part of the memory is not read or written for a long time, the CPU idle time separated by a certain period of time is used. The address of the above area specified by the empty read memory address counter CNTR (not shown) is set in the memory address register MAR (101) (step a). Then, a full word read MFR is performed from the main memory (1) ( Step b). The take and syndrome read from main memory (1) are MRR (3).

CB R (4) is supplied to F CC (51), F
The data is checked for errors in the CC (51) (step C). If an error is detected in this step C, the CPU and DMA device memory requests and E
In order to rewrite the corrected data from CC (5) and take the interlock ITL, MRQ INT (1 to internal interlock flip-flop 7' ITL F/
(step d). Then, the correction data output from E CC (5) to RB R (81) is sent to M W R (2) via W B R (7).
main memory (1) specified by MARQI.
Memory full word write M to the same memory address of
Play FW.

(Step e). When this step e is completed, the interlock flip 70 block ITL F/F is reset (step f) L, and the inhibition of memory requests from the DMA device Q41 is released. Next, in step g, it is checked whether it is the final memory address, and if it is the final address, O is set in the memory address counter CNTR (step h). (in this example, 4 bytes) is added (step i).

Next, interrupts are checked in step j, and if there is an interrupt request, the program exits from the loop and moves to the interrupt processing routine; if there is no interrupt, it returns to the idle routine.

〔Effect of the invention〕

The present invention is as described above, and when it consists of IWi
When the main memory is full, using the idle time of the CPU,
Perform word read and EC performed when reading memory
By rewriting the data corrected by the C circuit, it is possible to prevent errors of two or more bits from occurring even in portions that have not been read or written for a long time. Also, between memory read and rewrite writes, D M
Even if the memory request from device A is successful, there is a budding state in which the interlock circuit allows normal data writing.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 e
2 is a flowchart illustrating an idle routine that includes firmware that is "unexpected." 1: Main memory, 5: ECC circuit, 13: Interlock circuit. Figure 1 Figure 2

Claims (1)

[Claims] Empty reading of the memory is performed while the CPU-U is idle, error detection and correction of the read data is performed by the ECC circuit, and when an error is detected, the corrected data p+1
A memory control method that is characterized by interlocking memory requests from DMA under firmware control during processing.