JP2546002B2 - Parity circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a novel parity circuit that obtains a parity based on data and performs a parity check using the parity and the data.

[Conventional example] Conventionally, when writing or reading data in a computer or the like, for example, a parity bit is added to the most significant bit of the data, but this parity bit makes the total number of "1" of the data always even or odd. The data check is performed by this even or odd number.

Therefore, as shown in FIG.
When data is written in the memory unit (for example, RAM) 3 via the data bus 2 in the CPU 1, the parity generation / check circuit 4 generates parity in which the total number of “1” s of the data is even or odd, This parity is parity RAM
It is stored in the unit 5. When data is transferred by the CPU 1, that is, when the data in the memory unit 3 is read out via the data bus 2, the parity generation / check circuit 4
Then, the value obtained based on the data is compared with the value read from the parity section 5, and if they do not match, an error is generated and an interrupt signal is output to the CPU 1. As a result, the CPU 1 can stop the data transfer due to the interrupt.

[Problems to be Solved by the Invention] However, in the parity circuit described above, a new parity RAM unit 5 is required in addition to the memory unit 3, that is, at least one memory has to be increased, and that much is required. The cost was increasing.

In addition, recent storage elements, such as DRAMs, tend to have a large capacity, and it is difficult to obtain a small capacity DRAM. Therefore, even in a small system, a large capacity DRAM
Will be used for the memory unit 3 and the parity unit 5, and the DRAM
Not only is not used effectively, but also the uneconomic side has come to occur.

Furthermore, when an error occurs due to an interrupt, it is impossible to determine whether the parity bit stored in the parity unit 5 has an error or the data stored in the memory unit 3 has an error.

The present invention has been made in view of the above problems, and an object thereof is to provide a parity circuit capable of reducing the cost and effectively using a memory.

[Means for Solving the Problems] In order to achieve the above object, the present invention checks the parity when reading data from a memory based on an instruction from a CPU, and if the data is normal, transfers the data to a predetermined data bus. In the parity circuit that transfers data to the memory circuit, the internal memory area is divided into two, one of which is the original data data area and the other is the parity area for the parity data, and when data is written to the memory area. And a timing circuit for alternately designating the data area and the parity area when reading data,
When writing the parity data to the parity area and reading the parity data from the parity area, two parity bits that differ depending on whether the total number of “1” or “0” included in the parity data is an even number or an odd number is set. A parity generation unit for generating, and an exclusive OR circuit for inverting or non-inverting the parity data written to the parity area and the parity data read from the parity area based on the parity bit from the parity generation unit. , A latch circuit for temporarily holding the parity data read from the parity area via the exclusive OR circuit, the parity data held in the latch circuit and the original read from the data area. While comparing with the data and sending out the match and mismatch signals, In the case of a match, a comparison unit that detects the number of mismatch bits, and an interrupt signal generation unit that outputs an interrupt signal and the number of mismatch bits to the CPU in response to a mismatch signal from the comparison unit are provided. When the parity data does not match, the CPU transfers the parity data held in the latch circuit to the data bus when the CPU determines that the parity data side is correct due to the number of mismatch bits. There is.

[Operation] With the above configuration, when writing data to the memory via the data bus (when writing data in the write cycle), the parity is generated based on the data, and the number of "1" s of the data is calculated. To be For example, if the parity is odd, it is set to "1", and if it is even, it is set to "0", and this parity is temporarily stored. Based on the parity, the data is inverted or non-inverted, the inverted or non-inverted data is used as parity data, and a predetermined area (address corresponding to write data) of the parity area is rewritten by this parity data. After that, the temporary storage of the parity is cleared, and the data is directly written in the data area as the original data.

In this way, the data is written in the data area as usual, and the predetermined area of the parity area is rewritten with the parity data of the inverted or non-inverted data.

Then, when reading the data in the memory (when reading the data in the read cycle), first, the parity data in the parity area is read, and the parity is generated based on the parity data. in this case,
"1" if the parity data in the parity area is abnormal
Since the number is odd, parity "1" is obtained from the parity data, and if the parity area is normal, the parity "0" is obtained and this parity is temporarily stored. Subsequently, the read parity data is inverted or non-inverted and latched based on the parity. After that, the currently read data is compared with the latched parity data, and a match or mismatch signal is output. Further, in the comparison, it is determined whether or not the number of mismatched bits is one. If the number of the mismatched bits is one, it is determined that the parity data side is correct, and the latched parity data is transferred to the data bus.

[Examples] Examples of the present invention will be described below with reference to FIGS. 1 to 10. In FIG. 1, the same parts and corresponding parts as those in FIG. 11 are designated by the same reference numerals, and the duplicated description will be omitted.

In FIG. 1, the parity circuit includes a memory unit 3 having a data area and a parity area, write data is output to the memory unit 3, read data is output to the data bus 2, and parity data described below is output. Exclusive OR circuit 6 for inverting or non-inverting and outputting
And a parity generation circuit 7 that generates a parity based on the written data or the read parity data,
The generated parity is temporarily stored, and the parity F / F circuit 8 for inverting or non-inverting the exclusive OR circuit 6 according to the stored parity and the latch circuit 9 for latching the read parity data. And a comparison unit that compares the latched parity data with the data currently read out on the data bus 2, outputs a match or mismatch signal, and determines whether or not the number of mismatch bits is one. 10, a three-state circuit 11 that places the latched parity data on the data bus 2, and an interrupt F / that outputs an interrupt signal to the CPU 1 due to a mismatch signal from the comparison unit 10.
F circuit 12, CPU 1 clock (φ) signal, memory unit 3,
A timing circuit 13 that generates timing signals for the parity F / F circuit 8, the latch circuit 9, the comparison unit 10, and the interrupt F / F circuit 12, and an address on the address bus is decoded to select the chip select (CS) of the memory unit 3. A decoder 14 that outputs a signal and an enable signal for the three-state circuit 11 is provided.

The exclusive OR circuit 6 is provided with a circuit including two EOR circuits 6a and 6b and three-state buffer circuits 6c and 6d as many as the number of bits of the data bus 2, as shown in FIG. Then, the written or read parity data is inverted or non-inverted according to the state (“1”, “0”) of the parity F / F circuit 8.

Next, the operation of the parity circuit configured as described above will be described based on the time charts of FIGS. 3 and 4 and the schematic diagrams of the data and parity data of FIGS. 5 to 10.

First, assuming that data writing is being executed based on the write cycle shown in FIG. 3, an address is output from the CPU 1 (shown in FIG. 3B), and this address causes the decoder 14 to output the memory section. A chip select signal is output to 3 (shown in FIG. At this time, the timing circuit 13 outputs the timing signal a to the clock (φ).
From T ₁ to T _W timing, that is, the most significant bit of the address is set to “H” (shown in (i) of the same figure), and during the “H”, the address is stored in the memory unit 3. It will indicate the parity area. On the other hand, the parity generation circuit 7 determines whether the number of “1” is odd or even based on the data to be written. For example, when the number is odd, the parity of “1” is generated. If the number is even, a parity of “0” is generated and output to the parity F / F circuit 8.

Then, from the timing circuit 13, the clock (φ) T ₂
Since the timing signal c is output at the timing, "1" or "0" is temporarily stored in the parity F / F circuit 8 (shown in (e) and (f) of the same figure). The exclusive OR circuit 6 inverts the input data,
Alternatively, it will be non-inverted and output. Further, from the timing circuit 13, the timing signal b, that is, the write enable signal is "L" at the timing of T _W of the clock (φ).
Since it is set to the level (shown in (g) of the same figure), the memory unit 3
Is set to a writable state, data on the data bus 2 is converted into parity data via the exclusive OR circuit 6, and a predetermined area (address corresponding to the write data) of the parity area is rewritten by this parity data. . In this case, when the parity "1" is generated by the parity generator 7, the data on the data bus 2 is inverted and written in the parity area by the exclusive OR circuit 6, and the parity "0" is also generated. When it is generated, the data on the data bus 2 is directly converted to parity data, and a predetermined area of the parity area is rewritten by this parity data.

Subsequently, after the T _W timing of the clock (φ), the timing circuit 13 sets the timing signal a, that is, the most significant bit of the address to the “L” level, and the timing signal b,
That is, the write enable signal is set to the “L” level at the T ₃ timing of the clock (φ) (shown in (g) of the same figure), and the parity F / F circuit 8 is set at the rising timing of the first pulse of the timing signal b. Because it is cleared ((f) in the figure)
(Shown in FIG. 3), the exclusive OR circuit 6 is non-inverted, and the address indicates the data area of the memory unit 3. At this time, the exclusive OR circuit 6 outputs the data on the data bus 2 to the memory section 3 as it is, so that the write data is written in a predetermined area of the data area.

That is, in the write cycle, the parity is generated at the timing of T ₁ , T ₂ , and T _W of the clock (φ), the inverted or non-inverted parity data is written in the parity area, and after T _{W of the} clock (φ). , Non-inverted data, that is, original data is written in the data area.

On the other hand, since the data in the data area is read and transferred, the data read is executed based on the read cycle shown in FIG. The number of data "1" s is determined to be an even number, and the write data is, for example, "11 (H)", that is, the data "1" s.
If the number of is even, as shown in FIG.
It is assumed that the memory unit 3 is normal and that the same data "11 (H)" is written at a predetermined address in the data area and the parity area.

First, the CPU 1 outputs an address (shown in FIG. 2B), and the address is output from the decoder 14 to the memory unit 3.
The chip select signal is output (as shown in FIG. In this case, the timing signal a from the timing circuit 13 is in "H" level to T _1, T _2, T _W of CPU1 clock (phi), that is the most significant bit of the address is "1" (FIG. (Shown in (i)), and since the timing signal b is set to "H" level during this read cycle ((g) in the figure).
Address) indicates that the address indicates the parity area of the memory section 3 while the timing signal a is at "H" level. Therefore, the parity data 1 in the parity area is read by the above address, but since the memory unit 3 is normal, the parity data 1 is "11 (H)" (shown in FIG. 7C).

Subsequently, the parity generation unit 7 detects whether the number of "1" s of the read parity data "11 (H)" is odd or even. In this case, it is even. , "0" is stored in the parity F / F circuit 8 and the exclusive OR circuit 6 is set to the non-inverting output operation. Then, the parity data 1 via the exclusive OR circuit 6 remains “11”.
(H) ”(parity data 2) (shown in (c) of the figure).

At this time, the timing circuit 13 outputs the clock (φ)
T _W timing signal d is output (shown in FIG. (J)), the signal d of inverting the parity data 2 by "11 (H)" is latched by the latch circuit 9 (FIG. (K) Shown in). After that, that is, after T _{W of the} clock (φ), the timing signal d is set to the “L” level and the parity F /
Since the output of the F circuit 8 remains at "0" level, the data "11 (H)" in the data area of the memory unit 3 is read according to the address from the CPU 1. The read data is passed through the exclusive OR circuit 6 as it is to the data bus 2
It is placed on the top (shown in (h) of the same figure).

Next, "11" of the data currently on the data bus 2
(H) "and" 11 (H) "of the parity data 2 latched in the latch circuit 9 are compared in the comparison unit 10, and a match or mismatch signal is output to the interrupt F / F circuit 12 for comparison. A match signal is output from the part 10. At this time,
Although the timing signal d is output from the timing circuit 13 at T ₃ of the clock (φ) (shown in (1) of the same figure), the interrupt signal is not set in the interrupt F / F circuit 12 and the interrupt signal is generated. No signal is generated (indicated by the broken line in FIG. 6 (m)).

By the way, as shown in FIG. 6, for example, the data area is abnormal, and "10" is not "11 (H)".
Assuming that (H) ”is written and the parity area is normal,“ 11 (H) ”of the parity data 2 in the parity area is latched by the latch circuit 9 as it is, as described above. , The data "10 (H)" in the data area is read and this data is compared with the latched parity data. In this case, since the mismatch signal is output to the interrupt F / F circuit 12, the interrupt is generated. A signal is output to the CPU 1. Thereby, the CPU 1 performs interrupt processing, and whether the data or parity data is different based on the judgment by the comparison unit 10 whether the number of mismatch bits is one or not. Inversion is executed, that is, if the number of mismatch bits is 1, the data “10 (H)” is different, that is, the data area is abnormal, because there is an error in the data. It is possible to determine that the tier area is normal.At this time, the floating signal of the three-state circuit 11 is released by the enable signal from the decoder 14, and the parity data “11 ( Since "H)" is output as data (correct data), the next read cycle can be continuously executed.

If the parity area of the memory unit 3 is abnormal and "01 (H)" is written instead of "11 (H)" as shown in FIG. Data 1 “01 (H)” is read. Then, since the number of "1" s of the data is odd, the parity "1" is generated by the parity generation circuit 7, and therefore the parity F / F circuit 8 stores the "1". Therefore, the exclusive OR circuit 6 is shown (indicated by the broken line in FIG.
Is inverted output operation, that is, the parity data 1 via the exclusive OR circuit 6 becomes "FE (H)" (parity data 2), and this parity data 2 ("FE (H)") is latched by the latch circuit 9. Latched on.

Then, in the same way as above, the data in the data area "11
(H) "is read and this data is compared with the parity data 2" FE (H) "of the latch circuit 9. In this case, since a mismatch signal is obtained, the CPU 1 is interrupted (the same). This is indicated by the solid line in the figure (m).
Then, the interrupt processing is performed, and the comparison unit 10 inverts whether the data or the parity data is different based on the determination as to whether the number of mismatch bits is one or not. That is, when the number of mismatched bits is 7, it can be determined that the parity area is abnormal and the data area is normal because the parity data has an error.

In the above embodiment, the case where the number of “1” s of the write data is an even number has been described, but the same is true even if the number is an odd number.

First, when the write data is, for example, “01 (H)”, that is, when the number of “1” s in the data is an odd number, as shown in FIG. 8, when the memory unit 3 is normal, Inverted "FE (H)" is written in the parity area and data "01 (H)" is written in the data area.

Then, in the same manner as above, the parity data in the parity area is read out.
Since the number of "1" s in (H) "is odd, parity" 1 "is generated in the parity generation unit 7. Then, the parity data 1" FE (H) "is the exclusive OR circuit. The parity data 2 “01 (H)” is inverted at 6 and the parity data 2 “01 (H)” is latched by the latch circuit 9.

Then, the data "01
(H) "is read out and this data is compared with the latched parity data. In this case, since a coincidence signal is obtained, the CPU 1 is not interrupted ((m) in the figure).
The read cycle is continued.

Also, as shown in FIG. 9, for example, assume that the data area is abnormal and "00 (H)" is written in this data area instead of "01 (H)", and the parity area is Assuming that the data is normal, the parity data 1 “FE (H)” in the parity area is inverted to parity data 2 “01 (H)”, and this parity data 2 “01 (H)” is obtained. It is latched by the latch circuit 9.
Then, the data "00 (H)" in the data area is read and this data is compared with the latched parity data. In this case, a disagreement signal is obtained, and the CPU 1 is interrupted (shown by the solid line in (m) of the figure). As a result, the CPU 1 performs the interrupt process, and the comparison unit 10 determines whether or not the data or parity data is different based on whether or not the number of mismatch bits is one. In this case, since the number of mismatch bits is one, it can be determined that the data area is abnormal and the parity area is normal.

Also, for example, as shown in FIG. 10, the parity area is abnormal and "01
It is assumed that “FF (H)” is written instead of (H). Then, the parity data 1 “FF (H)” is read and the number of “1” of the parity data 1 is even. Because of this, the parity “0” is generated in the parity generation unit 7. Therefore, the “0” is stored in the parity F / F circuit 8, and the exclusive OR circuit 6 performs the non-inverted output operation. Therefore, the parity data 1 that has passed through the exclusive OR circuit 6 becomes the parity data 2 "FF (H)" as it is,
It is latched by the latch circuit 9.

Then, in the same manner as above, the data in the data area "01
(H) "is read out and this data is compared with the latched parity data 2. In this case, a mismatch signal is obtained and an interrupt is issued to the CPU 1 (indicated by the solid line in FIG. As a result, the CPU 1 performs the interrupt process, and the comparison unit 10 determines whether the data or the parity data is different based on the determination whether the number of mismatch bits is one. In this case, since there are seven mismatch bits, it can be determined that the parity data has an error, that is, the parity area is abnormal and the data area is normal.

The write cycle in FIG. 3 and the read cycle in FIG. 4 are performed by the microprocessor Z80, but the same applies to other ones.

[Effects of the Invention] As described above, according to the parity circuit of the present invention, a memory having a data area and a parity area, and an exclusive arrangement for inverting or non-inverting the parity data when writing or reading the parity data. Logical OR circuit, a parity generation circuit that generates a parity bit based on the data written in the data area or the read parity data, and a parity F that controls the inversion and non-inversion output of the exclusive OR circuit by the generated parity bit. The / F circuit and the latch circuit that latches the parity data read via the exclusive OR circuit and the latched parity data are compared with the data currently read from the memory, and a match or mismatch signal is output. An interrupt signal is sent to the CPU by the output comparison unit and its mismatch signal. Since it has an output interrupt F / F circuit and can judge whether there is only one mismatch bit in the above comparison, it is possible to omit the parity check memory (memory element; IC). The cost can be reduced. Also,
Even if there is a mismatch, if the parity data side is determined to be correct by the number of mismatch bits, the latched parity data is transferred to the data bus.
The read cycle is not interrupted.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a parity circuit showing an embodiment of the present invention, FIG. 2 is a specific partial circuit diagram of the parity circuit, and FIGS. 3 and 4 explain the operation of the parity circuit. 5 to 10 are schematic diagrams for explaining the contents of the memory used in the parity circuit, and FIG. 11 is a schematic block diagram of a conventional parity circuit. In the figure, 1 is a CPU, 2 is a data bus, 3 is a memory unit (RA
M), 6 is an exclusive OR circuit, 7 is a parity generation circuit,
8 is a parity F / F circuit, 9 is a latch circuit, 11 is a comparison unit, 1
2 is an interrupt F / F circuit, 13 is a timing circuit, and 14 is a decoder.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masaaki Saito, 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa, Fujitsu General Co., Ltd. (72) Toru Iwano, 1116 Suenaga, Takatsu-ku, Kawasaki, Kanagawa (56) Reference JP-A-55-4757 (JP, A)

Claims (1)

(57) [Claims] 1. A parity circuit that checks the parity when reading data from a memory based on an instruction from a CPU and transfers the data to a predetermined data bus when normal, divides an internal memory area into two parts. , One of which is the data area for the original data and the other of which is the parity area for the parity data, and the data area and the parity area alternate when data is written to and read from the memory section. And the timing circuit specified in the above, depending on whether the total number of "1" or "0" contained in the parity data at the time of writing the parity data to the parity area and at the time of reading from the parity area is an even number. And a parity generation unit that generates two different parity bits according to An exclusive OR circuit that inverts or does not invert the parity data to be written to the parity data and the parity data read from the parity area based on the parity bit from the parity generation unit; and the exclusive logic from the parity area. A latch circuit that temporarily holds the parity data read out via the sum circuit and the parity data held in the latch circuit and the original data read out from the data area are compared and the results match. , A non-coincidence signal is sent, and in the case of non-coincidence, a comparison unit that detects the non-coincidence bit number, and an interruption signal generation means that outputs the non-coincidence signal to the CPU by the non-coincidence signal from the comparison unit And when the original data and the parity data do not match,
The parity circuit, wherein the CPU transfers the parity data held in the latch circuit to the data bus when the CPU determines that the parity data side is correct based on the number of mismatch bits.