JPH03186936A - Parity circuit - Google Patents

Abstract

PURPOSE:To eliminate a parity check memory by judging whether a non- coincidence bit is one or not at the time of comparison. CONSTITUTION:When a data area is abnormal, not '11(H)' but '10(H)' is written and a parity area is normal, '11(H)' of parity data 2 in the parity area is latched by a latch circuit 9 as it is. Then, data '10(H)' in the data area is read, and the data and latched parity data are compared. Since a non- coincidence signal is outputted to an interruption F/F circuit 12, an interruption signal is outputted to CPU 1. Consequently, an interruption processing is executed in CPU 1 and inversion whether data or parity data is different or not based on judgement whether the number of non-coincident bits is one or not is executed by a comparison part 10. Thus, the parity check memory is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a novel parity circuit that determines parity based on data and performs a parity check using this parity and data.

[Conventional example] Conventionally, when writing or reading data in a computer or the like, a parity pit is added to the most significant bit of the data. Data is checked using this even or odd number.

Therefore, as shown in FIG. 11, data is transferred to the memory section (
For example, when written to RAM) 3, parity generation and
The test circuit 4 generates a parity that makes the total number of LL I TT of the data an even or odd number, and this parity is stored in the parity RAM section 5 . And the CPU
When data is transferred in step 1, that is, when the data in the memory section 3 is read out via the data bus 2, the parity generation/check circuit 4 generates a value calculated based on the data and the parity section 5. The value read from C is compared with the value read from C.
Output to PUI. This causes that interrupt to
Data transfer can be stopped and processed using the CPUI.

[Problems to be Solved by the Invention] However, in the parity circuit described above, a new parity RAM section 5 is required in addition to the memory section 3, which means that at least one memory must be added. The cost increased accordingly.

Furthermore, recent memory elements, such as DRAM, are at a low quantification rate of 1r+l, making it difficult to obtain RAM. Therefore, even in the case of a small system, 1) RAM of the Omiya site is used for the memory section 3 and parity section 5, which not only does not effectively utilize the DRA and M, but also causes an uneconomical situation. became.

Furthermore, when an error occurs due to an interrupt, the parity section 5
It was not possible to determine whether there was an error in the parity hit stored in the memory section 3 or whether there was an error in the data stored in the memory section 3.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a varitillo path that can reduce costs and make effective use of memory.

[Means for Solving the Problems] In order to achieve the above object, the present invention checks parity when reading/transferring data in a memory and transmits data to a CPU based on this parity check. The parity circuit for generating an interrupt includes a data area and a parity area provided in the memory, a parity generating means for generating parity based on the data or parity data read from the parity area, and a parity generating means for generating parity based on the data or parity data read from the parity area. Exclusive OR means for inverting or non-inverting the parity data when writing data as parity data into the above parity area or reading parity data from the parity area; Compare the parity data sent through and the data actually read from the above data area,
Comparing means for outputting a match or mismatch signal and determining whether there is at least one mismatch bit;
The gist of the present invention is to include an interrupt signal generating means for outputting an interrupt signal to the CPU in response to the mismatch signal.

[Operation] With the above configuration, when data is written to the memory via the data bus (when data is written by a write cycle), parity is generated based on the data, and the number of tries for that data is calculated. For example, if the number is odd, the parity is set to "0", and if the number is even, it is set to O'", and this parity is temporarily stored. Based on the parity, the data is inverted or non-inverted, This inverted or non-inverted data is used as parity data, and a predetermined area of the parity area (address corresponding to the write data) is rewritten with this parity data.Then, the temporary storage of the parity described in -1- is cleared, and - The data is written to the data area as is.

In this way, data is written in the data area as usual, and a predetermined area of the parity area is rewritten with the above-mentioned inverted or non-inverted parity data.

Then, in (1) when reading data from the memory by a read cycle), parity data in the parity area is first read, and parity is generated based on this parity data. in this case,
If the parity data in the parity area is abnormal, LL
Since the number of I I+ is odd, the parity 11 ]-TI is obtained from the parity data, and if the parity area is normal, the parity "0" is obtained and this parity is temporarily stored. Subsequently, the read parity data is inverted or non-inverted based on the parity and latched. Thereafter, the currently read data and the latched parity data are compared, and a match or mismatch signal is output.

Further, during the comparison, it is determined whether the number of unmatched pins is -.

[Example] Hereinafter, an example of the present invention will be described based on the drawings 1 to 10. In FIG. 1, the same parts and corresponding parts as in FIG. 11 are denoted by the same reference numerals, and redundant explanation will be omitted.

In FIG. 1, the parity circuit includes a memory section 3 having a data area and a parity area, outputting data to be written to the memory section 3, outputting read data to a data bus 2, and outputting data to be written to the memory section 3, as will be described later. Invert parity data,
Alternatively, an exclusive OR circuit 6 that outputs the non-inverted data, a parity generation circuit 7 that generates parity based on write data or read parity data, and a parity generation circuit 7 that temporarily stores the generated parity and stores the stored parity. A parity F/F circuit 8 that makes the exclusive OR circuit 6 perform an inverting or non-inverting output operation according to Compare the data currently being read out on data bus 2,
Outputs a match or mismatch signal, and also outputs a match or mismatch signal.
A comparison unit 10 that determines whether the number is one, a three-state circuit 11 that puts the latched parity data on the data bus 2, and an interrupt signal sent to the CPU 1 by a mismatch signal from the comparison unit IO. Interrupt F/
F circuit 12, CPU clock (φ) signal, memory section 3, parity F/F circuit 8, latch circuit 9, comparison section 1
0 and the timing 1% 13 that generates the timing signal of the interrupt F/F circuit 12 and the chip select (CS) of the memory section 3 that decodes the address on the address bus.
A decoder 14 that outputs a signal and an enable signal for the three-chip circuit 11 is provided.

Note that, as shown in FIG. 2, for example, the exclusive OR circuit 6 includes a circuit including two FOR circuits 6a and 6b and three-chip 1 to buffer circuits 6c and 6d. Parity F
/F circuit 8 state (II l 71 , 11 Q 11
), the written or read parity data is inverted or non-inverted.

Next, the operation of the parity circuit having the above configuration will be explained based on the time charts of FIGS. 3 and 4 and the data and parity data schematic diagrams of FIGS. 5 to 10.

Assuming that data writing is executed based on the write cycle shown in FIG. 3, CPLj 1
An address is outputted at (shown in FIG. 3(b)), and a chip select signal is outputted from the decoder 14 to the memory section 3 based on this address (as shown in FIG. 2(d)). At this time, the timing signal a from the timing circuit 13 is set to "H" level from T□ of the clock (φ) to Tti timing, that is, the most significant bit of the address is set to II HI.
The address is set to I (shown in (i) of the same figure), and while it is at "H", the address indicates the parity area of the memory section 3. On the other hand, the parity generation circuit 7 determines whether the number of ``1'' is odd or even based on the data to be written. For example, if the number is odd, a parity of ``1'' is generated. , if the number is even, a parity of II OII is generated and output to the parity F'/F circuit 8.

Next, the timing circuit 13 outputs the clock (φ)'
■ Since the timing signal C is output at 2 timings, the parity F/I" circuit 8 temporarily stores its 1" or II Orr ((e) and () in the same figure).
f)), this latch data causes the exclusive OR circuit 6 to invert or non-invert the manual data and output it. Furthermore, since the timing signal b, that is, the write enable signal, is set to the "L" level from the timing circuit 13 at the timing Tw of the clock (φ) (as shown in FIG. The data on the data bus 2 that is enabled is converted into parity data via the exclusive OR circuit 6, and a predetermined area of the parity area (address corresponding to the write data) is rewritten with this parity data. In this case, if the parity “king” is generated in the parity generation unit 7,
The data on the data bus 2 is inverted by the exclusive OR circuit 6 and written to the parity area, and the parity is "0".
” is generated, the data on the data bus 2 is directly converted into parity data, and a predetermined area of the parity area is rewritten with this parity data.

Subsequently, after the 1゛w timing of the clock (φ), the timing signal a from the timing circuit 13, that is, the highest binary bit of the address, is set to the ILL L I+ level, and the timing signal b, that is, the write 1- enable signal. is set to the 11L II level at the T timing of the clock (φ) (as shown in (g) in the figure), and the parity F/F circuit 8 is cleared at the rising timing of the first pulse of the timing signal ( (shown in figure (f)).

The exclusive OR circuit 6 operates in a non-inverting manner, and the 11- address indicates the data area of the memory section 3. At this time, the exclusive OR circuit 6 directly outputs the data on the data bus 2 to the memory section 3, so that the write data is written to a predetermined area of the data area.

That is, in the life l-cycle, the clock (φ
Parity is generated at T, , T, , Tω timing of ), inverted or non-inverted parity data is written to the parity area, and non-inverted data is written to the data area after TW of tarok (φ).

On the other hand, in order to read the data in the data area and transfer it by X1, it is assumed that data reading is executed based on the fourth read cycle shown in the same figure. In addition, “1” of the data
If the write data is, for example, 1'11 (H)'', that is, if the number of '1's in the data is an even number, as shown in Figure 5. As shown in the figure, the memory unit 3 is normal and the same data “Sat1” is stored at the specified address in the data area and parity area.
(+1)” has been written in writing 12.

First, the address is output from CPU i ((b) in the same figure).
), and the chip select signal for the memory unit 3 is output from the decoder 14 according to the address (see (d) in the same figure).
). At this time, the timing signal a from the timing circuit 13 is Tx of the clock (ψ) of the CPU 1, r
It is set to II HII level up to T 21 T w, that is, the most significant bits 1 to 1 of the address are set to u I II (
(shown in (i) of the same figure), and since the timing signal a is set to the LL HII level during this read cycle (as shown in (g) of the same figure), the timing signal a becomes LL HI+.
During the level, the address will point to the parity area of the memory section 3. Therefore, parity data 1 in the parity area is read by the above address, but
Since the memory unit 3 is normal, its parity data 1 is 'J l (H)' (as shown in FIG. 2(c)).

Subsequently, the parity generation unit 7 detects whether the number of 1' steps of the read parity data "1 step (H)" is an odd number or an even number. In this case, it is an even number. Therefore, if O in circuit 8,
++ is stored, and the exclusive OR circuit 6 is set to non-inverting output operation. Then, the parity data ↓ passed through the exclusive OR circuit 6 becomes "11 (H)" (parity data 2) as it is (as shown in FIG. 3(c)).

At this time, the timing signal d is output from the timing circuit 13 at Tt++ of the clock (φ) (as shown in FIG.
"11 (H)" is latched by the latch circuit 9 (shown in (k) of the figure). After that, 1 of the clock (φ)
After that, the timing signal d is set to the "L" level, and the output of the parity F/F circuit 8 remains at "O+ level, so the data in the data area of the memory unit 3 is changed according to the address from the CPU 1." 11 (H)" is read out. The read data is directly placed on the data bus 2 via the exclusive OR circuit 6 ((h)
).

Next, the data currently on data bus 2 “” - Wang (
H)” and “11 (H)” of the parity data 2 latched in the latch circuit 9 are compared in the comparator 10, and a match or mismatch signal is sent to the interrupt F/F circuit 12.
The comparison unit 10 outputs a match signal.

At this time, the timing signal d is input BI from the timing circuit 13 at T3 of the clock (φ) ((1) in the same figure).
), and since they match, interrupt F/F circuit 1
2 is not set and no interrupt signal is generated (see the same figure (
(indicated by the dashed line in m)).

By the way, as shown in Fig. 6, for example, the data area is abnormal, and it is not "11 (H)" but "10".
(H)" has been written and the parity area is JE normal. Similarly to the above, the parity data 2 "11 (H)" in the parity area is latched into the latch circuit 9 as is. Then, the data "0 (H)" in the data area is read out and this data is compared with the latched parity data, but in this case a mismatch signal is output to the interrupt F/F circuit 12. , an interrupt signal is output to the CPU.
Interrupt processing is performed by the CPU 1, and based on the comparison unit 10's judgment as to whether or not the number of mismatched pins is one or not, reversal is performed to determine whether the data is different or the validity data is different. be done. In other words, if the number of mismatched bits is -, there is an error in the data, so it is determined that the data "10 (H)" is incorrect, that is, the data area is abnormal, and the parity area is iE normal. be able to. At this time, the enable signal from the decoder 14 releases the floating state of the three-chip 1 to circuit 11, and the parity data ``'1''(+1)'' of the latch +01M9 is output as data (correct data) on the data bus 2. Therefore, it is possible to continue executing the next read cycle.

Furthermore, as shown in FIG. 7, for example, the memory section 3
The parity area is abnormal, and the parity area is “11(H)” instead of “11(H)”.
Assuming that "01 (H)" has been written, the parity data 1 "01 (H)" is read out. Then, since the number of "↓5'" of that data is an odd number, parity generation is performed. The parity "earth" is generated in the circuit 7, so the parity "earth" is generated in the parity/de circuit 8.
Since "F" is stored (as shown by the broken line in FIG. 6(f)), the exclusive OR circuit 6 is set to an inverse output operation, that is, the parity data passing through the exclusive OR circuit 6 is "F". E (H)'' (parity data 2), and this parity data 2 (' F E
()l)”) is latched by the latch circuit 9.

Next, data area data area 11 as shown in -
(H)" is read out, and this data is compared with parity data 2 "FE (II)" of the latch circuit 9.

In this case, since a mismatch signal is obtained, an interrupt is applied to CPLI 1 (as shown by the solid line in FIG. 3(m)).

As a result, the CPU 1 performs an interrupt process, and based on the judgment made by the comparator section (2) 0 as to whether the number of mismatched bits is -, inversion is performed to determine whether the data or parity difference is different. That is, when the number of mismatched bits is seven, it can be determined that the parity area is abnormal and the data area is normal because there is an error in the parity data.

Note that in the above embodiment, the write data II
Although we have explained the case where the number is an even number, the same applies even if the number is an odd number.

First, when the write data is, for example, "01 (H)", that is, when the number of rr 1 n of the data is an odd number, as shown in FIG. 8, if the memory section 3 is normal, The parity area has an inverted FE()1)
” and data 170↓()l)” is written in the data area.

Then, in the same way as above, the parity data in the parity area is read out, but this parity data 1 "l-"
Because the number of "1"s in "E()Iin" is an odd number.

Parity generation section 7 generates parity LL I II.

Then, the parity data 1 ” F' E (II
)” is inverted by the exclusive OR circuit 6 and converted to parity data 2 (Q 1 (H)), which then converts the parity data 2 to cono parity data 2.
O (H) is latched by the latch circuit 9.

Next, data 1101 (H
)" is read and compared with the latched parity data. In this case, a match signal is obtained, so no interrupt is generated on the CPU (see figure (m) ), the read cycle continues.

Further, as shown in FIG. 9, for example, it is assumed that the data area is abnormal and "OO(H)" is written in this data area instead of "01(H)", and the parity area is J , E, parity data 1"F E (H) in the parity area, as in the notebook.
" is inverted and becomes parity data 2"01 (+()", and this parity data 2"'01 (H)" is latched into the latch circuit 9. Then, the data in the data area is "OO(H)". is read out, and this data is compared with the latched parity data.In this case, a mismatch signal is obtained, and an interrupt is applied to CPLI (as shown by the solid line in FIG. 3(m)).

As a result, the CPU 1 performs an interrupt process, and it is determined whether the data or parity data is different based on the determination by the comparison unit 1O as to whether the number of mismatched bits is one. In this case, since the number of mismatched bits is one, it can be determined that the data area is abnormal and the parity area is normal.

Also, as shown in Figure 10, for example, there is an abnormality in the parity area, and 'FF(H)' is written in the parity area instead of '0 (+1)'''). shall be. Then, parity data 1 ” I-
``F(+1)'' is read out, and since the number of 111 IIs of the validity data king is an even number, the parity generation unit 7 generates the parity ``O''. Since the IIO++ is stored in the circuit 8, the exclusive OR circuit 6 performs a non-inverting output operation, and the parity data 1 passed through the exclusive OR circuit 6 is converted into the same parity data 2 "to" F ( H)”
and is latched by the latch circuit 9.

Next, in the same way as above, data “01 (
)l)" is read out and this data is compared with the latched parity data 2. In this case, a mismatch signal is obtained and an interrupt is issued to the CPU 1 (
(Indicated by the solid line in Figure (m)). As a result, an interrupt process is performed in the CPU 1, and a determination as to whether the data or parity data is different is executed based on the determination in the comparator 10 as to whether the number of mismatched bits is one.

In this case, since there are seven mismatches 20-pi1-, it can be determined that there is an error in the parity data, that is, the parity area is abnormal and the data area is normal.

It should be noted that, although the write cycle 1 to cycle in FIG. 3 and the read cycle in FIG. 4 are performed by the microprocessor Z80, the same applies to other systems as well.

[Effects of the Invention] As explained above, according to the parity circuit of the present invention, when writing or reading parity data to a memory having a data area and a parity area,
An exclusive OR circuit that inverts or non-inverts the parity data, a parity generation circuit that generates a parity bit based on the data written to the data area or the read parity data, and an exclusive OR circuit that uses the generated parity bit. A parity F/F" circuit that controls inverted and non-inverted outputs, a latch circuit that latches the parity data read out via its exclusive OR circuit, and a latch circuit that latches the parity data read out through the exclusive OR circuit, and the latched parity data that is currently being read out from the memory. A comparison unit that compares the data and outputs a match or mismatch signal, and an interrupt F/F ++-1 that outputs an interrupt signal to the CPU based on the mismatch signal.
Since it is possible to judge whether or not there is only one unmatched pin 1 through the above comparison, it is possible to omit the parity check memory (storage element: IC) and reduce costs. It is also possible to determine whether there is an abnormality in the data area or parity area, that is, whether the data or parity data is incorrect.

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram of a parity circuit showing an embodiment of the present invention, Fig. 2 is a specific partial circuit diagram of the parity circuit described above, and Figs. 3 and 4 show the operation of the above parity circuit. Time chart diagrams for explanation, Figures 5 to 1
FIG. 0 is a schematic diagram for explaining the contents of a memory used in the parity circuit, and FIG. 11 is a schematic block diagram of a conventional parity circuit. In the figure, 1 is the CPU, 2 is the data bus, and 3 is the memory section (R
AM), 6 is an exclusive OR circuit, 7 is a parity generation circuit, 8 is a parity F/F circuit, 9 is a latch circuit, 11 is a comparison section, 12 is an interrupt F/F circuit, I3 is a timing circuit, 14 is a It is a decoder.

Claims (1)

[Claims] (1) A parity circuit that checks parity when reading memory data and transferring the data, and interrupts the CPU based on the parity check, a data area and a parity area provided in the memory; parity generating means for generating parity based on the data or parity data read from the parity area; and when writing the data as parity data in the parity area according to the parity; Exclusive OR means for inverting or non-inverting the parity data when parity data is read out, and parity data currently read from the data area through the exclusive OR means. Compare with the data,
Comparing means for outputting a match or mismatch signal and determining whether there is at least one mismatch bit, and interrupt signal generating means for outputting an interrupt signal to the CPU based on the mismatch signal. A parity circuit featuring: