JPS554757A - Error control system of memory unit - Google Patents

Error control system of memory unit

Info

Publication number
JPS554757A
JPS554757A JP7779078A JP7779078A JPS554757A JP S554757 A JPS554757 A JP S554757A JP 7779078 A JP7779078 A JP 7779078A JP 7779078 A JP7779078 A JP 7779078A JP S554757 A JPS554757 A JP S554757A
Authority
JP
Japan
Prior art keywords
bit
odd
word
inspection
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7779078A
Other languages
Japanese (ja)
Other versions
JPS5736680B2 (en
Inventor
Tsugio Miyake
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7779078A priority Critical patent/JPS5736680B2/ja
Publication of JPS554757A publication Critical patent/JPS554757A/en
Publication of JPS5736680B2 publication Critical patent/JPS5736680B2/ja
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To control errors well at a control memory unit (CS) read time by adding an odd/even inspection bit to an information bit group and adding further the second odd/even inspection bit to them to form one-word information.
CONSTITUTION: One-bit odd/even inspection bit p1 is added to even-bit information A, and odd/even inspection bit p2 for information A and bit p1 is added to them, thereby forming one word. At a write time, the whole of the word is inverted and is recorded if an error is detected. This word is read and is stored in register 2 through CS1, and odd/even inspection for the whole of the word is performed in odd/even inspection circuit 5; and if the number of bit "1" is even, circuit generates an error signal, and a required error processing such as reread is performed. If contents of register 2 are decided as correct, inversional recording or not is decided by odd/even inspection circuit 6 according to the detection of the odd or even number of bit "1" in the word including information A and bit p1, and inversin circuit 3 is controlled, thus reading out well the recording word by the error control at a CS read time.
COPYRIGHT: (C)1980,JPO&Japio
JP7779078A 1978-06-27 1978-06-27 Expired JPS5736680B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7779078A JPS5736680B2 (en) 1978-06-27 1978-06-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7779078A JPS5736680B2 (en) 1978-06-27 1978-06-27

Publications (2)

Publication Number Publication Date
JPS554757A true JPS554757A (en) 1980-01-14
JPS5736680B2 JPS5736680B2 (en) 1982-08-05

Family

ID=13643769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7779078A Expired JPS5736680B2 (en) 1978-06-27 1978-06-27

Country Status (1)

Country Link
JP (1) JPS5736680B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03186936A (en) * 1989-12-15 1991-08-14 Fujitsu General Ltd Parity circuit
US9075742B2 (en) 2009-09-09 2015-07-07 Kabushiki Kaisha Toshiba Memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03186936A (en) * 1989-12-15 1991-08-14 Fujitsu General Ltd Parity circuit
US9075742B2 (en) 2009-09-09 2015-07-07 Kabushiki Kaisha Toshiba Memory device

Also Published As

Publication number Publication date
JPS5736680B2 (en) 1982-08-05

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