JPH0743668B2 - Access control device - Google Patents

Description

DETAILED DESCRIPTION [Outline] Controlled in response to sending a memory access to a storage unit,
A busy control circuit that sends a busy signal corresponding to a memory bank that is a busy management unit of a storage unit to be accessed,
And a selection circuit for selecting one from memory accesses from a plurality of ports and sending it to the storage unit. In the access control unit for the memory access to the storage unit, the busy control circuit has one timing. For each cycle, the type of the memory access is determined and a busy signal for inhibiting the input to the selection circuit is generated for a predetermined cycle, and a busy signal generated by the preceding memory access and a subsequent memory are generated. The input to the selection circuit is permitted based on the type of access.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory busy check system in a system having a memory access control circuit that processes a plurality of types of memory accesses.

Generally, the storage unit in a computer system, except for the buffer memory, normally reads and writes using several cycles.

During these several cycles, it is necessary to prohibit access to the same area (generally for banks).

In order to perform this access prohibition control, a method is often used in which a busy signal indicating that the area is in use is recognized as being in use while the corresponding memory area is being accessed.

In this method, new memory access refers to the busy signal corresponding to the memory area that the self access request wants to access, and if it is in the unused state, accesses it, and if it is in the used state, waits until it becomes the unused state before accessing. Works like.

There are usually the following three types of memory access. That is, read access.

 All write access.

 Partial write access.

Is.

Is an access for reading the contents of the memory, is an access for rewriting all the processing units (for example, 8 bytes) in the computer system, and is an access for rewriting a part of the processing units.

Conventionally, since there was no problem because only one memory access processing cycle was used after the access request was selected by the access selection circuit, but when selected by the access selection circuit, After reading the data and replacing a part of the data with the write data, a check bit for the new data is generated, and this time, as the full write access, the memory is accessed after being selected again by the selection circuit.

That is, the memory is used for two memory access processing cycles, and the memory access selection circuit is used twice.

Therefore, in the system in which the memory access from many processing devices is processed by one selection circuit, the conventional method using the memory access selection circuit twice as described above does not increase the throughput.

Therefore, in order to solve this problem, there is a method in which the memory access selection circuit is used only once in any of the above-described memory accesses.

According to this method, when the partial write access is selected by the selection circuit, first, the memory data is read and the write access is sent to the storage unit after a certain cycle. Therefore, the timing when the write access is sent to the memory. However, since the partial write access is specified at the time when the partial write access is selected by the selection circuit, there is a problem that the use time for the memory area becomes long, and an effective memory busy check method has been awaited.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional memory access circuit, and FIG. 4 is a time chart showing the access operation at that time. Hereinafter, the same reference numerals denote the same objects or processes throughout the drawings.

First, referring to FIG.
The operation of each memory access will be described.

Memory access from unit 0 is port (UOAC) 1
When this access is selected by the selection circuit (SEL) 2, it is input to the pipe-in T1 and the BUSY control circuit 3. Subsequent operations differ depending on the type of access.

Read access (FETCH): The address portion of the memory access selected by the selection circuit (SEL) 2 is selected by the selector (SEL1) 4 and set in the memory address register (MAR) 5.

Then, the storage unit (MEM) 6 is instructed to read the data, and after a certain time, the read data is set in the read register (MRD) 7 and sent to the access source device.

The operation at this time is shown in FIG. In the figure, MEM ACC indicates an actual memory operation (that is, read operation), and BUSY is a period in which selection of the next new access to the memory area is prohibited.

Full write access (FULL STORE): At the timing of pipeline T2, the write data from the port (UOWD) 9 is set in the register (WDa) 11 by the selector (SEL2) 10 and the check bit is generated by the check bit creation circuit 1c. After being generated, it is set in the write data register (MWD) 8 through the selector (SEL3) 12.

At the same time, the pipeline T3 sets the address part of the access to the memory address register (MAR) 5 through the selector (SEL1) 4 and instructs the memory part (MEM) 6 to write.

The operation at this time is shown in FIG. MEM ACC in this case is a write operation.

Partial write access (PARTIAL STORE): The address part of the access selected by the selection circuit (SEL) 2 is selected by the selector (SEL1) 4 and set in the memory address register (MAR) 5.

Then, the storage unit (MEM) 6 is instructed to read the data, and the data read after a predetermined time is input to the merge circuit (MERGE) 13 through the read data register (MRD) 7 and the shift register. .

On the other hand, the write data is set in the register (WDa) 11 from the port (UOWD) 9 at the timing of the pipeline T2, and passes through the shift register to the merge circuit (MERG).
E) Entered in 13.

In the merge circuit (MERGE) 13, the storage unit (MEM)
Of the data read from 6, the portion designated by the write data is replaced with the write data, and the check bit creation / error check circuit 2c and the register (WD
b) It is set in the write data register (MWD) 8 through 14, the data correction circuit 3c, and the selector (SEL3) 12.

At the same timing as this, the pipeline T8 sets the memory access address section in the memory address register (MAR) 5 through the selector (SEL1) 4,
Writing is instructed to the storage unit (MEM) 6.

The operation at this time is shown in a time chart in FIG. 4 (3).

[Problems to be solved by the invention]

As described above, in the conventional system, as is clear from the time chart shown in FIG. 4, in each memory access-, when the selection circuit (SEL) 2 selects another memory access at the timing shown by BUSY, MEM ACC
Since it may disturb the actual memory operation indicated by
Access to the corresponding memory at that timing was prohibited in the selection circuit (SEL) 2.

However, since the timing at which the memory unit (MEM) 6 is actually used is the timing indicated by MEM ACC, in the conventional method, the extra timing is prohibited.
There was a problem that the efficiency of memory access was significantly reduced.

In view of the above-mentioned conventional drawbacks, the present invention focuses on the fact that the timing at which the memory unit (MEM) 6 is actually used, that is, MEM ACC, is different from the BUSY timing due to the memory access described above, and efficiently. It is an object of the present invention to provide a method for performing a memory busy check to significantly improve the throughput of memory access.

[Means for solving problems]

 FIG. 1 is a diagram showing the concept of the present invention.

The busy mode indicated by a plurality of BUSY signals according to the present invention is shown for each type of access, as shown in FIG.
(D) and (b) read access (FETC
H), and (c) full write access (FULL
STORE), and (d) shows a partial write access (PARTIAL STORE).

(1) to (3) show the relationship between a plurality of memory busy signals according to the present invention and the type of memory access to be prohibited by the busy mode indicated by the busy (BUSY) signals.

As is clear from the figures (1) to (3), in the present invention, the BUSY described above is indicated by a plurality of signals, and
It is configured to indicate the type of memory access to be prohibited by the value indicated by the BUSY signal.

As is clear from this figure, the principle of the present invention is that, in each memory access, the above-mentioned MEM ACC {that is, the timing at which the memory section (MEM) 6 is actually operating} does not overlap each memory. The feature is that other allowable memory access types are defined for the access.

For example, in the case of (b) read access (FETCH), the MEM ACC that actually uses the storage unit 6 is a selection circuit (SEL).
It is between 3τ and 3τ after selection in 2, and BUSY section *
The read access (FETC
H), if the input to the selection circuit (SEL) 2 only for partial write access (PARTIAL STORE) is prohibited, the most efficient memory access can be performed.

In the case of the full write access (FULL STORE) in (c), the MEM ACC that actually uses the storage unit 6 is the selection circuit (SE
L) It is between 6τ and 3τ after the selection in 2, and the access that occurs at the timing shown by the first ◎ in the BUSY section will be overlapped by MEM ACC in any type of access, and all types of memory access are prohibited. It At the timing indicated by *, the read access (FETCH) and partial write access (PARTIAL STOR) that occurred at this timing
The input to the selection circuit (SEL) 2 only for E) may be prohibited.

Similarly, (d) partial write access (PARTIAL
In case of STORE), MEM ACC that actually uses the storage unit 6
Is between the 3τ and 3τ after the selection in the selection circuit (SEL) 2 and 1
It is between 1τ and 3τ, and at the timing shown by * at the beginning of BUSY section, as in (b) Read access (FETCH), read access (FETCH) and partial write access (PARTIAL STO) occurred at this timing
Input to the selection circuit (SEL) 2 only for RE) is prohibited. At the timing shown by ○ below, read access is possible from 6τ to 10τ, and partial write access (PARTIAL STORE) is possible after 14τ.
Only full write access (FULL STORE) should be prohibited. At the subsequent timings indicated by ◎ and *, as in the case of full write access (FULL STORE) in (c), ◎
All access is prohibited at the timing shown by, and only read access (FETCH) and partial write access (PARTIAL STORE) are prohibited at the timing shown by *.

[Action]

That is, according to the present invention, a busy control circuit which is controlled in response to sending of a memory access to a storage unit and sends a busy signal corresponding to a memory bank which is a busy management unit of the storage unit to be accessed; A selection circuit for selecting one of the memory accesses from the port and sending it to the storage unit, and in the access control unit for controlling the memory access to the storage unit, the busy control circuit has one timing cycle. Each time, the type of the memory access is determined and a busy signal for inhibiting the input to the selection circuit is generated for a predetermined cycle, and a busy signal generated by the preceding memory access and a subsequent memory access are generated. Since the control is performed so that the input to the selection circuit is permitted based on the type of Even when the in over time, different types of access, will be accessed is a memory access exists, the effect of the throughput of memory access can be greatly improved.

〔Example〕

 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. The same reference numerals as those in FIG. 3 denote the same objects, and the decoder (DEC) 21, 23 and B0 (bank 0) check circuit 24 are It is a functional block necessary for implementing the present invention.

First, when memory access information is set from the unit 0 to the port (UOAC) 1, the OPC indicating the type of access is set.
Part is decoded by the decoder (DEC) 21, and the bank address part (AD) used for busy management is the decoder (DEC).
C) Decoded by 22.

The decoder (DEC) 21 decodes the type of memory access to be prohibited, which is defined corresponding to the BUSY bits (BIT) 0, 1 in FIG.

That is, in the decoded output, 'F' indicates FETCH access, 'PST' indicates PARTIAL STORE access, 'FST' indicates F
Indicates ULL STORE access.

In the decoder (DEC) 23, bank correspondence (that is, B0
~ B3) outputs the above BUSY bits (BIT) 0, 1 to the above B0
In the (bank 0) check circuit 24, the access prohibition output shown in FIG. 1A can be input to the selection circuit (SEL) 2 by taking the illustrated logic.

As described above, in general, in the case of a system of a method of centrally controlling memory access from a plurality of devices, there is a high possibility that access to the same memory bank will collide. It may be possible to access if the type of access is different, and it is expected that the throughput of memory access can be expected to be greatly improved.

[Effects of the Invention] As described above in detail, in the memory busy check method of the present invention, in the access control circuit for controlling the memory access to the storage unit, a memory busy signal composed of a plurality of bits depending on the type of memory access. By providing a means for generating a busy pattern that can be displayed in a different sequence, it is possible to selectively prohibit the memory access corresponding to the memory busy pattern. Even if it is during the busy period, there is an accessible memory access if the type of access is different, and the memory access throughput can be greatly improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the concept of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional memory access circuit. The figure shows a conventional memory access operation in a time chart. In the drawing, 1 is a port (U0AC, U1AC, U2AC) 2 is a selection circuit (SEL) 3 is a BUSY control circuit 4 is a selector (SEL1) 5 is a memory address register (MAR) 6 is a storage unit (MEM) 7 is read data Register (MRD) 8 Write data register (MWR) 9 is port (U0WD, U1WD, U2WD) 10 is selector (SEL2) 11 is register (WDa) 12 is selector SEL3) 13 is merge circuit (MERGE) 14 is register (WDb ) 21,22,23 are decoders (DEC) 24 are B0 check circuits 1C, 2C, 3C are check circuits, and correction circuits T1, T2, T3 to T8 are pipelines, respectively.

Claims (1)

[Claims] 1. A busy control circuit (3), which is controlled in response to sending of a memory access to a storage unit, and sends a busy signal corresponding to a memory bank, which is a busy management unit of the storage unit to be accessed, and a plurality of bus control circuits. And a selection circuit (2) for selecting one of the memory accesses from the port and sending it to the storage unit, the access control device controlling the memory access to the storage unit, the busy control circuit (3 ) Generates the busy signal for inhibiting the input of the subsequent memory access to the selection circuit (2) by discriminating the type of the preceding memory access for each timing cycle, and is generated by the preceding memory access. The busy signal and the type of the subsequent memory access, and the subsequent memory to the selection circuit (2) every timing cycle. Access control device and permits the input of the access.