JPH0561761A - Main storage control system - Google Patents

Abstract

PURPOSE:To change the control timing of a memory controller without requiring large man-hour and cost in the case of updating a DRAM by comparing control timing information and a stage signal and turning-on the respective signals when they are coincident. CONSTITUTION:A memory controller 2 is equipped with a stage circuit 4 to generate the stage signal by starting the operation when being accessed from a CPU through a memory bus 1, and a timing circuit part 8 to transmit timing information. The timing storage part 8 transmits the timing information to a DRAM signal control part 5, DRAM address control part 6 and DRAM data control part 7 corresponding to the kind of access from the CPU. The respective control parts 5-7 compare the stage signal from the stage circuit 4 with the timing information from the timing storage part 8 and when the compared result is equal, respective output signals to a DRAM 3 are turned on. Therefore, the change of access time due to the change of the DRAM is limited only for the information in the storage part 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory control system, and more particularly to a main memory control system capable of easily changing the control timing of a memory control device for controlling access to a main memory device composed of a DRAM. Regarding

[0002]

2. Description of the Related Art In recent years, as the speed of computer systems has increased, there has been a demand for speeding up of main storage devices. Recently, a DRAM having a high access speed has been developed, and an increasing number of computers use it as a main storage device.

FIG. 6 shows a main memory control system in a computer using a DRAM as a main memory device. Figure 6
In FIG. 1, 1 is a memory bus connected to another main memory or a CPU, and 3 is a DRA used as a main memory
M and 2 ′ are memory control devices for controlling access to the DRAM 3 from the memory bus 1.

The memory controller 2'starts a clock counting operation when it is accessed from the CPU via the memory bus 1, and a stage from the start of access (a time step in which the cycle from the start to the end of the access is represented by a clock cycle). ), Which generates a stage signal indicating that the DRA receives the stage signal from the stage circuit 4.
A DRAM signal control unit 5 ′ that controls control signals such as RAS (row address selection) and CAS (column address selection) of M3, and DR that receives a stage signal from the stage circuit 4
A DRAM address control unit 6'for controlling an AM address signal and a DRA for receiving a stage signal from the stage circuit 4
And a DRAM data control unit 7'for controlling read / write (read / write) data of M3.

The DRAM signal control unit 5 ', the DRAM address control unit 6', and the DRAM data control unit 7'transmit the control signal, the address signal, and the data signal to the DRAM 3 at a predetermined stage timing. It has become.

[0006]

As described above, each control unit 5 ', 6', 7'of the conventional memory control device 2'is
It is made according to the access specifications of RAM3. Therefore, in order to speed up the access by changing the DRAM 3 to a high-speed one, the memory control device 2 ′ must be rebuilt according to the new DRAM 3.

This has a problem that particularly when the memory control device 2'is formed of an LSI, a large number of man-hours and costs are required for new development. The present invention eliminates the above-mentioned drawbacks of the prior art and improves DRA.
An object of the present invention is to provide a main memory control method capable of changing the control timing of the memory control device without requiring a large number of steps and cost when updating M or the like.

[0008]

SUMMARY OF THE INVENTION A main memory control system according to the present invention includes a main memory device composed of a DRAM and a DRAM.
A stage circuit that outputs a stage signal that indicates the stage from the start of access to the memory, and timing information that indicates the ON / OFF timings of control signals, address signals, and data signals for accessing the DRAM in association with the stage are stored. And means for comparing the timing information and the stage signal and controlling the control signal, the address signal and the data signal to be ON when they match.

[0009]

With the above structure, the timing information storing means stores in advance the timing information representing the timings for turning on and off the control signals such as RAS and CAS, the address signals and the data signals necessary for accessing the DRAM in association with the stage. It

The means for controlling compares the timing information regarding each control signal, the address signal and the data signal with the stage signal, and turns on each signal when they match. As a result, even if the DRAM is changed, only the timing information stored in the storage means needs to be changed, and it is not necessary to change the hardware.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows the basic configuration of the present invention. In FIG. 1, 1 is a memory bus connected to another main storage device or CPU, 2 is a memory control device connected to the memory bus 1, and 3 is access control by the memory control device 2 as a main storage device. It is a DRAM that is used.

The memory control device 2 starts operation when accessed by the CPU through the memory bus 1 and generates a stage signal, a stage signal from the stage circuit 4 and a timing from a timing storage unit 8 described later. A DRAM signal control unit 5 that receives information and outputs control signals such as RAS and CAS of the DRAM 3, and a DR that receives the stage signal from the stage circuit 4 and the timing information from the timing storage unit 8 and controls the address of the DRAM 3
A DR which receives the stage signal from the AM address control unit 6 and the stage circuit 4 and the timing information from the timing storage unit 8 and controls the read / write data of the DRAM 3.
It has an AM data control unit 7 and a timing storage unit 8.

The timing storage unit 8 is accessed by the CPU through the memory bus 1 and sends timing information to the control units 5, 6 and 7 according to the type of access.

Each of the control units 5, 6 and 7 compares the stage signal from the stage circuit 4 with the timing information from the timing storage unit 8 and when the comparison results are in agreement, the DRA
Control to turn on each output signal to M3 is performed.

FIG. 2 shows an embodiment of the present invention. In FIG. 2, the start signal line 1 a of the memory bus 1 is connected to the stage counter 14 and the memory bus monitoring unit 15 via the input buffer 9.

When the stage counter 14 receives a start signal indicating the start of access, it starts clock counting and outputs a stage signal represented by 1-8. Upon receiving the start signal, the memory bus monitoring unit 15 enables the address buffer 16, the mode buffer 18, the write data buffer 19, and the buffer 13.

The address input via the address bus 1b is transferred via the input buffer 10 to the address buffer 1
6 is stored. The address buffer 16 is the decoder 1
7 and the address to multiplexer 36. The decoder 17 decodes the address, and the timing storage unit 8
A signal designating a timing information register is sent to.

A mode signal indicating whether the access from the memory bus 1 is a read or a write is input to the mode buffer 18 via the buffer 11. The mode buffer 18 supplies a read signal that is turned on in the read mode and turned off in the write mode as selection signals for the multiplexers 20, 21 and 22 and as an input to each of the AND circuits 23 and 24. ..

The data bus 1d of the memory bus 1 is connected to the data terminal of the DRAM 3 via the input buffer 12, the write data buffer 19 and the output buffer 33, and the data is written from the memory bus 1 to the DRAM 3 via this path. ..

The data bus 1d is connected to the output buffer 1
3, the read buffer 30, and the input buffer 34 are connected to the data terminal of the DRAM 3, and the data is read from the DRAM 3 to the memory bus 1 via this path.

The timing storage unit 8 includes timing information registers 8-1, 8-2, 8-3, 8-4, 8-5, 8-.
6,8-7 and 8-8. The timing information of each signal required for accessing the DRAM 3 is stored in the timing information register designated by the output of the decoder 17.

Timing information registers 8-1, 8-2,
Read RAS on information 8-3 and 8-4 respectively specify the timing to turn on the RAS at the time of read,
Write RAS on information that specifies the timing to turn on the RAS during writing, read RAS off information that specifies the timing to turn off the RAS during reading, write RAS that specifies the timing to turn off the RAS during writing
Off information is stored.

Timing information registers 8-5, 8-6,
8-7 and 8-8 respectively show information regarding the timing of supplying an address during reading, information regarding the timing of supplying an address during writing, information regarding the timing of data during reading, and data during writing. Information about timing is stored.

Timing information registers 8-1 and 8-
2 is connected to the multiplexer 20. The multiplexer 20 reads the read RAS on information or the write R when the read signal from the mode buffer 18 is on or off.
Select AS-on information respectively.

Timing information registers 8-3 and 8-
4 is connected to the multiplexer 21. The multiplexer 21 reads the read RAS off information or the write R when the read signal from the mode buffer 18 is on or off.
AS off information is selected respectively.

Timing information registers 8-5 and 8-
6 is connected to the multiplexer 22. The multiplexer 22 selects the read address information or the write address information when the read signal from the mode buffer 18 is on or off, respectively.

Timing information registers 8-7 and 8-
8 is connected to the other input terminals of the AND circuits 23 and 24, respectively. AND circuits 23 and 24
Respectively select read data information or write data information when the read signal from the mode buffer 18 is on or off.

The outputs of the multiplexers 20, 21 and 22 are connected to the input terminals of the comparators 25, 26 and 27, respectively. The outputs of the AND circuits 23 and 24 are connected to the input terminals of the comparators 28 and 29, respectively.

Comparators 25, 26, 27, 28 and 29
The output terminal of the stage counter 14 is commonly connected to each of the other input terminals of the. Each comparator compares the output of the corresponding multiplexer with the stage signal, and outputs an ON signal when they match.

The output terminals of the comparators 25 and 26 are J
It is connected to the J terminal and the K terminal of the K flip-flop 31, respectively. The Q output signal of the JK flip-flop 31 becomes the RAS signal via the buffer 35.

The RAS signal turns on at the next clock when the match signal from the comparator 25 turns on, and turns off at the next clock when the match signal from the comparator 26 turns on. Turns off.

Multiplexers 20 and 21, comparator 2
5 and 26, flip-flop 31, and buffer 35 form the RAS portion of DRAM signal control unit 5 of FIG. Although the timing information and the control line are shown only for RAS in FIG. 2, the same applies to the other control signals CAS, OE and WE.

The output (address information) of the comparator 27 becomes the J input of the flip-flop 32. When the coincidence signal from the comparator 27 is turned on, the flip-flop 32 turns on the Q output at the next clock. This Q output is
It serves as a selection signal for the multiplexer 36.

The multiplexer 36 inputs the row address and the column address from the address buffer 16,
Either one is selected by the selection signal from the flip-flop 32 and is output to the DRAM 3 via the buffer 37 as a DRAM address signal.

The multiplexer 22, the comparator 27, the flip-flop 32, the multiplexer 36 and the buffer 3
Reference numeral 7 forms the DRAM address control unit 6 in FIG.

The output of the comparator 28 is the read buffer 30.
Control signal. That is, when the output of the comparator 28 is on, the data is read from the DRAM 3 to the memory bus 1 through the read buffer 30.

The output of the comparator 29 becomes a control signal for the output buffer 33. That is, when the output of the comparator 29 is on, the data is sent to the DRAM 3 through the output buffer 33.

The AND circuits 23 and 24, the comparators 28 and 29, and the buffers 30, 33 and 34 are
The DRAM data control unit 7 in FIG. 1 is formed.

The operation of the circuit shown in FIG. 2 will be described below. FIG. 3 is a timing chart showing an example of the write operation.

In FIG. 3, (A) is a clock signal counted by the stage counter 14. (B) is
It is a stage signal output from the stage counter 14 and sets stages 1 to 8.

(C) is a RAS signal, (D) is a CAS signal (all are on at a low level), (E) is an address signal, and (F) is a data signal. 3A to 3F
The timing information is set in advance in the timing information register corresponding to each signal so that each signal of FIG.

First, timing information is input from the memory bus 1 to each timing information register in the following manner.
First, an address is sent out from the memory bus 1 and set in the address buffer 16. This address is decoded by the decoder 17, and as a result, the timing information register in which the timing information should be set is determined.

A mode signal designating writing is set in the mode buffer 18. Next, the timing information from the memory bus 1 is written into the timing information register designated by the decoder 17 via the write data buffer 19.

The timing information is generated according to the timing shown in the timing chart of FIG. 3 as follows. RA
Since S is turned on at the end of stage 1, the write RAS on information of the timing information register 8-2 is set to 1, and the write RAS of the timing information register 8-4 is set.
Off information is set to 7.

Since the address changes from the row address to the column address at the end of stage 2, the write address information of the timing information register 8-6 is set to 2. Since the data is output at the stage 6, the write data information of the timing information register 8-8 is set to 6.

The timing information register to store the write information differs from that to the read information because the operation timing is different between the write operation and the read operation. With the same procedure as above,
Timing information is set in all timing information registers. When all the timing information has been set, D
The RAM 3 can be operated.

Next, the write operation shown in FIG. 3 will be described. From the CPU connected to the memory bus 1 to the DRAM 3
In the case of write access, first, the start signal is turned on, the stage counter 14 starts operating, and the stage count is incremented by 1 for each one clock cycle.

Upon receiving the start signal, the memory bus monitor 15 receives the address buffer 16 and the mode buffer 1.
8 and write data buffer 19 are enabled.
As a result, the address is stored in the address buffer 16, the signal indicating the write mode is stored in the mode buffer 18, and the data is stored in the write data buffer 19.

In this case, since it is a write, the read signal output from the mode buffer 18 is off. Therefore, the multiplexers 20, 21 and 22, and the AND circuits 23 and 24 all select the output of the write-related timing information register.

The control of the RAS signal is performed as follows. In stage 1, the output of the multiplexer 20 matches the stage signal, and the match signal of the comparator 25 turns on.
As a result, the J input of the JK flip-flop 31 turns on, and the RAS signal turns on at the next clock.

At stage 7, the output of the multiplexer 21 matches the stage signal, and the match signal of the comparator 26 turns on. As a result, the K input of the flip-flop 31 turns on, and the RAS signal turns off at the next clock.

Address control is performed as follows. In stage 2, the output of the multiplexer 22 and the stage signal match, and the match signal of the comparator 27 turns on. As a result, the J input of the flip-flop 32 is turned on,
At the next clock, the Q signal turns on and the multiplexer 3
6 is switched, and the DRAM address output changes from the row address to the column address.

Data control is performed as follows. Since the read signal is off, the timing information register 8-
The read data information output of 7 is suppressed by the AND circuit 23 and is not transmitted to the comparator 28. The write data information of the timing information register 8-8 passes through the AND circuit 24 and is compared with the stage signal by the comparator 29.

At the stage 6, the coincidence signal of the comparator 29 is turned on to enable the output buffer 33. As a result, the data stored in the write data buffer 19 is output to the DRAM 3.

The write operation of the circuit of FIG. 2 has been described above. In the read mode, the timing storage unit 8 is used.
By comparing the timing information stored in the read-related timing information register with the stage signal, control is performed in the same manner as in the case of writing.

However, in the case of reading, the comparator 28 operates and the read buffer 30 becomes operable according to the read data information of the timing information register 8-7. On the other hand, the memory bus monitoring unit 15 enables the buffer 13 to operate. As a result, the data is transferred from the DRAM 3 to the memory bus 1 at the timing according to the read data information.

As described above, in the present embodiment, the timing information stored in each timing information register forming the timing storage unit 8 indicates the timing when each signal is turned on or off by the stage number. Then, when each timing information matches the current stage, the corresponding signal is turned on.

By doing so, even if the DRAM is changed, the necessary timing information in the timing information register may be exchanged according to the control timing of the new DRAM, and it is necessary to redesign and manufacture the entire memory control device. There is no.

4 and 5 show another embodiment of the present invention. The present embodiment is an example of page write access of the DRAM 3, and the page access is performed twice by turning the CAS signal on and off twice during eight stages.
FIG. 5 shows waveforms of a clock, a stage signal, a RAS signal, and a CAS signal. FIG. 4 shows a portion related to the CAS signal of the circuit for realizing the timing shown in FIG.

In FIG. 4, the stage counter 14 is
The start signal from the memory bus 1 is counted and the stage signal is output. The decoder 39 decodes the stage signal and outputs the signal SG having the same number as the stage number.
1 to SG8 are output to eight AND circuits 40 to 47.

The timing information register 8-9 is the CAS information at the time of reading, and the timing information register 8-10 is
The CAS information at the time of writing is stored. The output of the timing information register 8-9 or 8-10 is selected by the multiplexer 38 as in the previous embodiment.

The output of the multiplexer 38 is sequentially input to the other input terminals of the AND circuits 40 to 47. The OR circuit 48 takes the logical sum of all outputs of the AND circuits 40 to 47 and outputs the result to the flip-flop 49. The flip-flop 49 is delayed by one clock and is the CAS of the DRAM.
Output a signal.

Write CAS information is formed as follows in accordance with the timing of each signal shown in FIG. Light CAS
Information is formed by 8 bits corresponding to the stage numbers 1-8, and each bit is named CAS1 to CAS8.

CAS1 to CAS8 are 1 when the CAS signal is turned on in the stage next to the corresponding stage,
When it is turned off, it is set to 0. Therefore, in the case of FIG. 5, the CAS information is "00101000", which is stored in the timing information register 8-10.

The operation based on the above write timing information will be described below. As in the embodiment described with reference to FIG. 2, the start signal from the memory bus 1 causes the stage counter 14 to start operating. In this case, since it is a write, the write CA of the timing information register 8-10
The S information is selected by the multiplexer 38, and the above CAS1 to CAS8 are output.

Since the timing information is "00101000", only CAS3 and CAS5 are 1 and the others are 0. First, in stages 1 and 2, SG1 and SG2 are sequentially turned on, but since CAS1 and CAS2 are off, A
The outputs of the ND circuits 40 and 41 are off.

In stage 3, since SG3 and CAS3 are on, the output of the AND circuit 42 is on, and therefore 0.
The output of the R circuit 48 is turned on, and the flip-flop 49
Set. As a result, in the next stage 4, the DRAM 3
The CAS signal of is turned on.

At stage 4, since CAS4 is off, A
The output of the ND circuit 43 is off. CAS on stage 5
Since 5 is on, the output of the AND circuit 44 is on, so the output of the OR circuit 48 is on and the flip-flop 49 is set. As a result, DR in the next stage 6
The CAS signal of AM3 is turned on. In the stage 6-8, the CAS 6-8 is off, and the outputs of the AND circuits 45 to 47 are not on.

When the control signal of the DRAM 3 is turned on and off a plurality of times as in this embodiment, the timing information is formed by a bit string corresponding to the stage signal, and the stage signal and the bit are sequentially compared. Also in this embodiment, DRA
Even if M changes, it is only necessary to change the contents of the timing information register.

In any case, the writing of data to the timing information register may be performed by firmware or the like before using the main storage device. Therefore, if the memory timing changes because the DRAM to be used is changed, the firmware may be changed.

[0071]

According to the present invention, the control signal of the DRAM,
Information regarding each control timing of the address signal and the data signal is stored in the timing storage unit in advance,
Since the timing of the operation of the DRAM is controlled in accordance with this, it is possible to deal with the change of the access timing due to the change of the DRAM only by changing the set value of the timing information stored in the timing storage unit.

Therefore, it is possible to design and manufacture the memory control device in a short period of time without changing the hardware, as the speed of the computer system using the DRAM as the main storage device increases.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 4 is a diagram showing another embodiment of the present invention.

5 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 6 is a diagram for explaining a conventional technique.

[Explanation of symbols]

1 Memory Bus 2, 2'Memory Control Device 3 DRAM 4 Stage Circuit 5, 5'DRAM Signal Control Unit 6, 6'DRAM Address Control Unit 7, 7'DRAM Data Control Unit 8 Timing Storage Unit 8-1 to 8-8 Timing information register 9, 10, 11, 12, 13, 30, 33, 34, 3
5,37 buffer 14 stage counter 15 memory bus monitoring unit 16 address buffer 17,39 decoder 18 mode buffer 19 write data buffer 20, 21, 22, 36, 38 multiplexer 23, 24, 40-47 AND circuit 25-29 comparator 31, 32, 49 Flip-flop 48 OR circuit

Front page continued (72) Inventor Tatsuya Yamaguchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa, Fujitsu Limited Takumi Nonaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Eiji Kanaya 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (1)

[Claims] 1. A main memory comprising a DRAM, a stage circuit which outputs a stage signal indicating a stage from the start of access to the DRAM, a control signal for accessing the DRAM, an address signal, and A unit that stores timing information that represents each ON / OFF timing of a data signal in association with a stage, compares the timing information with the stage signal, and when they match, controls a control signal, an address signal, and a data signal to be ON. And a means for controlling a main memory.