JPH10105457A - Memory control system and memory control circuitt - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control dynamic random access at high speed. SOLUTION: This system is provided with a memory control part 2 whereby m-times of page mode access are automatically executed to DRAM 3 for one time access of CPU 1 in configuration where the data bus width of CPU 1 is the m-fold one (m is a natural number being more than two) as compared with that of DRAM 3. The memory control part 2 identifies CPU access (an address, a read signal and a write signal indicating whether a reading operation or a writing operation and data at the time of the writing operation) in configuration where the data bus width of CPU 1 is the m-fold one as compared with that of DRAM 3. From the identification result, the memory control part 2 performs page mode acceess to DRAM 3 without the intervention of CPU 1. Thus, a dynamic random access in configuration where the data bus width of CPU 1 is the m-fold one as compared with that of a memory is controlled at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory control system and a memory control circuit.

[0002]

2. Description of the Related Art A conventional memory control system of this type is shown in FIG. In FIG. 4, the CPU 1
00 performs access according to the data bus width of the DRAM 103, thereby performing writing and reading to and from the DRAM 103. For example, if the bus width of the CPU 100 is 32
The case where the address of the DRAM 103 is 8 bits will be described as an example. This system includes a CPU 100 serving as a bus master, a DRAM 103 storing data,
A memory control unit 102 controls the DRAM 103 based on information from the CPU 100.

[0005] When writing data to the DRAM 103, the CPU 100 transfers data to the memory control unit 102 by using an 8-bit bus of a 32-bit data bus. The memory control unit 102 writes the 8-bit data to the DRAM 103. Similarly, at the time of reading, the CPU 100 reads 8-bit data from the DRAM 103 via the memory control unit 103.

[0004] In FIG.
As shown in Japanese Patent Publication No. 456, a memory element 112 having an n-bit data bus width is used for a CPU 110 having a 2 × n-bit data bus width. In this system, the CPU 110 has a data bus width of 2 × n (n is a natural number of 1 or more) times, the memory element 112 has a data bus width of n times, and a memory control for enabling the CPU 110 to access the memory element 112. A circuit 113, an address converter 114 for generating an address to the memory element 112,
2 × n-bit CPU data bus of CPU 110, 2 ×
It comprises an upper bus which is a data bus of the upper n bits of the n bits, a lower bus which is a data bus of the lower n bits, and an n-bit memory data bus connected to the memory element.

When the CPU 110 writes 2 × n-bit data to the memory element 112, the n-bit upper data is transferred to the data bus of the CPU 110, the transceiver 118,
The signal is input to the multiplexer 122 via 119. The n-bit lower data is input to the multiplexer 122 via the CPU data bus and the transceivers 118 and 120. Here, the address converter 114 generates, for the memory element 112, an address for storing lower-order data. Further, the memory control circuit 113 outputs a control signal for writing lower-order data to the memory element 112. When the writing of the lower data is completed, the address converter 11
4 generates an address for storing upper data,
The memory control 113 generates a control signal, and
Then, the upper data is written to 12.

At the time of reading, the address converter 114
From the storage address of the lower data of the memory element 11
2 outputs lower data, and stores the lower data in register 1
Hold at 21. After that, the address translator 114
The address of the storage destination of the upper data is output, and the upper data is read from the memory element 122. In the conventional system, the lower data of the register 121 and the memory element 112
The CPU 10 combines the upper data output from the
, The CPU 110 can read 2 × n-bit data.

[0007]

However, in this type of memory system, when the data bus of the CPU is connected to only 1 / n, the CPU writes / reads data, so that the CPU outputs / inputs data n times. In addition, at the time of writing, data is divided into n to generate an address, and the address is written to the DRAM n times. At the time of reading, even if the data is read n times from the DRAM, the data is latched, and the CPU collectively takes in the data,
CP is required because memory access cycles
When reading / writing for the data bus width of U,
There is a problem that a cycle of accessing the DRAM n times is required, and the memory cannot be controlled at high speed.

An object of the present invention is to provide a memory capable of performing dynamic random access control at a high speed when the data bus width of the CPU is m (m is a natural number of 2 or more) times the bus width of the memory. It is to provide a control system and a memory control circuit.

[0009]

SUMMARY OF THE INVENTION
The memory control system and the memory control circuit of the random access memory have a data bus width of the CPU of DRA.
When the configuration is m times the bus width of M, there is provided a memory control means for automatically performing m page mode accesses to the DRAM for one access of the CPU.

When the data bus width of the CPU is m times the bus width of the DRAM, the memory control means accesses the CPU (address, read signal and write signal indicating whether the operation is a read operation or a write operation, a write operation). Time, data). From this identification result, the memory control means
Page mode access to DRAM can be performed without CPU intervention.

This makes it possible to control dynamic random access at a high speed when the data bus width of the CPU is m, which is the bus width of the memory.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configurations of a memory control system and a memory control circuit according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the present invention. Referring to FIG. 1, a CPU 1 having a data bus width of 32 bits as a bus master in this configuration example is used.

In this embodiment, a CPU address 4 as a storage destination of data output from the CPU 1, a CPU data 5 as data actually written or read, and a CPU
1 controls a CPU read signal 6 and a CPU write signal 7 indicating the operation of the bus cycle, a bus cycle signal 8 for notifying the CPU 1 of the end of the operation, and information from the CPU 1. It is the memory control unit 2 that identifies such information and actually controls the memory.

The memory control unit 2 includes a memory address 9 indicating an actual storage destination of the memory, a memory data 10 indicating information to be stored in the memory, an RAS signal 11 indicating a time when row address information is taken into a memory element, a memory A CAS signal 12 indicating the timing of taking column address information into the element, a memory read signal 13 for performing a memory access read / write operation, a memory write signal 14, and memory data 10 are output to the DRAM 3.

Next, a detailed configuration of the memory control unit 2 of FIG. 1 will be described. FIG. 2 is a detailed block diagram showing the inside of the memory control unit 2 of FIG. Referring to FIG.
Fetch CPU address 11 output from PU1,
Address decode / address generator 10 for generating a memory address, and timing generator 1 for fetching and generating control signals for CPU 1 and DRAM 3
2. A data buffer 1 for taking in 32-bit data from the CPU 1 in units of 8-bit data width of the DRAM 3.
3 to 16, latches 8-bit data from the DRAM 3, and outputs the latched data to the data latches 17 to 2 connected to the divided 8-bit data bus of the CPU 1.
It consists of 0.

Next, the operation of the circuits shown in FIGS. 1 and 2 will be described. FIG. 3 is a time chart showing the operation of FIG. 1, and FIG. 3 (1) to FIG.
Consists of data and signals.

First, an operation in which the CPU 1 of FIG. 1 reads memory data from the DRAM 3 will be described with reference to FIG. In FIG. 2, the operation is started (FIG. 3A). At this time, the CPU 1 outputs a row address to the address decode receiving the CPU address 11 (see FIG. 3).
(B)). Next, upon receipt of the output of the read signal 18 from the CPU 1, the timing generator 12 enables the bus cycle signal 2, extends the operation of the CPU 1, and sends a read signal 23 and a RAS signal 21 indicating a read sequence to the DRAM 3. Then, the output is continued until the DRAM access is completed (FIG. 3C). The DRAM 3 shown in FIG. 1 takes in the row address information when the RAS signal 11 falls.

Next, the timing generator 12 shown in FIG.
The address decode / address generator 10 outputs a column address on the memory address from the information of the CPU address 11 (FIG. 3D). After the output of the column address, the timing generator 2 of FIG. 2 outputs a CAS signal 22 to the DRAM 3 (FIG. 3 (F)). The DRAM 3 shown in FIG.
At the fall of 2, the column address information is fetched.
Thereafter, from the output of the row address, the column address information and the read signal, the DRAM 3 outputs the data stored at that address onto the memory data.

When the timing generator 2 of FIG. 2 outputs the memory data on the memory data 17, it outputs a latch signal for causing the data latch 7 to latch the memory data. With this latch signal, the data latch 7
Holds memory data. At this time, the address decode / address generator 10 of FIG. 2 sends the updated column address information to the memory address 12 at the first address (FIG. 3E). After the output of this column address, the timing generator 2 of FIG.
A CAS signal 22 for M is output (FIG. 3 (G)).
The DRAM 3 shown in FIG. 1 takes in column address information when the CAS signal 12 falls. Then DRAM3
Supplies the data stored at that address to the memory data by supplying the above-described row address, newly acquired column address information and a read signal.

After outputting the memory data on the memory data 17, the timing generator 2 outputs a latch signal for causing the data latch 8 to latch the memory data. In response to the latch signal, the data latch 8 causes the generator 1 to output the updated column address information at the first address to the memory address 12 (FIG. 3 (F)). With the operation described above, when the data corresponding to the data width of the CPU 1, that is, 32-bit data is taken into the data latches 17 to 20 in FIG. 2 from the DRAM 13 in FIG. 1, the timing generator 2 outputs the bus access signal 20 Disable. At this time, when the CPU 1 receives the disable signal, the CPU 1 determines the end of the bus cycle, and takes in 32 bits of CPU data, that is, the output data of the data latches 17 to 20 in FIG.

By the above operation, the CPU 1 is not conscious of the operation, and the CPU 1 operates at high speed from the DRAM, ie, in the page mode.
Data of the data width of U1 can be read.

Also, when the CPU 1 of FIG. 1 writes data to the DRAM 3, the address information of the CPU address 11 of FIG.
1. The transition of the CAS signal 22 is the same as in the read operation (FIGS. 3H to 3J). At this time, the write data is output as data 5 in FIG.

The timing generator 12 shown in FIG. 2 enables the data buffer 3 when the first column address is determined (FIG. 1 (l)). Then, the memory data 17
At the top, CPU data 16 (bits 0 to 7) are output,
At that time, the timing generator 12 enables the memory write signal 24 (FIG. 3 (K)).

The DRAM 3 receives the memory write signal 14
Is stored in the address corresponding to the row address and the column address. Thereafter, the address decode / address generator 10 of FIG. 2 outputs the updated column address, and the timing generator 2 enables the data buffer 4 to store the CPU data 17 (bits 8 to 8) on the memory data 17. 15) is output. The DRAM 3 in FIG. 1 stores the data at the next address.

In the above operation, data 14 (bits 23 to 16) and data 15 (bits 3 to 16) shown in FIG.
1 to 24) are sequentially stored. Thus, the CP
It is possible to write data in the DRAM at high speed, that is, in the page mode, without the transfer of data by the U, in the page mode.

The dynamic random data described above
When the data bus width of the CPU 1 is m times the bus width of the DRAM 3, the memory control system and the memory control circuit of the access memory perform m page modes with respect to the DRAM 3 for one access of the CPU 1. -It has a memory control unit 2 that enables automatic access. When the data bus width of the CPU 1 is n times the bus width of the DRAM 3, the memory control unit 2 accesses the CPU 1 (address, a read signal and a write signal indicating whether a read operation or a write operation is performed, , And from the result of the identification, the memory control unit 2
Page mode access to DRAM2 can be performed without the intervention of U1. Thereby, the CPU 1
When the data bus width is m, which is the bus width of the DRAM 3, dynamic random access can be controlled at high speed.

[0027]

According to the invention described above, the CPU
Access from the DRAM, and access to the DRAM by C
Because the page mode access is performed without the intervention of the PU, the CPU can access the DRAM at high speed when the data bus width of the CPU is m times the data bus width of the DRAM (m is a natural number of 2 or more). Becomes

Further, according to the present invention, it is possible to control dynamic random access at a high speed when the data bus width of the CPU is m (m is a natural number of 2 or more) of the memory bus width. Therefore, it is possible to achieve effects such as improvement of transmission efficiency in a system or a circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a memory control system and a memory control circuit of the present invention.

FIG. 2 is a block diagram illustrating a memory control unit of FIG. 1;

FIG. 3 is a time chart showing an outline of the operation of FIG. 2;

FIG. 4 is a diagram showing a configuration according to a conventional technique.

FIG. 5 is a diagram showing a configuration according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Memory control part 3 DRAM 10 Address decode / address generator 12 Timing generator 13-16 Data buffer 17-20 Data latch

Claims (9)

[Claims] 1. A memory control system having a central processing unit and a storage unit for performing storage control, wherein: a storage control unit for controlling the storage unit; and a data bus width of the central processing unit, the storage unit comprising: Identification means for identifying address information of the central processing means by a control signal sent from the storage control means when the data bus width is m times (m is a natural number of 2 or more). A memory control system, wherein data of the central processing unit is read from the storage unit and controlled based on the identification result without intervention of the central processing unit in the storage control unit. 2. The memory control system according to claim 1, further comprising a memory having a data bus width 1 / (2 × m) times the data bus width of said central processing means. 3. A memory control system having a central processing means and a storage means for performing storage control, wherein a storage control means for controlling said storage means, and a data bus width of said central processing means, Identification means for identifying address information of the central processing means by a control signal sent from the storage control means when the data bus width is m times (m is a natural number of 2 or more); A memory control system according to the result, wherein the storage control means performs a page mode access to the storage means using the same row address information located at the lowest position of the data string, without the intervention of the central processing means. . 4. The memory control system according to claim 3, wherein when the central processing means makes one access, data is processed at a high speed by the page mode address. 5. A memory control circuit having a CPU and a memory, wherein a memory control is performed, the memory control circuit controlling the memory, and a data bus width of the CPU is m times a data bus width of the memory. (M is a natural number of 2 or more), and an identification circuit for identifying the address information of the CPU by a control signal sent from the memory control circuit. A memory control circuit for reading and controlling data of the CPU with respect to the memory without intervention of a CPU. 6. The data bus width of said CPU is 1/1.
The memory control circuit according to claim 5, further comprising a memory having a data bus width twice (2 x m) times. 7. A memory control circuit having a CPU and a memory for performing storage control, wherein: a memory control circuit for controlling the memory; and a data bus width of the CPU is m (m An identification circuit for identifying the address information of the CPU by a control signal sent from the memory control circuit when the number is a natural number of 2 or more times. A memory control circuit for performing a page mode access to the memory in common with row address information located at the lowest position of a data string without intervention of a CPU. 8. When one access is made from said CPU,
8. The memory control circuit according to claim 7, wherein data is processed at a high speed by the page mode address. 9. The memory control circuit according to claim 7, wherein said memory comprises a dynamic random access memory.