JPH10161929A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate any external semiconductor device for generating a select signal and to remarkably accelerate the access speed. SOLUTION: Address data for mapping composed of an address for a microcomputer 7 to start setting at the time of initial setting and address to end the setting are outputted to a serial interface part 4 by a serial signal and stored in a register 5 for address compare and initial setting is finished. When the microcomputer 7 outputs the address data at the time of access to a memory 1, an address comparator part 6 compares these address with the address data for mapping in the register 5 for address compare and when these address data are settled within the range of address data for mapping stored in the register 5 for address compare, a chip select signal CS for selecting the memory 1 is outputted to the control circuit of memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an electronic device,
In particular, the present invention relates to a technique that is effective when applied to speeding up access of peripheral devices supporting a microcomputer.

[0002]

2. Description of the Related Art According to studies by the present inventor, for example, a RAM supporting a microcomputer is disclosed.
(Random Access Memory) and RO
When providing a plurality of semiconductor devices as peripheral devices such as M (Read Only Memory), a so-called external address decoder electrically connected to an external bus is provided between the microcomputer and the semiconductor device. A chip select signal which is a selection signal for selecting a specific semiconductor device is generated by the address decoder.

[0003] An example of this type of semiconductor device is described in detail in Kazuo Nakamura (Author), published by CQ Publishing Co., Ltd. on May 1, 1987, "Memory Application from the Basics", page 22. This document describes a chip select input signal in a RAM.

[0004]

However, it has been found by the present inventors that the following problems arise in the generation of the chip select signal by the address decoder as described above.

That is, since the address decoder is external, the processing time of the address decoder becomes a delay time, which hinders the speeding up of the application equipment using the microcomputer.

An object of the present invention is to provide an electronic device which does not require an external semiconductor device for generating a selection signal, and can greatly improve access speed.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the electronic device of the present invention includes a first semiconductor device provided with mapping data generating means for generating mapping data, and a selection signal control means for generating a selection signal based on the mapping data. One or more second semiconductor devices connected to a common bus of the first semiconductor device and arbitrarily selected by a selection signal.

Further, in the electronic device according to the present invention, the selection signal control means may include a serial interface for exchanging mapping data input / output from the first semiconductor device by a serial signal, and an input to the serial interface. A comparison register for storing the mapping data thus obtained, and a comparison between the mapping data stored in the comparison register and access data output from the first semiconductor device at the time of access, so that the access data is mapped data. If it is within the range, the data comparison unit outputs a selection signal.

Further, in the electronic device according to the present invention, the second semiconductor device comprises a semiconductor memory.

As described above, the access time of the first semiconductor device and the access time of the second semiconductor device can be greatly reduced, so that the processing time of the electronic device can be significantly reduced.

Further, since an external semiconductor device for generating the selection signal becomes unnecessary, the cost and the number of components can be reduced, and the maintainability of the electronic device can be improved.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a chip select control unit provided in a memory according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of a connection between a microcomputer and a memory according to an embodiment of the present invention. FIG. 3 is an explanatory diagram of a connection between a microcomputer and a plurality of memories according to an embodiment of the present invention, and FIG. 4 is an explanatory diagram of a format of transfer serial data according to an embodiment of the present invention.

In the present embodiment, a so-called peripheral device S supporting a microcomputer is provided.
A memory (second semiconductor device) 1 composed of a RAM (Static RAM) semiconductor memory includes a basic component 2 that performs operations such as data storage, data read / write, and read operations, and a microcomputer (to be described later).
Is configured by a chip select control unit (selection signal control means) 3 which generates a chip select signal as a selection signal when is selected.

Further, the chip select control section 3 is provided with a serial interface section 4 which is an interface for transmitting and receiving address data by a serial signal.

Further, the chip select control section 3 is provided with an address compare register (comparison register) 5 for storing address data, and is electrically connected to the serial interface section 4.

The chip select control unit 3 compares the address data output from the microcomputer with the address data stored in the address compare register 5, and when they match, the data provided in the basic configuration unit 2. An address comparison unit (data comparison unit) 6 that outputs a chip select signal CS is provided in a control circuit that controls the input / output of the control circuit, and is electrically connected to the control circuit and the address comparison register 5 described above.

Next, the operation of the present embodiment will be described.

First, a microcomputer (first semiconductor device) provided in an electronic device and controlling the electronic device
The connection configuration between the memory 7 and the memory 1 will be described with reference to FIG.

The microcomputer 7 includes a data bus DB for exchanging data between the microcomputer 7 and the memory 1, an address bus AD for transmitting address data for designating an address at the time of access such as reading and writing of data, and data transfer. It is electrically connected to the memory 1 via an external bus which is a wiring formed on a printed wiring board of an electronic device such as a control bus CB for transmitting various signals.

The data bus DB, address bus AD and control bus CB constitute a common bus.

Further, the signal via the data bus DB is
Input / output to / from the basic component 2 of the memory 1 and the address bus A
The signal via D is input to an address comparison unit 6 provided in the basic configuration unit 2 and the chip select control unit 3.

In the control bus CB, a write signal WR instructing data writing and a read signal RD instructing data reading are wired so as to be input to the basic component 2.

Further, similarly, on the control bus CB, the clock signal and the address data of the serial signal which is the mapping data generated by the data generating means 8 provided in the microcomputer 7 are provided in the chip select control section 3. It is wired so as to be input / output to / from the serial interface unit 4.

Here, the generation of the address data by the data generating means 8 is assumed to be input and set by a user by a program.

Next, the processing of the chip select control unit 3 will be described.

First, the microcomputer 7 outputs mapping address data including an address to start setting and an address to end setting at the time of initial setting such as power-on to the serial interface unit 4 via the control bus CB by a serial signal. I do.

Next, the mapping address data is stored in the address compare register 5 via the serial interface unit 4, and the initialization is completed.

Thereafter, when the microcomputer 7 outputs address data via the address bus AD when accessing the memory 1, the address comparison unit 6 compares the address data with the mapping address data stored in the address compare register 5. And if the address data output from the microcomputer 7 is within the range of the mapping address data stored in the address compare register 5, the chip select signal CS for selecting the memory 1 is controlled by the control described above. Output to the circuit.

Next, a case where a plurality of memories are used in an electronic device will be described.

For example, one microcomputer 7
And three memories as SRAM (second semiconductor device)
A case where 1a to 1c are provided in an electronic device as shown in FIG. 3 will be described. In addition, these memories 1a to 1
The internal configuration at c is the same as that of the memory 1 shown in FIG.

First, the microcomputer 7 and the memory 1
Wirings for transmitting address data based on serial signals of a control bus CB for electrically connecting a to 1c are connected in a daisy chain,
The so-called daisy chain connection is formed.

This daisy chain connection is performed by the control bus C
The address data based on the serial signal output from the microcomputer 7 via B is input to the serial interface unit 4 (FIG. 1) of the first memory 1a, and the address data output from the serial interface unit 4 of the memory 1a is 2 It is connected so as to be input to the serial interface unit 4 of the second memory 1b.

The address data output from the serial interface unit 4 of the memory 1b is input to the serial interface unit 4 of the third memory 1c, and the address data output from the serial interface unit 4 of the memory 1b is stored in the microcomputer 7 Connected to be input to the

Therefore, the access between the microcomputer 7 and the memory 1b is performed via the memory 1a, and the access between the microcomputer 7 and the memory 1c is performed via the memories 1a and 1b.

The clock signal CK input via the control bus CB is supplied to the microcomputer 7,
It is wired so as to be input to the memories 1a to 1c.

Here, in FIG. 3, only wires for transmitting the serial data and the clock of the control bus CB are shown, and other wires such as the data bus and the address bus are not shown.

Next, this one microcomputer 7
The processing of the chip select control unit 3 (FIG. 1) provided in the three memories 1a to 1c will be described.

First, in the case of the daisy chain connection, since the memory 1a which is directly connected to the microcomputer 7 is accessed sequentially,
Is transferred serial data (mapping data) TS having a predetermined format at the time of initial setting such as power-on.
To the serial interface unit 4 of the memory 1a via the control bus CB.

Also, it is assumed that the user inputs and sets the mapping data by a program in the same manner as described above.

The transfer serial data TS is formatted in advance as shown in FIG.
A status bit SB consisting of a bit indicating whether or not initial setting has been performed, an error bit for checking whether there is an error in writing and reading, a start address bit TB for storing address data for starting setting, and an address for ending setting. It is composed of end address bits EB for storing data.

Next, in FIG. 2 to FIG. 4, the memory 1a to which the transfer serial data TS has been input stores the address data of the start address bit TB and the end address bit EB in the address compare register 5 of the chip select control unit 3. Store.

Thereafter, the serial interface unit 4
Data indicating that the initialization has been performed is written to the status bit SB, and the transfer serial data TS is output to the memory 1b via the control bus CB.

At this time, the serial interface unit 4 in the memory 1b stores the input transfer serial data TS
It is determined whether or not data indicating that the initial setting has been performed is written in the status bit SB. In this case, since the data indicating that the initialization has been performed is written in the status bit SB by the serial interface unit 4 of the memory 1a, the transfer serial data T
S is output from the serial interface unit 4 to the memory 1c via the control bus CB as it is.

Similarly, in the memory 1c, the serial interface unit 4 determines whether or not data indicating that the initial setting has been performed is written in the status bit SB of the input transfer serial data TS. By outputting the transfer serial data TS to the microcomputer 7 via the control bus CB, the memory 1
The initialization of a is completed. Further, the microcomputer 7 determines that the initial setting of the memory 1a has been completed based on the setting contents of the status bit SB of the input transfer serial data TS.

Next, the microcomputer 7 outputs the transfer serial data TS for initializing the memory 1b to the serial interface unit 4 of the memory 1a via the control bus CB.

Then, the serial interface unit 4 of the memory 1a to which the transfer serial data TS has been input outputs the transfer serial data TS to the serial interface unit 4 of the memory 1b via the control bus CB as it is.

Here, the transfer serial data TS for initializing the memory 1b output from the microcomputer 7 is data in which the status bit SB indicates that the initial setting has not been performed. By setting a bit indicating that the setting has been made in a predetermined register, the memory 1 is determined to have already been initialized.
The serial interface unit 4a of FIG. 4A makes a determination and outputs the transfer serial data TS to the memory 1b as it is.

Next, the memory 1b, to which the transfer serial data TS has been input, stores the address data of the start address bit TB and the end address bit EB in the address compare register 5 of the chip select control section 3, and then stores the data in the serial interface section. 4 writes data indicating that the initialization has been performed to the status bit SB, and outputs the transfer serial data TS to the memory 1c via the control bus CB.

Then, the serial interface unit 4 of the memory 1c determines whether or not data indicating that the initial setting has been performed is written in the status bit SB of the input transfer serial data TS. The data TS is output from the serial interface unit 4 to the memory microcomputer 7 via the control bus CB.

Similarly, in the memory 1c, similarly, the transfer serial data TS output from the microcomputer 7 is transferred to the memory 1a via the memories 1a and 1b.
c, and the initial setting is performed.

When the microcomputer 7 outputs address data via the address bus at the time of access, the address comparing unit 6 compares the address data with the mapping address data stored in the address compare register 5. When the address data output from the microcomputer 7 is within the range of the mapping address data stored in the address compare register 5, the chip select signal CS for selecting the corresponding memory is compared with the addresses of the memories 1a to 1c. The device 6 outputs the signal to the control circuit described above.

Thus, according to the present embodiment, by providing chip select control unit 3 in memories 1 to 1c, an external semiconductor device for generating a chip select signal becomes unnecessary, and access time is greatly reduced. can do.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the above embodiment, a case has been described where a chip select control unit is provided in an SRAM memory as a peripheral device supporting a microcomputer.
(Dynamic RAM), ROM (Read On)
By using a common bus, it is possible to connect to various devices such as a memory and a communication device such as a serial interface and a microcomputer such as a slave processor by using a common bus, and to provide a chip select control unit in a peripheral device that operates by a chip select signal. Even can greatly reduce the access time.

[0058]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the access time between the first semiconductor device and the second semiconductor device can be greatly reduced.

(2) In the present invention, the processing speed of the electronic device can be increased by the above (1).

(3) Further, according to the present invention, since an external semiconductor device for generating a selection signal is not required, the cost and the number of components can be reduced, and the maintainability and productivity of the electronic device can be improved. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of a chip select control unit provided in a memory according to an embodiment of the present invention.

FIG. 2 is a connection explanatory diagram of a microcomputer and a memory according to an embodiment of the present invention.

FIG. 3 is a connection explanatory diagram of a microcomputer and a plurality of memories according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a format of transfer serial data according to an embodiment of the present invention.

[Explanation of symbols]

 1 to 1c Memory (second semiconductor device) 2 Basic configuration unit 3 Chip select control unit (selection signal control unit) 4 Serial interface unit 5 Address compare register (comparison register) 6 Address comparison unit (data comparison unit) 7 Microcomputer (first semiconductor device) 8 data generating means CS chip select signal DB data bus AD address bus CB control bus TS transfer serial data SB status bit TB start address bit EB end address bit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Atsushi Shishido 3274 Hitachi Yonezawa Electronics Co., Ltd., Yanazawa-shi, Yonezawa-shi, Yamagata Prefecture (72) Inventor Masanori Hazuki 3 Yagibashi-Higashi, Yanazawa-shi, Yonezawa-shi, Yamagata 3274 Inside Hitachi Yonezawa Electronics Co., Ltd. (72) Kinzo Umezu, Inventor Kinzo Umezu 3 Yamagata Prefecture Yonezawa City, Oaza Hanazawa, Yagibashi East 3 3274 Hitachi Yonezawa Electronics Co., Ltd. 3274 Hitachi Yonezawa Electronics Co., Ltd. (72) Inventor Masayuki Kato 3274 Hitachi Yonezawa Electronics Co., Ltd.

Claims (3)

[Claims] A first semiconductor device provided with data generating means for generating mapping data; and a selection signal control means for generating a selection signal based on the mapping data, wherein the first semiconductor device has a common configuration. An electronic device, comprising: one or more second semiconductor devices connected to a bus and arbitrarily selected by a selection signal. 2. The electronic device according to claim 1, wherein the selection signal control means exchanges mapping data input / output from the first semiconductor device by a serial signal, and the serial interface. A comparison register storing the mapping data input to the unit, and comparing the mapping data stored in the comparison register with access data output from the first semiconductor device at the time of access; An electronic device, comprising: a data comparison unit that outputs a selection signal if the access data is within the range of the mapping data. 3. The electronic device according to claim 1, wherein the second semiconductor device is a semiconductor memory.