JPH0652039A - Data transfer system - Google Patents

Abstract

PURPOSE:To remarkably shorten transfer time by enabling data transfer from transfer origin memory to transfer destination memory to be performed only in a read-in cycle. CONSTITUTION:When a processor 1 sets a fast transfer mode on a mode selection register 8, a memory selection circuit 5, a read-in selection circuit 6, and a write selection circuit 7 select another input terminals. When the processor 1 outputs the address of a RAM 2 to an address bus 10, a memory selection signal decoded by an address decoder 4 is supplied to the RAM 2 and a RAM 3, which enables both RAMs to make access. When the processor 1 outputs a read-in signal, data is read out of the RAM 2 to a data bus 11, and the read-in selection circuit 6 blocks the input of the read-in signal to the RAM 3, and the write selection circuit 7 sends out the read-in signal to the RAM 3 as a write signal. As a result, the data read out to the data bus 11 is written on the RAM 3, then, the data transfer is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system for transferring data from a transfer source memory to a transfer destination memory by a processor, and more particularly to a read only memory (Read O).
nly Memory (hereinafter, abbreviated as ROM) to random access memory (Random Access)
Memory; hereinafter, abbreviated as RAM) to a data transfer method suitable for transferring data.

[0002]

2. Description of the Related Art Conventionally, in this type of data transfer system, R
Read cycle and RA for reading data from OM
A method of transferring data from the ROM to the RAM has been adopted by alternately performing two cycles of a write cycle for writing data in M.

[0003]

In the above-mentioned conventional data transfer method, two cycles of a read cycle for reading data from the ROM and a write cycle for writing data to the RAM are alternately performed to read data from the ROM.
Large capacity ROM because data was transferred to AM
There is a problem that it takes time to transfer data from the RAM to the RAM.

In view of the above points, an object of the present invention is to provide a data transfer system capable of significantly transferring data by transferring data from a transfer source memory to a transfer destination memory only in a read cycle. To do.

[0005]

The data transfer system of the present invention is a data transfer system in which a processor transfers data from a transfer source memory to a transfer destination memory, and a mode selection for holding a data transfer mode under the control of the processor. A register, and a memory selection circuit for sending a memory selection signal obtained by decoding an address from the processor to the transfer source memory and the transfer destination memory when the data transfer mode held in the mode selection register is a high-speed transfer mode, A read selection circuit that blocks a read signal from the processor to the transfer destination memory when the data transfer mode held in the mode selection register is a high-speed transfer mode; and a data transfer mode held in the mode selection register. In high-speed transfer mode, the processor The read signal to the transfer destination memory and a write select circuit for sending a write signal.

[0006]

According to the data transfer method of the present invention, the mode selection register holds the data transfer mode under the control of the processor, and the memory selection circuit outputs the data transfer mode from the processor when the data transfer mode held in the mode selection register is the high-speed transfer mode. The memory selection signal obtained by decoding the address of is sent to the transfer source memory and transfer destination memory, and when the data transfer mode held by the read selection circuit in the mode selection register is the high-speed transfer mode, read from the processor to the transfer destination memory The signal is blocked, and the read signal from the processor is sent to the transfer destination memory as a write signal when the data transfer mode held in the mode selection register is the high speed transfer mode by the write selection circuit.

[0007]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing the configuration of a data transfer system according to an embodiment of the present invention. The data transfer method according to the present embodiment includes a processor 1, a RAM 2 as a transfer source memory, a RAM 3 as a transfer destination memory, an address decoder 4, a memory selection circuit 5, a read selection circuit 6, and a write selection circuit 7. And mode selection register 8
It consists of and.

The processor 1 is connected to the RAM 2 and the RAM 3 via the data bus 11 and is connected to the address bus 10.
RAM2, RAM3 and address decoder 4 via
It is connected to the. Further, the processor 1 is connected to the read terminal 21 of the RAM 2, one input terminal of the read selection circuit 6 and the other input terminal of the write selection circuit 7 via the read signal line 18, and RA via the write signal line 19.
It is connected to the write terminal 22 of M2 and one input terminal of the write selection circuit 7. Further, the processor 1
It is connected to the input terminal of the mode selection register 8 via the mode setting signal line 26.

The RAM 2 and the RAM 3 are the address bus 1
It has an address space of the number of bits excluding the most significant bit of 0, and is divided by the most significant bit of the address bus 10.

The address decoder 4 includes an address bus 10.
If the most significant bit of the upper address is input and the address points to RAM2, the memory selection signal is output to the memory selection signal line 12, and if the address points to RAM3, the memory selection signal is output to the memory selection signal line 13. . The address decoder 4 is connected to the memory selection terminal 20 of the RAM 2 and the other input terminal of the memory selection circuit 5 via the memory selection signal line 12, and one input terminal of the memory selection circuit 5 via the memory selection signal line 13. It is connected to the.

The memory selection circuit 5 is a circuit for connecting one of the two input terminals to the output terminal according to the level of the control terminal, and the output terminal is the memory selection terminal of the RAM 3 via the selection signal line 15. It is connected to 23.

The read selection circuit 6 is a circuit for connecting one of the two input terminals to the output terminal according to the level of the control terminal, and the "0" level is input to the other input terminal and the output terminal Are connected to the read terminal 24 of the RAM 3 via the selection signal line 16.

The write selection circuit 7 is a circuit for connecting one of the two input terminals to the output terminal according to the level of the control terminal, and the output terminal is the write terminal 25 of the RAM 3 via the selection signal line 17. It is connected to the.

The mode selection register 8 is a register for holding the data transfer mode of the normal transfer mode or the high speed transfer mode, and the output terminal thereof is through the mode selection signal line 14 to select the memory selection circuit 5, the read selection circuit 6 and the write selection. It is connected to the control terminal of the circuit 7. The mode selection signal line 14 shows a "0" level in the normal transfer mode and a "1" level in the high speed transfer mode.

Next, the operation of the data transfer system of the present embodiment thus constructed will be described.

(1) Normal transfer mode

When the processor 1 outputs a mode setting signal for setting the normal transfer mode to the mode setting signal line 26,
The normal transfer mode is set in the mode selection register 8.
As a result, the mode setting signal line 14 becomes "0" level, and the memory selection circuit 5, the read selection circuit 6 and the write selection circuit 7 select the signal input to one of the input terminals from the selection signal lines 15, 16 and 17, respectively. It becomes a state to output to. That is, the memory selection circuit 5 connects the memory selection signal line 13 to the selection signal line 15, the read selection circuit 6 connects the read signal line 18 to the selection signal line 16, and the write selection circuit 7 selects the write signal line 19. Connect to signal line 17.

In the read cycle, the processor 1 first outputs the address indicating the read memory address of the RAM 2 to the address bus 10.

The address decoder 4 includes an address bus 10
Input and decode the most significant bit of the address above, R
The memory selection signal for selecting AM2 is set to the memory selection signal line 1
Output to 2. As a result, the RAM 2 can be accessed. At this time, since the memory selection circuit 5 selects the memory selection signal line 13, the RAM 3 is not accessed.

Next, the processor 1 outputs a read signal to the read signal line 18. As a result, the data is read from the RAM 2 onto the data bus 11, and the processor 1
The data on the data bus 11 is stored in a register (not shown) or the like.

Subsequently, the processor 1 outputs the address indicating the write memory address of the RAM 3 to the address bus 10 in the write cycle.

The address decoder 4 includes an address bus 10
Input and decode the most significant bit of the address above, R
Memory selection signal line 1 for selecting the memory selection signal AM3
Output to 3. The memory selection signal output to the memory selection signal line 13 is sent to the selection signal line 1 via the memory selection circuit 5.
5 is output, and the RAM 3 can be accessed. At this time, the address decoder 4 operates the memory selection signal line 12
Since the memory selection signal is not output to the RAM 2, the RAM 2 is not accessed.

Next, the processor 1 outputs the data stored in the register to the data bus 11 and the write signal to the write signal line 19. As a result, the write signal is supplied to the RAM 3 via the write selection circuit 7 and the selection signal line 17, and the data on the data bus 11 is RA.
Written to M3.

(2) In case of high speed transfer mode

When the processor 1 outputs a mode setting signal for setting the high speed transfer mode to the mode setting signal line 26,
The high speed transfer mode is set in the mode selection register 8.
As a result, the mode selection signal line 14 becomes the "1" level, and the memory selection circuit 5, the read selection circuit 6 and the write selection circuit 7 select the signal input to the other input terminals from the selection signal lines 15, 16 and 17, respectively. It becomes a state to output to. That is, the memory selection circuit 5 connects the memory selection signal line 12 to the selection signal line 15, the read selection circuit 6 connects the “0” level to the selection signal line 16, and the write selection circuit 7 selects the read signal line 18. Connect to signal line 17.

In the read cycle, the processor 1 outputs the address indicating the read memory address of the RAM 2 to the address bus 10.

The address decoder 4 includes an address bus 10
Input and decode the most significant bit of the address above, R
The memory selection signal for selecting AM2 is set to the memory selection signal line 1
Output to 2. Since the memory selection circuit 5 is now selecting the other input terminal, the memory selection signal output to the memory selection signal line 12 selects the RAM 2 and at the same time the RAM 3 via the memory selection circuit 5 and the selection signal line 15.
Select. As a result, it becomes possible to access the RAM 2 and the RAM 3.

Next, the processor 1 outputs a read signal to the read signal line 18. As a result, data is read from the RAM 2 to the data bus 11 and the write selection circuit 7 selects the read signal line 18, so that the read signal is sent as a write signal to the RAM 3 via the write selection circuit 7 and the selection signal line 17. The data supplied to the data bus 11 and read to the data bus 11 is written in the RAM 3.
That is, data is transferred from RAM2 to RAM3. At this time, since the "0" level is input to the read terminal 24 of the RAM 3 via the read selection circuit 6, the read operation of the RAM 3 is prohibited, and the RAM 2 and RA
Data collision with M3 is prevented.

In the above embodiment, the transfer source memory is R
Although the case where the AM2 and the transfer destination memory are the RAM3 has been described, it goes without saying that the present invention can be similarly applied even when the transfer source memory is the ROM.

[0031]

As described above, according to the present invention, by using the memory read cycle of the processor to read data from the transfer source memory and simultaneously write the data to the transfer destination memory, the transfer source memory is transferred to the transfer destination memory. The data can be efficiently transferred, and the transfer time can be significantly shortened.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a data transfer system according to an embodiment of the present invention.

[Explanation of symbols]

 1 processor 2 ROM 3 RAM 4 address decoder 5 memory selection circuit 6 read selection circuit 7 write selection circuit 8 mode selection register 10 address bus 11 data bus 12 memory selection signal line 13 memory selection signal line 14 mode selection signal line 15 selection signal line 16 selection signal line 17 selection signal line 18 read signal line 19 write signal line 20 memory selection terminal 21 read terminal 22 write terminal 23 memory select terminal 24 read terminal 25 write terminal

Claims (1)

[Claims] 1. A data transfer method in which a processor transfers data from a transfer source memory to a transfer destination memory, and a mode selection register that holds a data transfer mode under the control of the processor, and data held in the mode selection register. When the transfer mode is a high-speed transfer mode, a memory selection circuit that sends out a memory selection signal obtained by decoding an address from the processor to the transfer source memory and the transfer destination memory, and a data transfer mode held in the mode selection register A read selection circuit that blocks a read signal from the processor to the transfer destination memory in the case of the high-speed transfer mode, and a read signal from the processor when the data transfer mode held in the mode selection register is the high-speed transfer mode Write to the transfer destination memory Data transfer method characterized by having a write selection circuit for transmitting a signal.