JPH0457287A - Multiport memory - Google Patents

Abstract

PURPOSE:To prevent error in the write/read of information due to simultaneous access by constituting a memory cell area match deciding means so as not to decide match concerning minimal bits among the address information of first and second ports at least. CONSTITUTION:When a DHA signal 40 is 1, an A0 match signal 41 is masked and when a1L signal 3b - A10L signal 3k are equal to A1R signal 9b -A10R signal 9k regardless of whether an A0L signal 3a is match with an A0R signal 9a or not, a memory cell area match internal signal 122 is made active. At such a time, when both an inverted CSL signal 4 and an inverted CSR signal 10 are active, a WAIT generating circuit 23 judges that access from an L side port 100 competes with access from an R side port 101, and outputs an internal control signal 15, internal control signal 16, inverted WAITL signal 7 and inverted WAITR signal 13 so that the port on the side of trying access later to the memory cell area of the same unit can be waited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-port memory having a plurality of ports, such as a dual-port memory.

[Conventional technology]

An example of a conventional multiport memory will be explained with reference to FIG. FIG. 1 is a block diagram of a dual port memory, and FIG. 4 is a circuit diagram of the arbitration circuit shown in FIG. 1 as a conventional example.

In FIG. 1, (1) is a memory cell, (100) is a first port accessible to memory cell (1), and, for example, L side baud F'+ (101) is a first port accessible to memory cell (1). 2 ports, e.g. R side port, (2) is L
Data bus of side port (100), (3) is address bus of L side port (100), (4) is C8 [signal, (5) which activates L side port (100) when '0 level is given. When the #0'' level is given, the L side port (1,0
The IEL signal (6) writes the contents of the data bus (2) of the L side port (100) to the memory cell (1) at the address specified by the address bus (3) of 0). Address bus (
OEL signal that reads the contents of the memory cell (1) at the address specified by 3) to the data bus (2) of the L side port (100), (7) is the same as the address being accessed from the R side port (101). address.

When trying to access simultaneously from the rear side port (100), 20'' level is output, and the L side port (100)
The WAITL signal is used to put the CPU (not shown) that is attempted to be accessed from
101) address bus, (10) is the C8R signal that activates the R side port (101) when 20 level is applied, (11) is the C8R signal that activates the R side port (101) when 20'' level is applied.
101) to the address specified by the address bus (9).
The HER signal (12) that writes the contents of the data bus (8) of the side port (101) writes the contents of the address specified by the address bus (9) of the R side port (101) to the Data bus (8) of port (101)
), (13) is the L side port (1
When attempting to access the same address from the R side port (101) at the same time as the address being accessed from the R side port (101), the #O# level is output and the address being accessed from the R side port (101) is output.
This is a WAITR signal for placing a CPU (not shown) that is attempted to be accessed from the CPU into a waiting state for operation. (14)
The contents of the address bus (3) of the L side port (100), the contents of the address bus (9) of the R side port (101), the C8L signal (4) and the C3R signal (10) are input, and the L The internal control signal (15) of the side port (100) and the R side port (101) is used to prevent the side port (100) and the R side port (101) from accessing the same address of the memory cell (1) at the same time. ), (16)
This is an arbitration circuit that generates the above WAITL signal (7) and WAITR signal (13).

(17) represents the data bus (2) of the L side port (100), the OEL signal (6), the WEL signal (5), and the L side port (100).
The internal control signal (15) of 00) is applied to give data to be written in the memory cell (1) to the memory cell (1),
Receives data read from memory cell (1),
moreover.

The I10 buffer of the L side port (100) provides a control signal to the memory cell (1), and (18) transfers the information on the address bus (3) of the L side port (1,00) to the corresponding memory cell (1). Address decoder of the L side port (100) that converts the address to be selected into the code to be selected, (19)
is the data bus (8) of the R side port (101), the OER signal (12), the WER signal (11), and the R side port (101).
) is added to the internal control signal (16) of the memory cell (
1) I10 buffer of the R side port (101) that provides data to be written to the memory cell (1), receives data read from the memory cell (1), and also provides a control signal to the memory cell (1); (20) is an address buster for multiple R-side ports (101) that converts information on the address bus (9) of the R-side ports (101) into a code for selecting a corresponding address of the memory cell (1).

In addition, the L side port (100) is an I10 buffer (17)
.

It has an address decoder (18), a data bus (2), an address bus (3), and an OEL signal (6).
, WEI, signal (5), C3L signal (4), and WAI signal (7), and the R side port (1
01) has an I10 buffer (19), an address decoder (20), a data bus (8), an address bus (9), an OER signal (12), a WER signal (11), a C3R signal (10), and a WAITR signal. It has (13) terminals.

Next, in FIG. 4 showing details of the conventional arbitration circuit (14), (21) shows the contents of the address bus (3) of the L side port (100) and the address bus (9) of the R side port (101). ) are matched.

Address match determining means 1, which outputs an address match internal signal (22) if the address matches, for example, an address match determining circuit;
Address match internal signal (22), C3L signal (4), and C3R signal (10) are input to (23), and internal control signal (15) of L side port (100) and R side port (1
This is a WAIT generation circuit that outputs an internal control signal (16) of 01), an IAI signal (7), and a WAITR signal (13).

Next, the operation will be explained. Dual port memory is L
If the addresses accessed from the side port (100) and the R side port (101) are not the same, they can be accessed without affecting each other at all, but if you try to access the same address at the same time, simultaneous access is disabled. Mediation will be conducted to prevent this.

First, based on the time chart shown in FIG.

The operation when the L-side port (100) attempts to read from the address that the R-side port (101) is currently accessing for writing will be described.

At time (32), the contents of the L-side address bus (3) and the contents of the R-side address bus (9) match, and.

West [Signal (4) and ■ Signal (10) are both active (“
0'' level), an access conflict occurs, and the address match internal signal (22) becomes active (IW level).

In this case, the address bus (9) of the R side port (Lot)
becomes 80+1 first, and then the side port (100)
address bus (3) or 80+1, access from the L side port (100) is accessed from the R side port (1o1).
) will be in a waiting state until the access from ) is completed.

During this time, the WAITL signal (7
) becomes active ('O' level), and the L side port (
100) is placed in a waiting state.

At time (33), when the WAI signal (7) of the L side port (100) becomes inactive (“1” level), the access contention ends and the waiting port (100) becomes inactive (“1” level).
0) is address A. Read the contents of +1.

Note that in this example, the read address A.

The content of +1 is the data (Dx) previously written from the R side port (101) to address An+1.

Now, in the conventional multi-port memory shown in FIGS. 1 and 4, a memory cell (100) or a second port (101) is connected to a memory cell (100) in a unit of memory cell area spanning a plurality of memory addresses. ), it has a function of determining whether or not the unit memory cell area being accessed from the first port (100) is about to be accessed from the second port (101). Therefore, the second port (101) for the above-mentioned memory cell area being accessed from the first port (100)
It was not possible to prevent access from. i.e. 7
For example, information on a unit of memory cell area that is being written from the first port 1-(100) is read out from the second port (101) as write-completed data, resulting in a problem that the information is erroneously transferred. To prevent this problem, conventionally,
While data is being read or written to the first port (100) or memory cell (1), do not read or write from the second port (101), regardless of which memory cell area is being read or written. like.

The CPU (not shown) connected to the second port (101) side is connected to the memory cell (1) outputted by the CPU (not shown) connected to the first port (100), and status information indicating whether or not it is in an access state. Read the above status information, or is it L, meaning that memory cell (1) is being accessed? When connecting the above-mentioned CPU connected to the second port (101) side,
(not shown), the method was to use software to prevent access to the memory cell (1), but this not only complicates the program but also makes the first port (
There is a problem in that the memory cell (1) cannot be accessed from the second port (101) no matter which address of the memory cell (1) is accessed from the second port (100).

[Invention or problem to be solved]

Dual-port memory, which is an example of conventional multi-port memory, is configured as described above, so access is determined based on a single address, and access is performed in units of memory cell areas spanning multiple memory addresses. In this case, the first port (100) or the second port (101
), it cannot be determined and data may be exchanged incorrectly.

The present invention has been made to solve the above-mentioned problem, and relates to a case where a memory cell area covering a plurality of memory addresses is accessed as a unit.

A means is provided for determining whether or not the unit of the memory cell area that is being accessed from the first port is to be accessed from the second port; The object is to obtain a multiport memory in which writing or reading from only two ports is prevented.

[Means to solve the problem]

The multiport memory according to the present invention includes memory cells;
Partial address information excluding at least the least significant bit of a memory address having a plurality of binary encoded bits, or a memory cell area spanning multiple identical memory addresses as a unit, and read/write operations with memory cells for each memory cell area of this unit. The partial address information of the predetermined unit of memory cell area that the first port is reading or writing is the partial address information of the memory cell area that the second port is reading or writing. A memory cell area-match determining means for determining whether or not there is a match is provided.

[Effect]

In the multi-port memory according to the present invention, the memory cell area coincidence determination means is arranged in the first. The match determination is not made for at least the minimum bit of the address information of the second port, and the output signal of the memory cell area match determination means is used to
Simultaneous access from the second port to a unit of memory cell area consisting of a memory cell area spanning a plurality of memory addresses being accessed by the first port is not performed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a block configuration diagram of a dual port memory, which is the same as that used in explaining the conventional example, but in one embodiment of the present invention, an arbitration circuit (one
4) The internal connection is different from that of the conventional example. FIG. 2 is a circuit diagram showing details of the arbitration circuit (14) in one embodiment of the present invention. In FIG. 2, (40) is a memory cell area of two consecutive memory addresses as a unit memory cell area, and when writing or reading from memory cell (1) for each unit memory cell area, active (21 DAH signal (41) is L
The AOL signal (3a) of the address bus (3) of the side port (100) and the address bus (9) of the R side port (101)
) AOR signal (9a) is input and when both are equal, the output becomes #1 # level, (4
2) is the ALL signal (3b) of the L side port (100) and the R
The AIR signal (9b) of the side port (101) is input and 9
A1-number circuit whose output is #1'' when both are equal;
(51) is the Al0L signal (3k
) and the R side port (101,) AlOR signal (9k) are input, and when both are equal, the output becomes 21''.
-Several circuits.

(52) is the DAH signal (40) and the AO-number circuit (41)
(53) is an OR circuit into which the output signal of
The output signal of the circuit (52) and the output signal of the Al-number circuit (42).

A2 to A9 - output signals of several circuits (not shown);

This is an AND circuit which receives the output signal of the Al0-number circuit (51) and outputs the memory cell area-number circle part signal (122).

Note that the above AO-number circuit (41) to Al0 coincidence circuit (
51), OR circuit (52), and AND circuit (53)
) constitutes the memory cell area match determining means 1, for example, the memory cell area match determining circuit (121).

Next, the operation will be explained. In fig.

When the DAH signal (40) is at #1'' level, the AO match signal (41) is masked and the AOL signal (3a) and AO
Whether the R signal (9a) matches or not, the ALL signal (3b) to Al0L signal (3k) and the AIR signal (9b
) to A1OR signal (9k), the memory cell area-number circle signal (122) becomes active ('1' level), and at this time, both the C8L signal (4) and the C3R signal (10) If it is active ('0' level),
The WAIT generation circuit (23) assumes that accesses from the L-side port (100) and accesses from the R-side port (101) are competing with each other, and the WAIT generation circuit (23) assumes that the access from the L-side port (100) and the access from the R-side port (101) are competing with each other, and that Internal control signal (15), internal control signal (16), W to make the port wait
A-blind [signal (7), WAη1 signal (13) is output.

Note that when the DAH signal (40) is at the 20'' level, the operation is the same as in Figure 4, which shows the conventional example, and the L side port (1
The data on the address bus (3) of 00) and the address bus (9) of the R side port (101) are all the same.

Only when both the C8L signal (4) and the C3R signal (10) are active (“0” level), the WAIT generation circuit (23) accepts access from the L side port (100) and access from the R side port (101). It determines that there is an access conflict and operates.

Next, FIG. 3 shows address A from the L side port (100) in the dual port memory shown in FIGS. 1 and 2. While the memory cell area of two consecutive memory addresses of address 80+1 and address 80+1 are being read out one after another, the address A0+1 is transferred from the R side port (101).
This is a time chart when trying to write data to . In the figure, (60) is the point at which access contention begins.

(61) is the point in time when the access conflict ends.

At time (60), even though the contents of address A are being read from the L side port (100), the contents of address A are being read from the R side port (101). In order to write data (Dx) to +1, the R side address bus (9) is
. +1 and activate the C3R signal (10) (#0
2 level), the memory cell area match judgment circuit (
121) makes the memory cell area match internal signal (122) active ('1' level) and activates the WAIT generation circuit (2).
3) makes the WAITR signal (13) active (0" level) and puts the processor etc. (not shown) connected to the R side port (101) into a waiting state.

At time (61), the address bus (
3) contents or A, +1 to another value (A,, A, +1
At the same time, the C3L signal (4) changed to inactive ('1' level), so the memory cell area match internal signal (122) and the lllAlTR signal (13) became inactive ('1' level). return,
The processor, etc. (not shown) connected to the R-side port (101) that had been kept waiting starts operating, and the R-side port (101) is connected to the R-side port (101).
The contents of the data bus (8) of 1) (Dx) are specified by the address bus (9) of the R side port (101) at address A.
. Write to +1.

Note that in the above embodiment, the memory cell area match determination circuit (
121), the memory cell area of two consecutive memory addresses is taken as a unit memory cell area, and the memory cell area match determination is not performed for the lowest address bit (AO). In contrast to the case where the memory cell area at a memory address higher than that is used as a unit memory cell area, the lowest address bit (
The memory cell area matching may not be determined for the address bits following AO) as well.

〔Effect of the invention〕

In the multi-port memory according to the present invention, the memory cell area coincidence determination means is arranged in the first . Since the configuration is configured so that at least the minimum bit of the address information of the second port is not checked for a match, the first port is accessing a memory cell area that is a unit of memory cell area spanning multiple memory addresses. access is prevented by the output signal of the above-mentioned memory cell area match determining means.

This has the effect of preventing errors in writing and reading information due to simultaneous access.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a dual port memory according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of the arbitration circuit in FIG. 1, and FIG. 3 is an operation of a dual port memory according to an embodiment of the present invention. It is a time chart figure. FIG. 4 is a block diagram showing a conventional arbitration circuit, and FIG. 5 is an operation time chart of a conventional dual port memory. In the figure, (1) is a memory cell, and (100) is an L side port. (101) is an R side port, and (121) is a memory cell area match determination circuit. In Figure 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] Each unit includes a memory cell and a memory cell area extending over a plurality of memory addresses having the same partial address information excluding at least the least significant bit among memory addresses having a plurality of binary encoded bits. a first port and a second port that read from and write to the memory cell; partial address information of the predetermined unit of memory cell area that the first port is reading from or writing to; A multi-port memory comprising: memory area match determination means for determining whether partial address information of a memory cell area to be written matches.