JPS61211786A - Ic card - Google Patents

Abstract

PURPOSE:To read a data without mistake and improve a reliability by storing the same content data in plural memory elements, reading a data comprising bits judged by taking a decision by majority every bit on a data read from the respective elements to make a data. CONSTITUTION:A data of a parallel bit inputted from a terminal through a data bus 5 is converted into a data of a serial bit by a central processing unit 2, and thereafter distributed to data buses 13-15 by a majority circuit 11. The same address signal is supplied to memory elements 8-10 from the central processing unit 2, and in a designated address, the data from data buses 13-15 are written at the same time. By the address signal from the central processing unit 2, the memory elements 8-10 read the data at the same time from the designated same address and supply to the circuit of decision by majority 11. Every bit, the decision by majority is done, the data is converted into the parallel bits by the central processing unit, and thereafter, fed to the terminal through the data bus 5 as a data read from a data memory 7.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an IC card capable of storing data.

[Conventional technology]

In recent years, systems that use cards to conduct product transactions and eliminate the need for direct cash payments have been attracting attention. Cards used in such systems include, for example, magnetic cards with a magnetic sheet attached that are used as cash cards in deposit systems such as banks, and as disclosed in Japanese Patent Application Laid-Open No. 58-28761. An IC card is known in which an I'C chip such as a data processing section or memory is attached, and a data memory is provided so that desired data can be stored.

However, since magnetic cards use magnetic sheets as data memory, and IC cards use RAM as their data memory.
(random access memo IJ) as data memory,
RAM depending on the battery capacity for its data retention
In both cases, there are restrictions on the data that can be stored, making them inconvenient to use.

In response, the present applicant previously proposed an IC card that uses non-volatile FROM (programmable read-only memory) as data memory. This IC card does not require a battery to hold data in the data memory, and therefore the storage capacity of the data memory can be made sufficiently large.

FIG. 2 is a block diagram showing an example of such a conventional IC card, in which 1 is a program memory, 2 is a central processing unit, 3 is a data memory, 4 is an address decoder, 5 is a data bus, and 6 is an address bus. be.

In the figure, a processing program is stored in a program memory 1, and a central processing unit 2 is connected to an address bus 6.
and program memory 1 via address decoder 4.
By sequentially specifying the addresses of , the processing program is fetched from the program memory 1, and data is written and read from the data memory 3. When writing data, data supplied from a terminal (not shown) via the data bus 5 is sent to the data memory 3 specified by an address signal supplied from the central processing unit 2 via the address bus 6 and address decoder 4. is written to the address of In addition, when reading data, the address bus 6 and the address decoder 4 are connected from the central processing bag W2.
A predetermined address of the data memory 3 is designated via
Data read from that address is sent to the terminal via the data bus 5.

[Problem that the invention seeks to solve]

By the way, in such an IC card, if there is a defect in the data memory, correct data will be lost and errors will occur in the data read from the data memory. If a defect in the data memory already exists before the IC card is used, the defect can be detected by writing test data to all addresses in the data memory in advance and reading them out. It is sufficient to avoid writing data to addresses where data errors occur due to defects. however,
If a long period of time passes after data is written, part of the written data may change.If a defect occurs in the data memory, it is difficult to avoid errors in the read data. Can not.

Furthermore, by adding an error detection and correction code to the data and storing it in the data memory, errors in read data can be corrected. However, the error correction ability of this method is limited, and when the number of errors is large, errors remain in the read data. When storing extremely important data in an IC card, errors in read data cannot be tolerated.

Furthermore, if the data memory is damaged or damaged due to external force being applied to the IC card, all stored data may be lost.
Data may not be read out at all due to circuit breakage or the like.

As described above, conventional IC cards have had problems in terms of reliability.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and to provide an IC card that can always read data without error and has improved reliability.

[Means to resolve the problem]

To this end, the present invention uses a plurality of memory elements as a data memory device, stores data of the same content in each of the memory elements, and when reading data from the data memory device, the memory elements are reading out the addresses in which data with the same content at each address has been written, and further determining the bit by taking a majority vote for each bit of the data read out from each of the memory elements,
Data consisting of bits obtained by the determination is used as read data from the data memory device.

(Example〕 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of an IC card according to the present invention, in which 7 is a data memory device, 8.9.10
11 is a memory element, 11 is a majority circuit, 12 is an address bus, and 13, 14, and 15 are data buses. Portions corresponding to those in FIG. 2 are given the same reference numerals, and redundant explanation will be omitted.

In FIG. 1, first, when writing data, parallel bit data input from a terminal (not shown) via a data bus 5 is converted into serial bit data by a central processing word W2. , data bus 1 in majority circuit 11
3, 14, and 15 and simultaneously supplied to memory elements 8, 9, and 10 constituting the data memory device 7. Further, the same address signal is transmitted from the central processing unit 2 to the memory elements 8 through the address bus 6, the address decoder 4, and the address bus 12. Delivered on '9.10. In the memory element 8.9.10, data from the data buses 13, 14.15 are simultaneously written to the address designated by this address signal.

In this way, when data is input via the data bus 5, this data is transferred to the memory elements 8, 9.1 designated by the address signals supplied from the address bus 12.
0 to each address. Therefore, data having the same content is stored in the same addresses of the memory elements 8, 9, and 10.

Next, when reading data from this data memory device 7, central processing unit 2 sends address signals to memory elements 8, 9, and 10 via address bus 6, address decoder 4, and address bus 12. Memory element 8.
9. ,．． At 10, data is simultaneously read out as a serial bit string from the same address designated by this address signal, and is supplied to the majority circuit 11 via data buses j3, 14 and 15, respectively.

The majority circuit 11 determines whether the simultaneously supplied bits of each data have many “1”s or many “0”s, and determines whether the bits are “1” or “0”.
When there are many ``, a ``1'' bit is output, and when there are many ``0'', a ``0'' bit is output, and the majority decision is made for each bit of each data that is supplied simultaneously. The data consisting of bits is converted into parallel bits by the central processing unit 2, and then transferred to the data bus 5 as data read from the data memory device 7.
is sent to the terminal via.

According to this embodiment, since it is almost impossible for memory elements 8, 9, and 10 to have a defect at the same address, memory elements 8, 9, and 10 are almost never defective. ,．． Even if each of the bits 9.10 is defective, at least two bits out of the three bits simultaneously supplied to the majority circuit 11 via the data bus 13.14.15 are correct. Therefore, the data output from the majority circuit 11 is free of errors. Furthermore, even if one of the memory elements 8, 9, 10 is destroyed due to external pressure, or the circuit becomes disconnected and data cannot be read, data can be read from the remaining memory elements. . - This greatly improves the reliability of stored data.

FIG. 3 is a circuit diagram showing a specific example of the majority circuit 11 in FIG. 1, in which 5' is a data bus, 16. .

16□, 1f) 3.17 is tri-state buffer, 1
8. .

18□, 1B3 l is AND gate, 19 is OR circuit,
20 is an input terminal, and parts corresponding to those in FIG. 1 are given the same reference numerals.

A data bus 5' between the central processing unit 2 (FIG. 1) and the majority circuit 11, and a data memory device 7 between the majority circuit 11 and the majority circuit 11.
The data buses 13, 14 and 15 (FIG. 1) each consist of one signal line. A write/read selection signal (hereinafter referred to as W/R select signal) S is supplied from the central processing unit 2 to the input terminal 20 1, thereby causing a tri-state buffer (hereinafter referred to as TS buffer) 16. ~1F
33.17 control.

First, when writing data, the W/R select signal from the input terminal 20 becomes high level (ie, "I"), and the TS buffer]6. ~163 is data bus 1 after all
Connect 3.14.15 to data bus 5'.

On the other hand, the output terminals of the TS buffer 17 and the OR circuit 19 are disconnected from the sound data bus 5'.

Therefore, serial bit data from the central processing unit 2 (FIG. 1) is transferred from the data bus 5' to the TSS buffer 16. ~
163 to the data buses 13, 14.15 and simultaneously to the memory elements 8. 9.10 (Figure 1).

When reading data, W/R from input terminal 20
The select signal becomes low level (i.e. “0”),
TS buffer 16. ~163 is data hash 13.1 respectively
4.15 from the data bus 5', and TSS
The output terminal of the buffer 1 for circuit 19 is connected to the data bus 5'.
Connect to.

Therefore, the data read from the memory elements 8, 9, 10 are supplied in parallel via the data buses 13, 14, 15, but the data on the data bus 13 is
, 1B□, data on the data bus 14 is supplied to AND gates 1B, , 183, and data on the data bus 15 is supplied to AND gates 18□, 183, respectively.

And gate 18. .about.18□ are respectively supplied to the OR circuit 19. Here, the relationship between the data bits simultaneously supplied from the data buses 13, 14, and 15 and the output bits of the OR circuit 19 is shown in the following table.

(Margins below) (Table) As is clear from this table, the level of the output bits of the OR circuit 19 matches the level of the bits that are simultaneously supplied to the data buses 13, 14, and 15, whichever has the largest number of bits.

That is, the levels of these bits are determined by majority decision, and the bits whose level matches the level of the larger number are sent to the OR circuit 19.
obtained from. The output bit of this OR circuit 19 is TS
Buffer 17. Central processing unit 2 via data bus 5'
is supplied to

As described above, in this embodiment, the data memory attachment 7 is made up of three memory elements, but it may be made up of four or more memory elements. In addition, the data memory device 7
Although the majority decision of the data from the computer is configured using hardware, the majority decision may be made using software in the central processing unit 2.

In this case, within the central processing unit 2, data from each memory element is stored in different areas of the internal memory, and an internal register is used to perform a majority decision on each data.

In the above embodiment, data with the same content is stored at the same address of the memory elements 8, 9, and 10, but the data is not limited to this, and may be stored at different addresses. In this case, when reading data, memory elements 8, 9 .
Needless to say, addresses 10 to which data of the same content are written at the same time are designated at the same time.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of pieces of data having the same content are stored in a data memory device, and data pieces having the same content are simultaneously read out from the data memory device to make a majority decision for each bit. Therefore, even if there is an error in any of the data that is read out at the same time, this error can be removed by majority decision, and even if one of the data with the same content cannot be read from the data memory device, , it is possible to provide an IC card that is not a problem in the continuous output of data and has greatly improved reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an IC card according to the present invention, FIG. 2 is a block diagram showing a conventional IC card,
FIG. 3 is a block diagram showing an example of the majority circuit in FIG. 1. 2...Central processing unit, 7...Data memory device, 8
゜9.10. ...Memory element, 11...Majority circuit, 12...Address bus, 13, 14.15...Data bus. 1st Ward 5 2nd Ward 3

Claims (1)

[Claims] In an IC card equipped with a data memory device, the data memory device is composed of a plurality of memory elements configured to store a plurality of pieces of data with the same content, and the data memory device is composed of a plurality of memory elements that store data with the same content, and from each address where the data with the same content is written in the memory element. An IC characterized in that a plurality of data read simultaneously is supplied and a majority circuit is provided to take a majority vote on the plurality of data bit by bit, and the output data of the majority circuit is used as data read from the data memory device. card.