JP2510604B2 - Storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device having a variable storage capacity, and relates to a storage configuration recognition control that facilitates memory expansion.

[Conventional technology]

Conventionally, a system in which the storage capacity is variable depending on the type and number of memory packages mounted in the device is known from Japanese Patent Laid-Open No. 59-148693, and the type and storage capacity of the memory package on the memory package side. By transmitting this information from the memory package to the memory control circuit, the memory package recognizes the memory configuration and controls memories having different capacities.

[Problems to be solved by the invention]

Conventionally, a means for transmitting memory configuration information from a memory package to a memory control circuit is required, and this means is usually achieved by assigning a dedicated signal pin for transmitting memory configuration information to the memory package. Further, when a large amount of information is transmitted, a method of reducing the number of dedicated signal pins by providing a means for coding the memory configuration in the memory package is used.

The above method requires a signal pin or logic for transmitting information other than the information necessary for normal memory access, and has a problem that the memory package and the peripheral portion become large.

Further, in the above method, when sharing a memory package between different devices, a certain restriction is required for the configuration information transmitting means.

An object of the present invention is to provide a plurality of connectors and a plurality of memories having a storage capacity of one or two or more types without exchanging information dedicated to the memory configuration recognition between the memory package and the memory control circuit. An object of the present invention is to provide a memory configuration recognition control method in which a general program can perform continuous memory addressing for any combination with a package and a general program can access the memory without being aware of the memory configuration.

The above-mentioned object is, in the memory control unit, memory configuration storage means for storing the configuration of the memory package, configuration recognition processing state storage means for indicating whether or not a program is currently executing memory configuration recognition processing, and the configuration recognition. When the stored data in the processing state storage means indicates that the configuration recognition processing is in progress,
A memory selection signal is output to one of the plurality of connectors for connecting the memory package according to a part of the information of the memory access address from the upper-level device, and the stored data in the configuration recognition processing state storage means is subjected to the configuration recognition process. When the state is not shown, one of the connected memory packages is selected from the information of a part of the access address from the host device to the storage device and the memory configuration information in the memory configuration storage means, and the memory is selected. A memory configuration control means for outputting a signal, the configuration control program recognizes the memory configuration prior to a normal memory access, and stores the result in the memory configuration storage means, thereby providing a plurality of types of memory packages. This is achieved by making it possible to access any combination of That.

[Action]

When the configuration control program writes the information indicating that the configuration recognition process is being performed in the configuration recognition processing state storage means, the memory configuration control means causes the memory configuration control means to decode a part of the access address regardless of the configuration of the connected memory package. Since the memory selection signal is output to one of the plurality of connectors from, the configuration control program changes the access address, and the write / read access to the memory is performed to compare the write data with the read data. It is possible to determine whether the memory package is connected to the connector being accessed and, if so, what its storage capacity is.

After recognizing the configurations of the memory packages connected to all the connectors by the above method, the recognition result is written in the memory configuration information storage means, and the configuration recognition processing state storage means indicates that the configuration recognition processing is not in progress. The information is written by the configuration control program, and the memory configuration recognition process by the configuration control program ends.

At the time of normal memory access after the end of the configuration recognition process, the memory configuration control unit determines which of the connected memory packages the access address corresponds to, and outputs a control signal for the memory package according to the result.

As a result, without exchanging information used only for recognizing the memory configuration between the memory package and the memory control unit, any one of a plurality of connectors can be provided with one or more predetermined types. When any one of a plurality of memory packages having a storage capacity is connected, the addressing of the memory is made continuous, and the general program can access the memory without directly considering the memory configuration.

〔Example〕

An embodiment of the present invention will be described below in detail with reference to the drawings.

First, the configuration of this embodiment will be described with reference to FIG. In this embodiment, the memory control unit 101 and the connectors [1] to [4] (1
02a-102d), memory packages [1]-[4] (103a
~ 103d). Here, the memory package is a package in which a plurality of memory elements and their peripheral circuit components are mounted on a printed circuit board. There are two types of this memory package, a 4 Mbyte package composed of 1 Mbit dynamic random access memory (DRAM) and a 16 Mbyte package composed of 4 Mbit DRAM. 1] to [4] (102a to 10)
It can be connected to any of 2d). Therefore, as the memory configuration of this embodiment, there are three combinations of unmounted, 4 Mbyte package connection, and 16 Mbyte package connection for each connector, and there are a total of 3 ⁴ = 81 combinations. .

The memory control unit 101 includes a memory configuration information register 104, a configuration recognition flag register 105, a capacity determination circuit 106, a memory package selection circuit 107, RAS signal generation circuits 108a to 108d, a timing generation circuit 109, an address multiplexer 110, address decoders 113 and 114. Composed of. The memory configuration information register 104 is a register readable / writable by a program, and has connectors [1] to [4] (102a
~ 102d) write the configuration information of the memory package connected to the configuration control program. As shown in Fig. 2, this register corresponds to each connector and whether or not a memory package is mounted (INS = 1: mounted, INS = 0: not mounted), the type of memory package (M16 = 1: 16 MB package, M16 = 0:
4M byte package) 2 bits each. The configuration recognition flag register 105 is a program readable / writable register, and when the value “1” is written to this register, the configuration recognition mode is set, and the configuration recognition of the memory can be performed by the program by the procedure described later. The capacity determination circuit 106 receives the data [R0] to [R7] · 117 of the memory configuration information register 104 as input, and identifies the configuration of the memory. The output signal 124 of this circuit consists of capacity information for each connector and total capacity information from connector [1] to each connector. This circuit is the total capacity from the connector [1] to the connector [k] (k = 1,2,3,4) and the part that generates connector-based capacity information 301a to 301d as shown in FIG. Connector [1] Capacitance Discriminating Circuit 303, Connector [1, 2] Capacitance Discriminating Circuit 3 for Generating Configuration Identification Signals 306a to 306d
04, connector [1,2,3] Capacity determination circuit 305, connector [1,2,3
3, 4] The capacity determination circuit 306. Connector [k] (k
= 1,2,3,4), a signal indicating that the xM byte package is connected (x = 0 indicates not mounted) is sk
(X), a signal indicating that the total storage capacity from the connector [1] to the connector [k] is yM bytes is ck (y)
Is represented. The connector [1, ..., k] capacitance determination circuit outputs the output signal ck-1 of the connector [1, ..., k-1] capacitance determination circuit.
It inputs (y) and sk (x) and outputs a ck (y) signal. As an example of this connector [1, ..., k] capacity determination circuit, FIG. 4 shows a connector [1,2,3] capacity determination circuit.
In FIG. 4, 401 is an AND gate, 402 is an OR gate, and hereinafter the same symbols represent the same kind of gates. C2 (0) ~ C2 (32)
Only one of them is "1" (true), which indicates the total capacitance value of the connectors [1] and [2]. This is the capacity of the connector 3, that is, "1" of S3 (0) to S3 (16)
Is a signal indicating the total capacitance value of the connectors [1, 2, 3]. For example, C3 (20) is generated as C3 (20) = C2 (20) * S3 (0) + C2 (16) * S3 (4) + C2 (4) * S3 (16). (• indicates a logical product, and + indicates a logical sum.) The memory package selection circuit 107 includes a decoder [2] · 1.
The 14 output signals 116 and the output signal 124 of the capacity determination circuit 106 are input, and the RAS signals MRAS [1] to M corresponding to each connector are input.
RAS [4] · 119 is output. The decoder [2] decodes the upper 4 bits A22 to A25 of the 26-bit address bus 111 and outputs a decode signal every 4 Mbytes and a decode signal 116 every 16 Mbytes. The decode signal for every 16 Mbytes is produced from the original decode signal for every 4 Mbytes by, for example, an OR gate circuit as shown in FIG. The memory package selection circuit identifies which connector the access address corresponds to the memory package connected to from the decode signal 116 and the memory configuration information.
Generation circuits of MRAS [1] and MRAS [2] are shown in FIGS. 6 and 7. In the figure, M (m to n) is the output signal of the decoder [2] · 114, and indicates that the access address is in the range of at least mM and less than nM. The MRAS [3] and MRAS [4] are generated in the same manner. RAS signal generation circuit 108a-108
d is the output signal CRAS [1] to CRAS of the decoder [1] · 113 that decodes the upper two bits A24 to A25 of the address.
[4] 115 and the output signals MRAS [1] to MRAS [4] 119 of the memory package selection circuit 107 are selected by the data MCHK 118 of the configuration recognition flag register 105, and the RAS signal RAS to the memory package is selected. [1] to RAS [4] · 120 are generated. The timing of the RAS signal is defined by t1 from the timing generation circuit 109. FIG. 8 shows a RAS [1] generation circuit. Address multiplexer 110 is address A
2 to A23 as input, A2 as shown in Fig. 9 and Fig. 10
~ A11 and A22 are row addresses, A12 to A21 and A23 are column addresses, the timing signal t2 from the timing generation circuit 109 switches the row address and the column address, and the address signals MA00 to MA10.
Outputs 3. Since the 1M bit DRAM has 10 address pins and the 4M bit DRAM has 11 address pins, the most significant bit MA10 is not connected to the 4M byte package composed of the 1M bit DRAM. In this embodiment, the data width of the memory is 32 bits (4 bytes),
Since the memory is accessed only in units of 4 bytes, the lower 2 bits A0 and A1 of the address are not used.
The CAS signal 121 and WE signal 122 to the memory package are commonly connected to all connectors.

Next, the operation of this embodiment will be described with reference to the case where the connector [1] is not connected,
An example will be described in which the connector [2] is connected to a 16 Mbyte package, the connector [3] is not connected, and the connector [4] is connected to a 4 Mbyte package.

In this embodiment, a memory configuration recognition process is performed by the configuration control program at the time of system initialization. This step is
This is as shown in the flowchart of the figure. First, the memory configuration recognition mode is instructed by writing the value "1" to the configuration recognition flag register 105 (step 1101). As a result, MCHK in FIG. 8 becomes "1", and CRAS [1] to [4] output from the decoders [1] and 113 are selected as the RAS signal. At this time, since the upper 2 bits A24 and A25 of the address are decoded as shown in FIG. 10, by changing A24 and A25, regardless of the memory package configuration,
RAS [1] to RAS [4] are output to the connectors [1] to [4]. In this state, when data is written / read to the address'0000000'X (hexadecimal display) (step 1102), RAS
Although [1] is output, since the connector [1] is not mounted in this example, the write data and the read data do not match (step 1103), and it is found that the connector [1] is not connected. . Next, the same access is made to the address'1000000'X. In this example, since the memory package is connected to the connector [2], the write data matches the read data. Write'AAAAAAAA'X at address '13FFFFC'X, write'55555555'X at address 1'FFFFFC'X, and read address'13FFFFC'X (step 1104), and in this example, to connector [2].
Since a 16MB package is connected, '13FFFF
The C'X address and the '1FFFFFC'X address are distinguished, and the read data is'AAAAAAAA'X (step 1105), which shows that the 16-Mbyte package is connected to the connector [2]. Similarly, when the configuration recognition is performed for the connector [3] and the connector [4], the connector [3] is not connected,
Since the 4M byte package is connected to connector [4], A22 and A23 in Fig. 8 are ignored and '33FFFFC'X
The address and '3FFFFFC'X address indicate the same address on the memory package, and the result of the processing in step 1105 is' 5555555.
It becomes 5'X, and it can be seen that the 4 Mbyte package is connected to the connector [4].

Next, the memory configuration information obtained as a result of the above processing is written in the memory configuration information register 104 (step 110).
6). In this example, R2, R3, and R6 in FIG. 2 are set to "1", and R0, R1, R4, and
R5 and R7 become “0”. Finally the configuration recognition flag register 105
"0" is written to the memory to cancel the memory configuration recognition mode (step 1107), and the memory configuration recognition processing by the configuration control program ends.

When a value is written in the memory configuration information register 104, the output of the capacity determination circuit 106 is S1 as shown in FIG.
(0), S2 (16), S3 (0), S4 (4), C1 (0), C2 (1
6), C3 (16) and C4 (20) signals become "1". The correspondence between memory packages and addresses in this example is as shown in FIG. In this example, since the connector [1] and the connector [3] are not connected, the 16M byte package of the connector [2] is assigned to addresses 0 to 16M, and the 4M byte package of the connector [4] is assigned to addresses 16 to 20M.

In this example, the address is
Considering the case of accessing 13M, the decoder [2] .1
In the output of 14, M (12 to 16) and M (0 to 16) are "1". At this time, the output of the AND gate 701 in FIG. 7 becomes "1", and MRAS [2] is output. When the value MCHK of the configuration recognition flag register 105 is “0”, the RAS signal selection circuit 108a to
Since MRAS [1] to [4] are selected as RAS signals by 108d, in this case, RAS [2] is output and the first
According to the address assignment shown in Fig. 2, the 16Mbyte package connected to connector [2] is accessed.

According to the present embodiment, continuous address allocation is possible for any combination of the connector and the memory package, and the general program can perform memory access without being aware of the memory configuration. Further, since the interface signal between the memory control circuit and the memory package may be only the address, data, and memory control signals, a signal dedicated to recognizing the memory configuration is unnecessary, and the memory package can be configured by only the memory element and the driver.
The storage device can be made inexpensive and small, and the memory package can be easily shared between different types of devices.

In addition, although the example in which the DRAM is used as the memory is described in the present embodiment, the same effect can be obtained even when the static random access memory (SRAM) is used. Further, in the present embodiment, the RAS is connected to the connector [3].
[3], RAS [4] are given, and in addition to the 4M byte package and 16M byte package to the connector [3], 8M byte package and 2 16M byte package which are 2 4M byte packages mounted in 1 package It is possible to connect a 32 Mbyte package in which a single package is mounted, and a configuration without using the connector [4] is also possible.

〔The invention's effect〕

According to the present invention, one type or two types having different storage capacities
Since consecutive addresses can be assigned to any combination of more than one type of memory package and a plurality of connectors, a general program can perform memory access without being aware of the memory configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a conceptual diagram showing the contents of a memory configuration information register, FIG. 3 is a block diagram of a capacity discriminating circuit, and FIG. 4 is a connector [1, ... k] A diagram showing an example of the capacitance discrimination circuit, FIG. 5 is a diagram showing a part of the address decoding circuit, FIGS. 6 and 7 are a logic diagram of a part of the memory package selection circuit, and FIG. 8 is a RAS.
Partial logic diagram of the signal generation circuit, FIG. 9 is a conceptual diagram of address allocation, FIG. 10 is a conceptual diagram of address allocation in the memory configuration recognition mode, FIG. 11 is a flowchart showing a memory configuration recognition method, and 12 The figure is a conceptual diagram showing the correspondence between memory packages and addresses. 101 ... Memory control unit, 102 ... connector, 103 ... Memory package, 104 ... Memory configuration information register, 105 ...
... Configuration recognition flag register, 106 ... Capacity determination circuit, 107
... Memory package selection circuit, 108 ... RAS signal generation circuit, 109 ... Timing generation circuit, 110 ... Address multiplexer, 111 ... Address bus, 112 ... Data bus, 113 ... Decoder [1], 114 ... … Decorator [2],
115 ... Decoder [1] output signal, 116 ... Decoder [2] output signal, 117 ... Memory configuration information register output data, 118 ... Configuration recognition flag register output data, 119 ... Memory package selection circuit output Signal, 120 ...
… RAS signal, 121 …… CAS signal, 122 …… WE signal, 123 ……
Memory address signal, 301 ...... Capacity signal by connector, 302
...... Connector [1] Capacity determination circuit, 303 ...... Connector [1, 2] Capacity determination circuit, 304 …… Connector [1, 2, 3] Capacity determination circuit, 305 …… Connector [1, 2, 3, 4 ] Capacity determination circuit,
306 …… Configuration identification signal, 401,701 …… AND gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaharu Gushiken 1 Horiyamashita No. 1 Horiyamashita, Hadano City, Kanagawa Prefecture Inside the Kanagawa Plant, Hitachi, Ltd. (56) References JP 61-129792 (JP, A) JP 60- 150146 (JP, A) JP 60-220441 (JP, A) JP 62-74137 (JP, A) Actually opened 61-176654 (JP, U)

Claims (1)

(57) [Claims] 1. A plurality of memory packages, a plurality of connectors for connecting the plurality of memory packages, and a host device, for connecting and controlling the memory packages via the connectors. A storage device having a memory control unit, wherein the memory control unit operates in the host device, a memory configuration storage unit that stores the presence / absence of a memory package and the mounted memory capacity corresponding to each of the plurality of connectors. According to the memory access address from the host device, a configuration recognition processing state storage unit that stores information indicating whether the program is currently executing the memory configuration recognition process based on an instruction of the configuration control program. Memory configuration control means for outputting a memory selection signal, and timing control means for controlling the timing of memory access Equipped with
A memory configuration recognition result by the configuration control program is stored in the memory configuration storage unit according to the configuration control program, and the memory configuration control unit includes a decoding unit that decodes a memory access address from the host device; Capacity determining means for inputting the memory information of the configuration storing means and outputting a signal representing a memory capacity corresponding to each connector and an integrated value of the memory capacity from the first connector to each connector, an output signal of the decoding means and the above The storage information of the configuration recognition processing state storage means is provided with memory package selection means for generating a memory selection signal to the connector by inputting the output signal of the capacity determination means and the storage information of the configuration recognition processing state storage means. Indicates that the memory configuration recognition process is in progress, A memory selection signal is output to one of the plurality of connectors according to a part of the information of the memory access address, and the stored information of the configuration recognition processing state storage means is not in the memory configuration recognition process. In the case shown, one of the memory packages connected to the plurality of connectors is selected from the partial information of the memory access address from the higher-level device and the stored information in the memory configuration storage means, and the memory is selected. A storage device which outputs a signal.