JPS60150146A - Main memory selector of electronic computer - Google Patents

Abstract

PURPOSE:To attain the package of main memories of different memory capacities with no initialization by storing the packing states of those main memories by a microprogram and controlling the access after deciding the allocation of addresses. CONSTITUTION:Memory boards M1, M2, M3 are packed with memory capacities 1, 4 and 16M bytes respectively. The capacity information IS1a and IS1b sends the value (1, 0) to a central processor 10. While the information IS2a and IS2b sends the value (0, 1) to the processor 10. In an initialization mode and a rise mode of a computer system, a microprogram 14 reads successively the capacity information given from each memory board and sends the memory packing state information to a mapper 16. The mapper 16 sets an address allocating function in response to the memory capacity of each memory board. In other words, the mapper 16 receives a memory address MA and decodes it. Then the information which decides a significant one of memory board selection signals SL1-SLn is written and set to the mapper 16.

Description

[Detailed Description of the Invention] ゛ [Technical Field of the Invention] □ The present invention provides a main memory selection device for an electronic computer, and in particular a method for transmitting address selection signals to both types of main memory devices having different storage capacities. This is a main memory selection device that dynamically relocates.

[Prior art]

FIG. 1 is a block diagram showing a conventional main memory selection device of a computer. In the figure, ylO is the central processing unit of the computer, M, to Mn are memory IDs representing the mounting unit of the main memory device, and 12 is a block diagram showing a main memory selection device of a conventional computer. This is a decoding circuit for memory board selection provided within the central processing unit 10. A memory address signal MA for accessing the main memory is input to the decoding circuit 12, and the memory address signal MA is decoded to output memory board selection signals SL, 8Ln through signal lines L1 to Ln. Memory board M, ~
Send to Mn.

Next, to explain the operation, when the central processing unit 10 accesses the data at a required memory address, it inputs the target memory address signal MA to the decoding circuit 12 and outputs the memory board selection signal SL. ,
- One SLi in SLn is considered significant. Depending on how busy you are,
The corresponding memory board Mi is selected and this is connected to the signal line L.
It is accessed by the central processing unit 10 via i.

The main memory selection device of a conventional electronic computer is configured as described above, and is configured to allocate memory addresses by the decoding circuit 12 as described above, and furthermore, the internal circuit of the decoder 12 is fixed. Since the memory address MA and the memory port F selection signals SL, . For example, if you use a mixture of memory ports such as Nonoite, IM, Nonoite, and 4Mbyte on the 512, you will be limited to the memory capacity that matches the memory board with the smallest memory capacity. [Summary of the Invention] This invention has been made in order to improve this drawback.
During initial settings, a microprogram in the central processing unit reads the storage capacity of multiple main storage devices, stores the beauty status of the main storage devices, and allocates addresses to each of the main storage devices based on the stored information. By setting circuit constants that determine The present invention proposes a main memory selection device for an electronic computer that can be accessed.

[Embodiments of the invention]

FIG. 2 shows one embodiment of the present invention, which includes a microprogram 14 in the central processing unit 10 that reads the storage capacity of a plurality of memory boards M, -Mn at the time of initial setting and performs necessary processing. A microprogram 14 writes and sets constants for mounting information of the memory boats M1 to Mn, and a mapper 16 is provided that allocates memory addresses MA based on the set constants.

On the other hand, each memory port rM, to Mn receives, for example, 2-bit capacity notification information I5I representing their unique storage capacity.
It has a built-in signal generation circuit so that it can send out the asI8tb-ISNa and SNb, and these capacity notification information 5ffia11S and b-ISnallSnb automatically connect to the signal line when the memory boards M and M-Mn are installed. Rin, B
, Rtb-Rnal are also sent to the microprogram 14 via nb.

Therefore, the microprogram 14 includes each signal gland,
Capacity notification information 151a sent to 〜几n.

By sequentially reading (1)S, b-ISna, and (2)Snb, it is possible to determine the current mounting state of the memory boards rM, .about.Mn. Then, the microprogram 14 sets a constant for row 5 for address distribution in the Matsuper 16 based on the memory implementation state information, sends this to the Matsuper 16 via the information sending line 18, and sets the constant of the Matsuper 16. is mounted on the memory board M, % M n
Set according to the storage capacity.

Next, the operation will be explained. Now, in FIG. 2, memory boards M, , M, and M are mounted, and their storage capacities are IM/ite, 4 MB, and 16 MB, respectively.
M) In this case, capacity notification information■
S, ~■S, are output as shown in FIG. That is, the capacity of memory board M1, notification information l5ia,
■Ssb is (1,0), memory board M2 capacity notification information IS, a, I Stb &-! C011) and memory board M, capacity notification information Is, a, Is, b
are the values of (1, 1) respectively on the signal lines R, a, R, b~”3a
, Rsb to the central processing unit 1o, and the memory boards M4 to Mn are mounted (. ) to the signal line “4 a s Ra b
~ Rna Sends to the central processing unit IO via a and Rnb.

Thus, during the initial settings when starting up the computer system, the microprogram 14 configures each memory port M,
-Capacity notification information from M n■Sla, IS, b~I
Sna, I 8nb are sequentially read, and memory mounting state information representing the storage capacity of the currently mounted memory boards M1 to Mn is sent to Matsupa ξ-1 via the information transmission line 18.
6, and the address allocation of the mapper 16 sets the function according to the storage capacity of the memory boards M, to Mn. That is, when the mapper 16 receives the memory address MA, it decodes it and outputs the memory date selection signal S.
Information determining which signal among L1 to SLn is to be made significant is written and set in the mapper 16.

The relationship between the memory address MA and the memory board selection signal at this time is as shown in FIG.
o o o o o o~X', 00 F F F F
Up to F, the memory board selection signal 8L1 becomes significant.
Memory address X'0100000 to X'04FFFF
The memory date selection signal 8Lt becomes significant until f'',
Furthermore, memory board xX'0500000~X'14F
The memory board selection signal SL becomes significant until FFFF.

Note that in the above embodiment, the memory board PM, -Mn
Capacity notification information I from 8. a, Is, b, I S
As explained above, when na and l5nb have 2 pits, by setting the capacity notification information to arbitrary m bits, memory boards M and ~Mn having (2vn-1) different storage capacities can be used. First, it becomes possible to control access from the central processing unit.

As explained above, the present invention uses a microphone program in a central processing unit to read the storage capacity of a plurality of main storage devices at the time of initial setting, store the mounting state of the main storage devices, and store the mounting state of the main storage devices based on the storage information. By setting the circuit constants that determine the address distribution of each main memory device, the central processing unit is configured to control access to each main memory device, so memory boards that configure main memory devices with different storage capacities can be It can be implemented without any physical initial settings, and the combination and order of memory boards can be selected arbitrarily, allowing the main memory to be used effectively without any restrictions. If you can do it, it will have an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing one example of current collection according to the present invention, and FIG. 3 shows an example of a memory board and the relationship between the value of capacity notification information at that time. The table shown in FIG. 4 is an explanatory diagram showing the relationship between memory addresses and memory board selection signals. In the figure, 10 is the central processing unit, M+ -Mn is the memory board 1.14 is the microprogram, and 16 is the Matsupart.
1Ll ~Ln, RrB, Rtb-几n
asRnb is a signal line, and 18 is an information transmission line. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Patent attorney Masuo Oiwa (2 others) Figure 3 Figure 4

Claims (1)

[Claims] (1) At the time of initial setting, a microprogram installed in the central processing unit of an electronic computer reads the storage capacity of multiple main memories/devices, memorizes the implementation status of the main memory, and An electronic device whose main feature is to control access to each of the main storage devices by the central processing unit by setting a circuit constant that determines the allocation of addresses to each of the main storage devices based on storage information. Computer main memory selection device.