JPS5916064A - Shared memory device - Google Patents

Abstract

PURPOSE:To access data shared among computers in an unused area in a memory area effectively, by receiving tap information added to address information from each computer system and performing access control over the 1st and 2nd memories. CONSTITUTION:A memory 13 is stored with data to be shared among plural computer systems and a memory 14 is stored with indirect address information for accessing the memory 13 indirectly. Then, a multiplexer 23 discriminates tag information added to direct address information outputted by each computer system to control access to the memories 13 and 14. When tag signals on signal lines 17 and 18 are both ''0'', the memory 13 is accessed directly and when the tag signal on the signal line 17 is ''1'', only the memory 14 is accessed directly. When the tag signal on the signal line 18 is ''1'', the memory 13 is accessed indirectly by the address information read out of the memory 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a simple and highly practical shared memory device shared by a plurality of computer systems.

[Technical background of the invention and its problems]

With the diversification of information processing and the development of distributed processing technology, a computer complex system has been developed in which data common to multiple computer systems is stored in a shared memory device, and the multiple computer systems are connected using this shared memory device. It is being This type of system is generally located at a physically distant location from the computer systems and shared memory device t, and access to the shared memory device by each system becomes complicated. Usually, the access is made using the absolute address tone. For this reason, each computer system often retains the above absolute address information within its execution program.
Changing the address location in the shared memory device accessed by the execution program requires changing the program itself, which is extremely difficult. Moreover, if a part of the shared memory device becomes unusable due to a failure, etc., there is a problem that the entire function of multiple computer systems that share this shared memory device may be impaired. .

Furthermore, data shared among multiple computer systems does not necessarily need to be always prepared in a shared memory device. In other words, data to be shared need only exist in the shared memory device when it is needed among multiple computer systems, and at that point, an unused area in the shared memory device is allocated and that area is used. Sharing data is sufficient to achieve that goal. If such control is performed, the shared memory device can be used effectively, its capacity can be reduced, and the cost of the device can be kept low.

However, as mentioned above, since access is fixed by absolute addresses, it is extremely difficult to dynamically change the location of shared data, and it also requires a large amount of memory and a complex address control device. There were problems such as.

[Purpose of the invention]

The present invention has been developed in consideration of these circumstances, and its purpose is to freely allocate data shared between multiple computer systems to unused areas within the memory area. The object of the present invention is to provide a shared memory device that is simple and highly practical.

[Summary of the invention]

The present invention includes a first memory that stores data shared among a plurality of computer systems, a second memory that stores indirect address information for indirectly accessing the first memory, and address information that is accessed from the computer system. A shared memory device is constituted by a control section that accesses the first and second memories according to the tag information for identifying the access mode given in addition to the tag information, and when the tag/information is in the first state, the control section configures a shared memory device. The first memory is directly accessed, the second memory is directly accessed when in the second state, and the second memory is accessed and read when the history is neither the first nor second state. The first memory is accessed indirectly using indirect address information.

〔Effect of the invention〕

Therefore, according to the present invention, the first memory for storing data and the second memory for storing indirect addresses can each be directly accessed, and the indirect address read by accessing the second memory can be used to access the first memory. Since the memory of the computer can be accessed indirectly, it is possible to arbitrarily allocate the storage location of the shared data without changing the programs in each computer system. Moreover, since the shared data can be stored in a required location only at the time when the shared data is needed, the capacity of the shared data can be effectively utilized and the amount of shared memory can be saved. In addition, even if a failure occurs in a part of the shared memory, addresses can be allocated avoiding the failure area, which has a great practical effect, such as preventing problems such as the failure of the entire system. is played.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a computer complex system consisting of a plurality of computer systems 2m, 2b to 2n connected using a shared memory device 1. As shown in FIG.

That is, a plurality of computer systems 2 m + 2 b to 2 n
, signal line 3 consisting of data line, address line, control line, etc.
a, connected to the shared memory device 1 via 3b to 3n;
This allows the shared memory device 11 to be used in each computer system 2.
m, 2b to 2n share the information to form a composite system.

The shared memory device 1 according to the present invention used in such a complex system is configured as shown in FIG. 2, for example. That is, the selection circuit 11 selects a plurality of computer systems 2th, 2b to 2n, and couples the shared memory device 1 to the computer systems 2a, 2b to 2n. Address information, data, etc. are transferred to a memory, which will be described later, through this selection circuit 11. This selection circuit 11 is composed of a multiplexer, a line buffer, etc., and is realized in the same manner as in the conventional device. A first memory 13 for storing shared data and a second memory 14 for storing indirect address information are connected to the data bus 12 of this selection circuit 11, respectively. These first and second memories 13 and 14 are selectively addressed and accessed in accordance with address information provided by the computer systems 2m, 2b to 2n via the selection circuit 11. Note that this address information is divided into an upper bit group and a lower bit group and given via address lines 15 and 16.

Further, the computer systems 2m, 2b to 2n add tag information to the address information and provide it to the shared memory device 1. These six tag terminal signals consist of a 2-bit g signal transmitted by signal lines 17 and 18, respectively, and
The tag signal is applied to a gate circuit 19 and simultaneously inverted via an inverter circuit 20 and then applied to a gate circuit 21. As a result, gate circuit 1
9.21 are reciprocally opened so that a write signal (access control signal) applied via the signal line 22 is applied to the first memory 13 or the second memory 14. , and the tag signal on the signal line 18 is applied to a multiplexer 23. This multiplexer 23 selects the upper bit group of the address information or the indirect address information read out from the second memory 14, combines it with the lower bit group of the address information, and supplies it to the first memory 13. It is. Direct access and indirect access to the first memory 13 are controlled by the function of the multiplexer 23.

Next, the operation of the apparatus configured as described above will be explained with reference to FIGS. 3 to 5. Now, "θ" is given as the tag signal on the signal line 17, and "1" is given to the write signal 11. Then, since only the gate circuit 21 is open, only the first memory 13 is written. A signal is given. Also, during this write, the tag signal on the signal line 18 is “
0″′, and as a result, the multiplexer 23
Address information of the upper bit group of address line 15-1- is selected. As a result, the first memory 13 is directly addressed by the address information given by the computer systems 2m, 2b to 2n, and the booter on the data bus 12 is written to the access address.

Further, at the time of such a write, if the tag signal on the signal line 17 is "1", only the gate circuit 19 is opened this time, and the write signal is given to the second memory 14. By this, the second memory 14
is addressed by the upper bit group of the address information, and data on the data bus 12 is written to the access address. In this case, the data carried on the data bus 12 is indirect address information for indirectly accessing the first memory 13.

In this way, with the tag signal t on the signal line 18 set to "0", the tag signal on the signal line 11 is set to "θ", and a mode indicating the first access mode is set; A mode indicating a second access mode is set by setting the tag signal of "1" to "1". Then, in the first access mode, the memory 13 of the whistle I is directly accessed by the address information, and in the second access mode, The second memory 14 is address information (upper bit group)
directly accessed by

Further, when the tag signal on the signal line 18 becomes "1" during writing, the multiplexer 23 sends the data to the second memory 14 instead of the upper bit group data of the address information.
The indirect address information to be read from is selected. This second memory 14 reads out indirect address information stored in advance at an address accessed by the directly given address information (upper bit group), thereby changing the address information. . By changing this address information, the first memory! 3 is accessed indirectly.

Further, when accessing to read data from the first and second memories 13 and 14, the write signal is set to "O". This write signal is inverted by the inverter circuit 24 and applied to the gate circuits 25 and 26. Furthermore, the gate circuit 25 receives the tag signal on the signal line 17, and the gate circuit 26 receives the tag signal from the inverter circuit 20. Inverted signals are applied to each. As a result, gate circuit 2
5, when the write signal 22 is "θ" and the tag signal on the signal #77 is "1", its output becomes "1"', and outputs the read data of the second memory 14 to the data bus 12, The gate circuit 26 is configured so that the write signal 22 is "0"',
And when the tag signal is "C", its output becomes "1"', and the read data of the first memory 13 is read out.
2, and data read access is performed. In the case of reading from the first memory 13 as well, direct access and indirect access are controlled by the tag signal on the signal line 18, as in the writing described above.

As mentioned above, depending on the state of the two tag signals, the first
And the access form to the second memory x3.14 is controlled. In other words, signal line 17.1
When the tag signal on the signal line 17 is "0", the first memory 13 is directly accessed as the first access mode, and when the tag signal on the signal line 17 is "1", the first memory 13 is directly accessed as the second access mode. Only the second memory 14 is directly accessed. Further, when the tag code on the signal line 18 is "1", the first memory 13 is accessed indirectly using the address information 3 successively output from the second memory 14. ing. Note that the first memory 1
By being able to directly access PAL 1, the memory 13 of PAL 1 can be accessed before writing indirect address information to the second memory 14, making it easy to test the memory.

Incidentally, the address space of the thus configured shared memory device 1 viewed from the computer systems 2a, 2b to 2n is as shown in space 27 in FIG. That is, it has a capacity of, for example, 24 bits and 16 Mbytes, and an address space of 4096 blocks divided into 4 byte size blocks. One block in such an address space can be specified by using the upper 12 bits of the 24-bit address information.

In contrast, the first memory 13, which is generally a shared memory
The capacity of
If an address is expressed in 20 bits, it is possible to set 256 byte-sized blocks fc1, and these blocks are specified using the upper 8 bits of the 20-bit address information. becomes possible.

However, since the actual address space of the first memory 13 is smaller than the address space seen from the computer system 2*+2b to 2n, rCyl
It is necessary to associate each block at the time point 2 of each Acmo Accessory with each block on the actual first memory 13. Therefore, the correspondence is made, for example, as shown by the arrow in FIG. The memory 14 of @2 stores the table showing this correspondence.
For example, as shown in FIG. 4, it is constructed by storing data of the upper eight bits of address information. The above-mentioned correspondence relationship is shown by ↓ between each address (block seen from the computer system) of this second memory 14 and the address information for the first memory 13 stored at each address,
This causes the first memory 1. -3 will be indirectly addressed and accessed.

That is, assume that the computer systems 2a, 2b to 2n are given a total of 24 bits of address information to the shared memory device 1, consisting of the upper 12 bits indicating the block number and the lower 12 bits indicating the address within the block. do.

The second memory 14 is accessed by the data of the upper 12 bits of such address information, and the indirect address information stored at that address is output 7. This indirect address information indicates the block number to be accessed in the first memory 13, and the address information is thereby converted. A block of the first memory 13 is accessed using this converted address information, and the address in the block is
2-bit data will be accessed. This concept is schematically illustrated in FIG. In this way, as shown in FIG. 3, it becomes possible to allocate and store data shared among a plurality of computer systems 2h, 2b to 2n to arbitrary addresses, and each computer system 2
In 2b to 2n, it is possible to access the shared data without changing the execution program.

In addition, the number of customers in the second memory 14 for the address information conversion may be 4K x 8 bits in the above example, and L
This can be achieved with one SI memory. Furthermore, data rewriting in the second memory 14 can be performed in exactly the same way as in the case of a normal memory, making it possible to easily configure the entire device.

Note that the present invention is not limited to the above embodiments, and the number of bits of address information and its data format may be determined according to specifications. Further, indirect access may be performed using all of the converted address information. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a computer complex system, FIG. 2 is a schematic configuration diagram of an embodiment of the present invention, and FIGS. 3 to 5 are diagrams for explaining the form of address information conversion. 1... Shared memory device, 2 a e 2 b ~ 2n.
...Computer system, 11...Selection circuit, 12...
data bus, 13...first memory, 14...second
memory, 15.16--address signal familiarization, 17.1
8... Signal line (tag information), 19, 21, 25° 26
...gate circuit, 20.24...inverter circuit,
23...Multiplexer.

Claims (1)

[Claims] a first memory that stores data shared between multiple computer systems; a second memory that stores indirect address information for indirectly accessing the first memory;
an access control unit that controls access to the first and second memories by determining tag information for access type identification added to direct address information output by each of the computer systems; The unit directly accesses the first memory using the direct address information when the tag information is in a first state, and accesses the second memory using the direct address information when the tag information is in a second state. When the tag information is not in either the first or second state, the second memory is accessed using the direct address information, and the indirect address information read from the second memory is accessed. A shared memory device, characterized in that the shared memory device accesses the first memory.