JPH0160864B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a multi-controller system in which a plurality of controllers are connected to each other via a transmission bus and data is exchanged between these controllers. In general, in this type of system, it is desirable to increase not only the data transfer rate on the transmission bus but also the overall transfer rate up to the time of sending and receiving data from each controller, that is, the effective transfer rate. .

[Prior art and its problems]

FIG. 1 is a block diagram showing an outline of a conventional controller. As is clear from the figure, the controller 1 is composed of a data transmitting/receiving device (also referred to as a data transfer device) 2 equipped with a buffer memory, a system memory 3, etc., and the data transfer device 2 and memory 3 are connected to each other within the system. are connected via a bus (system bus) 4. In addition, 5
is a transmission bus, and when configuring a multi-controller system, a plurality of controllers are installed in parallel on this transmission bus 5.

In other words, data transmission is performed from the system memory 3.
The data stored in a predetermined area of the system bus 4
This is done by transferring the data to a buffer memory in the transmitting/receiving device via the buffer memory, and then transmitting the data from the buffer memory via the transmission bus 5. On the other hand, data reception is performed by storing the received data in a buffer memory within the transmitting/receiving device and then transferring it to a predetermined area of the memory 3 via the system bus 4. Therefore, this method requires time to transfer data between the buffer memory and the system memory, and has the disadvantage that the data transfer speed decreases by that amount.

[Purpose of the invention]

This invention was made in view of these points,
It is an object of the present invention to provide a multi-controller system that can improve data transfer speed and easily write and read transfer data.

[Key points of the invention]

The key point is that the memory of the transfer device is configured with a pair of dual port memories that can be accessed from both the system bus and the transmission bus, and that this pair of memories is divided into blocks according to the number of controllers. When one block is transmitting data, the other block writes data, and when the remaining blocks are receiving data, the corresponding other block reads data. be.

[Embodiments of the invention]

Fig. 2 is a configuration diagram showing an embodiment of this invention;
This figure is a block diagram showing a specific configuration of the memory switching circuit and control circuit of FIG. 2. As shown in FIG. 2, this embodiment has a controller 1 ₁
The main data transfer device 2 ₁ is the system bus 4
and transmission bus 5 (reading, writing)
It is characterized in that it is composed of a pair of possible dual port memories 6, 7, switching circuits 8, 9, and a control circuit 10 for the switching circuit. It goes without saying that the other controllers 1 ₂ and 1 _N arranged in parallel on the transmission bus 5 are also configured in the same manner. Further, the data processing section and the like of the controller 1 are omitted from illustration. Each dual port memory 6, 7 is divided into a plurality of blocks B11 to B1N and B21 to B2N according to the number of controllers. For example, blocks B1N and B2N serve as data transmission or transmission data write areas for controller N, Other blocks B11, B12
. . , B21, B22 . . . are areas for receiving data for the controller N or reading out received data. The switching circuits 8 and 9 connect the system bus 4 to each block of the dual port memories 6 and 7, respectively.
The switching control circuit 10 controls the connection of both buses to the same block of the same dual port memory at the same time. That is, dual port memory 7
When block B2N of memory 6 is connected to transmission bus 5 via switching circuit 8, block B1N of memory 6 is connected to system bus 4 via switching circuit 9.

Here, the data transfer operation between the controller 1 and the controller 2 will be explained.

Now, block B12 of memory 6 is connected to transmission bus 5.
Furthermore, assuming that block B22 of memory 7 is connected to system bus 4, data transferred from controller 2 to controller 1, that is, data received by controller 1, is received by block B12 of memory 1. Ru. At this time, the previously received data is read from block B22 of the memory 7. When it is confirmed that the data received by the block B12 is correct by an appropriate means (not shown), the switching control circuit 10 and the switching circuits 8 and 9 switch the bus as shown by the broken line, and the memory 6 The block B12 of the memory 7 is connected to the system bus 4, and the block B22 of the memory 7 is connected to the transmission bus 5.
The data received by the block B22 can be read out via the system bus 4 and the block B22 can be prepared for receiving data.

The case where data is received from controller 2 has been explained above, but from controller 1 to 2
When transmitting data to , it can be done in the same manner as above. In this case, the blocks used are B11 and B21, and when one is transmitting, the desired data is transferred from controller 1 to controller 2 by alternately performing an operation of writing transmission data to the other. Can be sent.

By doing so, there is no need for data transfer between the buffer memory and the system memory as in the prior art, which provides the advantage of increasing the effective transfer speed. In addition, data sent and received by each controller connected to the transmission bus can be referenced by accessing the memory access image, that is, the memory block corresponding to the controller number, which has the advantage of simplifying data reading and writing. It is something.

FIG. 3 is a block diagram showing a specific example of a memory switching control circuit and a switching circuit. In the same figure,
11 is an address (address 1) when accessing dual port memories 6 and 7 from the transmission bus.
This is an address switching circuit between the address (address 2) and the address when accessing from the system bus.
If addresses 1 and 2 are input at the same time, one address will be accepted with a predetermined priority,
The other address is configured to wait until processing for this address is completed.
Reference numeral 12 denotes a block number storage memory that outputs a block number corresponding to an address. Reference numeral 13 denotes a bit memory that stores dual port memory switching information corresponding to the block number output from the block number storage memory 12, and an example of its configuration is shown in FIG. Here, if blocks B11 and B21 in FIG. 2 are defined as block numbers "1", blocks B12 and B22 are defined as block numbers "2", and blocks B1N and B2N are defined as block numbers "N", The contents of the switching information storage bit memory 13 are changed according to the position of the switch in the switch 9 as shown in FIG. That is, if the block in the dual port memory 6 is connected to the system bus 4 (or the block in the dual port memory 7 is connected to the transmission bus 5), it is "0", and if the block in the dual port memory 6 is connected to the transmission bus 5 ( Alternatively, switching information of "1" is stored for blocks in the dual port memory 7 that are connected to the system bus 4).
Therefore, the contents of the switching information storage bit memory 13 indicate the states of the switches in the switching circuits 8 and 9 of FIG. Note that 14, 16, and 17 are inversion gates, and 15 is a non-inversion gate. When the dual port memory is being accessed from the system bus 4, the inverting gate 16
Valid when signal B is applied, which is output based on the access signal (inverts the input signal and outputs it)
Therefore, the non-inverting gate 15 becomes valid when the signal A that is output based on the access signal is applied when the dual port memory is being accessed from the transmission bus 5 (the input signal is output as is). This is the result. Inversion gate 14
is made valid (the input signal is inverted and output) by a switching command output for each block upon completion of reception and completion of writing of transmission data, and the contents of the switching information storage bit memory 13 are inverted and written.

Here, the operation will be explained by taking as an example the case where address N of the dual port memory is accessed from the system bus 4 or the transmission bus 5.

First, when accessing from the system bus 4, the address switching circuit 11
address) becomes the address of the block number storage memory 12. At this time, for example, if address N is assigned to block number "1", the block number storage memory 12 outputs block number "1". This becomes the address of the switching information storage bit memory 13, and when this bit memory 13 is as shown in FIG. 4, "1" stored at the address of block number "1" is output. At this time, since the access is from the system bus 4, signal B is applied to the inverting gate 16.
is valid, and the "1" output from the switching information storage bit memory 13 is inverted by the inverting gate 16 and becomes "0". Therefore, a signal of "0" is applied to the dual port memory 6, and a signal of "1" inverted by the inverting gate 17 is applied to the dual port memory 7. only selected. Address 2 from address switching circuit 11 is simultaneously input to dual port memories 6 and 7, but since only dual port memory 6 is selected, access to block B11 in FIG. 2 corresponding to block number "1" is disabled. is performed from the system bus 4. When the access is completed, the switching command enables the inversion gate 14, and "0" is written to the address of the block number "1" in the switching information storage bit memory 13.

The above explanation is for the case where access is performed from the system bus 4, but when accessing from the transmission bus 5, address 1 is selected by the address switching circuit 11, and the non-inverting gate 15 is enabled by the signal A. The difference is that Therefore, a signal of "1" is applied to the dual port memory 6, and a signal of "0" is applied to the dual port memory 7, so that only the dual port memory 7 is selected. Then, access is made from the transmission bus 5 to block B21 in FIG. After the access is completed, the contents of the switching information storage bit memory 13 are inverted and written in response to the switching command, which means that the corresponding switches in the switching circuits 8 and 9 in FIG. 2 have been switched, and the system bus A block accessed from one of transmission bus 4 and transmission bus 5 can then be accessed from the other.

〔Effect of the invention〕

As described above, according to the present invention, a pair of memories is divided into N blocks, and each block has a dual port memory configuration that allows bus switching (system bus and transmission bus) when storing transmitted and received data.
Furthermore, by making each block correspond to the transmission data storage area of N controllers connected to the transmission bus, it has the advantage of increasing the effective transfer speed and simplifying data reading and writing. be.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example of a controller, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram showing a specific structure of the switching circuit and its control circuit shown in Fig. 2. , FIG. 4 is a block diagram of the switching information storage bit memory. Description of symbols 1 (1 ₁ , 2 ₂ , 1 _N )...Controller, 2...Data transmitting/receiving device (data transfer device), 3...System memory, 4...System bus, 5...Transmission bus, 6,7 ...Dual port memory, 8, 9...Switching circuit, 10...Switching control circuit, 11...Address switching circuit, 12...Block number storage memory, 13...Switching information storage bit memory, 14, 16, 17... ...inversion gate, 1
5...Non-inversion gate.

Claims (1)

[Claims] 1. In a multi-controller system in which a plurality of controllers in which a data processing device and a data transmitting/receiving device are connected via a system bus are connected in parallel via a transmission bus, and data is transmitted and received between these controllers, the data transmitting/receiving device There is a pair of dual port memories that are divided into blocks according to the number of controllers and can be accessed from both the system bus and the transmission bus, and when one of the blocks in the pair is made accessible from the system bus, the other is The switching means receives address signals from the system bus and the transmission bus, and selectively outputs one of the address signals. a block number storage memory 12 that stores a block number to which an address signal is assigned in correspondence with the address signal, and outputs the corresponding block number by inputting the address signal output from the address switching circuit 11; and the dual port. Switching information indicating whether each block of a pair of memories is connected to a system bus or a transmission bus is stored in correspondence with the block number, and the block number output from the block number storage memory 12 is used as input. A switching information storage memory 13 that outputs switching information, and after inverting the switching information output from the switching information storage memory 13 only for access from a predetermined bus of the two buses, one of the dual ports directly to memory,
gate means 1 for selecting one of the pair of dual port memories by inverting and supplying the same to the other dual port memory;
5, 16, 17, and the switching information storage memory 13
2. A multi-controller system comprising means 14 for inverting the switching information outputted from the dual port memory and storing it again after access to the dual port memory is completed.