JPH04258886A - Memory circuit - Google Patents

Abstract

PURPOSE:To lessen a load for connecting to an internal data bus, to facilitate a highspeed operation and to reduce an area for chips by forming a memory cell array for rewriting on the line of extension of the memory cell array for processing and directly transferring the data of the former to the latter by means of a data transfer circuit. CONSTITUTION:The read data of the memory cell array 5 for rewriting is directly transferred to the memory cell array 1 for processing, without routing through the internal data bus 3, by means of the data transfer circuit 9; the timing of this transfer is performed by a clock signal CK. Therefore, the load to connect with the internal data bus 3 is only on a memory part with the memory cell array 1 as a center, and further, since the memory cell array 5 and the memory cell array 1 are connected through the exclusive data transfer circuit 9, the operating speed is improved. Also, since the memory cell array 5 is formed on the extension of the memory cell array 1 in the same pattern, the wiring space, dead space and area for chips are reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to a memory circuit used in a digital signal processor that processes signals at regular sampling intervals.

0002

2. Description of the Related Art A digital filter is an example of an application of a digital signal processor that processes signals at regular sampling intervals. The basic calculation in a digital filter is the cumulative sum of the products of coefficient data and input. The characteristics of this digital filter are determined by coefficient data.

[0003] Usually, a plurality of coefficient data that determine the characteristics of a digital filter are stored in a built-in memory. Furthermore, if the characteristics of this digital filter are not unique and may change, the coefficient data is stored in a memory such as a RAM.

[0004] Changes in the characteristics of this digital filter, ie, changes in coefficient data, are performed by a host microcomputer that controls a signal processing processor that implements this digital filter. That is,
When the characteristics of the digital filter are changed, the host microcomputer transfers coefficient data that can realize the changed characteristics to the signal processing processor.

[0005] In transferring this coefficient data, it takes ten times as much time as the sampling period for signal processing to transfer one set of multiple coefficient data that realizes the changed characteristics, and the timing of the transfer is Since the signal processing that realizes the digital filter is completely asynchronous, the following two types of memory circuits have been proposed to facilitate this transfer.

FIGS. 2A and 2B are a block diagram showing a first example of a conventional memory circuit and a circuit diagram of its memory cells.

Reference numeral 1 denotes a RAM type processing memory cell array for storing coefficient data for signal processing. 3 is an internal data bus of the signal processing processor, and 2 is an address decoder that specifies the address of the processing memory cell array 1.

The signal processing processor performs signal processing using a processing memory cell array 1, a data bus 3, and an address decoder 2 to realize a digital filter.

Reference numeral 5 denotes a RAM type rewriting memory cell array that temporarily stores coefficient data for changing characteristics.

As mentioned above, the host microcomputer controlling the signal processing processor transfers new coefficient data to the signal processing processor in order to rewrite the coefficient data, but the signal processing processor has no interface with the host microcomputer. This coefficient data DT is received by the rewrite data input circuit 7, and is stored by the write circuit 8 in the memory cell MC2 specified by the address decoder 6 in the rewrite memory cell array 5. Since the coefficient data that determines the characteristics of the digital filter is a set of multiple pieces, the transfer of the coefficient data DT is repeated multiple times.

When all the coefficient data to be changed has been transferred to the rewriting memory cell array 5, the host microcomputer transfers a rewriting permission signal to the signal processing processor.

On the other hand, in the signal processing processor, signal processing of the digital filter is performed at each sampling period even while receiving coefficient data from the host microcomputer described above.

[0013] Normally, signal processing of a digital filter is as follows.
Although specific processing for realizing filter characteristics is performed for each sampling period, it is not necessary to use the entire sampling period for processing. That is, during one sampling period, except for the time during which the digital filter performs signal processing, it is in a HALT state, that is, in a state in which nothing is executed until the next sampling period.

Now, the signal processing processor that received the coefficient rewriting permission signal from the host microcomputer described above completes the signal processing of the digital filter in the next sampling period after receiving this signal, and enters the HALT state described above. At this point, the internal data bus 3, processing memory cell array, and 1-address decoder 2 are opened for coefficient data rewriting, and coefficient data rewriting is started.

The first rewrite data from the rewrite memory cell array 5 specified by the address decoder 6 is input to the read/write circuit 4a via the internal data bus 3 by the read circuit 10, and is input to the read/write circuit 4a by the address decoder 2 indicating the address to be changed. The content of the data at the address of the processing memory cell array 1 specified by is rewritten. This operation is repeated for the number of pieces of coefficient data that need to be rewritten.

FIGS. 3A and 3B are a block diagram showing a second example of a conventional memory circuit and a circuit diagram of its memory cells.

This circuit has a memory cell array 11 of dual port RAM type.

Coefficient data DT for rewriting received from the host microcomputer through the rewriting data input circuit 7 is input to the write circuit 8 at the time when one word of coefficient data DT is received. After that, address decoder 6
Data for rewriting is written to the memory cell MC at the address of the memory cell array 11 designated by a, and rewriting is performed.

On the other hand, the signal processing of the digital filter reads out the memory cell array 11 regardless of whether or not coefficients are rewritten. That is, address decoder 2a
, a part of the memory cell array 11, and the read circuit 10a
is always used for signal processing.

In this example, even if access to the memory cell array 1 for rewriting coefficient data from the host microcomputer and reading of coefficient data for use in internal signal processing are performed at the same time, they are performed separately. There is no problem because the memory cell MC is accessed.

[0021]

In the first example, the conventional memory circuit described above has a processing memory section centered on a processing memory cell array 1 and a rewriting section centered on a rewriting memory cell array 5. Since the memory section is formed separately and connected to the internal data bus 3, the load capacity of the internal data bus 3 increases and speeding up is hindered.
Another drawback is that the chip area becomes large; in the second example, even if the data to be rewritten is small, each memory cell MC must be of a dual-hole type, and the area occupied by the memory cell array 11 on the chip is large. This has the disadvantage that the overall chip area becomes larger.

An object of the present invention is to provide a memory circuit that can reduce the chip area and increase the speed.

[0023]

[Means for Solving the Problems] A memory circuit of the present invention includes:
A plurality of first memory cells arranged in a matrix, a plurality of first word lines that select the first memory cells in each row, and data of the first memory cells in each column. a memory cell array for processing for writing data into the first memory cells in a selected state and reading data from the first memory cells, including a plurality of first data lines respectively transmitting the data; a read circuit for transmitting data read from a memory cell array for processing to an internal data bus; a plurality of second memory cells arranged in a matrix corresponding to each column of the memory cell array for processing; a plurality of second word lines for selecting memory cells in each row; and a plurality of second word lines for transmitting data in the second memory cells for each column.
a rewriting memory cell array having data lines for writing data into and reading data from the second memory cells in the selected state; a write circuit for transmitting data to a data line; and a plurality of tri-state data transfer elements provided correspondingly between each of the first and second data lines; and a data transfer circuit that transfers the data to the corresponding first data line and maintains an insulating state between the first and second data lines except when the data is transferred.

[0024]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment includes a plurality of first memory cells MC1 arranged in a matrix, and a plurality of first word lines each of which selects the first memory cells MC in each row by an address decoder 2. WL1, and a plurality of paired first data lines DL1a, D that respectively transmit data of the first memory cell MC1 for each column.
A processing memory cell array 1 which includes L1b and writes data into a selected first memory cell MC1 and reads data from the first memory cell MC1; a read/write circuit 4 that transmits data to the internal data bus 3; a plurality of second memory cells MC2 arranged in a matrix corresponding to each column of the processing memory cell array 1;
The address decoder 6 selects these second memory cells MC.
2 is selected for each row.
L2, and a plurality of second data lines DL2 that are paired with each other and transmit data of the second memory cell MC2 for each column.
a, DL2b and a second memory cell MC2 in a selected state.
A memory cell array 5 for rewriting writes data to and reads data from these second memory cells MC2.
and the data DT for rewriting is sent to the second data line DL2a,
A write circuit 8 that transmits data to DL2b, a rewrite data input circuit 7 that transmits rewrite data DT from the microcomputer to the write circuit 8 in word units, and respective first and second data lines DL1a, DL1b-DL2a, DL
A clocked inverter CIV of a plurality of tri-state data transfer elements provided correspondingly between the second data lines DL2a and DL2b is provided between the second data lines DL2a and DL2b at a predetermined timing according to the clock signal CK. Data is transferred to DL1a and DL1b by crossing each other, and the first and second data lines DL1 are
The configuration includes a data transfer circuit 9 that insulates between DL1b and DL2a and DL2b.

That is, this embodiment differs from the conventional memory circuit shown in FIG. 2 in that the rewriting memory cell array 5 is provided on an extension of the processing memory cell array 1.
The point is that read data from the memory cell array 5 for rewriting is directly transferred to the memory cell array 1 for processing by the data transfer circuit 9 without going through the internal data bus 3. The timing of this data transfer is performed using the clock signal CK in the same manner as in the conventional example.

Therefore, the load connected to the internal data bus 3 is only the memory section centered on the processing memory cell array 1, and the rewriting memory cell array 5 and the processing memory cell array 1 are connected by a dedicated data transfer circuit 9. Therefore, the operation speed can be improved, and
Since the rewriting memory cell array 5 can be formed in the same pattern on an extension of the processing memory cell array 1, the wiring area and dead space between them can be reduced, and the chip area can be reduced.

[0029]

As explained above, the present invention forms a memory cell array for rewriting as an extension of a memory cell array for processing, and transfers data in the memory cell array for rewriting directly to the processing memory cell array by a data transfer circuit. By adopting a transfer configuration, the load connected to the internal data bus is reduced, and the data in the memory cell array for rewriting is directly transferred to the memory cell array for processing, making it possible to speed up the operation. In addition, there is an effect that the wiring area and dead space can be reduced and the chip area can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a first example of a conventional memory circuit and a circuit diagram of its memory cells.

FIG. 3 is a block diagram showing a second example of a conventional memory circuit and a circuit diagram of its memory cells.

[Explanation of symbols]

1 Processing memory cell array 2, 2a Address decoder 3 Internal data bus 4, 4a Read/write circuit 5 Rewriting memory cell array 6, 6a Address decoder 7 Rewriting data input circuit 8 Write circuit 9 Data transfer circuit 10, 10a Read circuit 11 Memory Cell array CIV clocked inverter DL1a, DL1b, DL2a, DL2b, DL1A,
DL1B, DL2A, DL2B data line MC,
MC1, MC2 Memory cells WL1, WL2
word line

Claims (2)

[Claims] Claim 1: A plurality of first
a plurality of first word lines that respectively select the first memory cells for each row, and a plurality of first data that respectively transmit the data of the first memory cells for each column. a processing memory cell array having a line for writing data into the first memory cells in a selected state and reading data from the first memory cells; A read circuit for transmitting data to an internal data bus, a plurality of second memory cells arranged in a matrix corresponding to each column of the processing memory cell array, and a selected state of these second memory cells for each row. and a plurality of second data lines that transmit data of the second memory cells for each column.
a memory cell array for rewriting that writes data to the memory cells of and reads data from these second memory cells; a write circuit that transmits data for rewriting to each of the second data lines; A plurality of tri-state data transfer elements are provided correspondingly between the first and second data lines, and the data on each of the second data lines is transferred to the corresponding first data line at a predetermined timing. A memory circuit comprising: a data transfer circuit that maintains an insulating state between the first and second data lines except when transferring data. 2. Each of the first and second data lines is formed in a pair, and the tri-state data transfer element is formed of a clocked inverter, and the tri-state data transfer element is configured to transfer data from the second data line to the first data line. 2. The memory circuit according to claim 1, wherein the memory circuit is configured such that the data are transferred so as to cross each pair.