JPH06222976A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the reliability of stored data by providing a means for judging data to be used at the time of reading from each port even when the different data are simultaneously writter from the respective ports to the same address. CONSTITUTION:This device is provided with a pair of memory cell groups 1 and 2, write control parts 4 and 5 for writing data from one port preferentially to one memory cell group and writing data from the other port preferentially to the other memory cell group when the data are simultaneously written from the respective ports A and B to both of memory cell groups 1 and 2, and read data comparison parts 6 and 7 for comparing the stored contents of mutually corresponding addresses in the respective memory cell groups 1 and 2 when reading data and for selecting the data to be read when the data are different from each other. Thus, since the data to be used can be selected at the time of reading, the reliability of data is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a pair of ports that allow a plurality of processors to share the same data and access the data independently.

[0002]

2. Description of the Related Art Conventionally, a so-called dual port memory has been known as a semiconductor memory device which can be simultaneously and independently accessed by a plurality of processors. This dual-port memory has a pair of ports that can directly access each address of the memory cell array, and each port corresponds to each processor. Its structure is shown in FIG. The memory cell array 11 can be simultaneously accessed from the port A and the port B, and is used for exchanging data between the CPUs and parallel processing of the same data.

In the above dual port memory, when the write operation is simultaneously performed from both ports to the same address (for example, An), it is unclear which write operation has priority. In some cases, data continuity with other addresses cannot be maintained and a data error may occur.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the prior art as described above, and its main purpose is to perform different data write operations for the same address from each port. It is an object of the present invention to provide a dual port semiconductor memory device capable of ensuring the reliability of the data even if the data is broken.

[0005]

According to the present invention, there is provided a semiconductor memory device in which a pair of ports can be accessed independently of each other.
A pair of storage element groups having addresses corresponding to each other to be read, and data written from one of the ports to one of the storage element groups when writing is simultaneously performed from the ports to the storage element groups. Writable with priority,
And a control means for allowing the data from the other port to be written preferentially to the other storage element group, and the storage of addresses corresponding to each other of the storage element group when reading the data from the respective port. This is achieved by providing a semiconductor memory device characterized by having a selection means for comparing the contents and selecting which data is read out if the data are different from each other.

[0006]

As described above, normally, the same data is written to the addresses corresponding to each other in the pair of storage element groups (memory cell arrays) having the same structure, and the write operation is simultaneously performed to the same address from each port. In this case, one storage element group stores the data from one port, the other storage element group stores the data from the other port, and it is possible to select which data to use when reading. This ensures the reliability of the data.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a dual port memory as a semiconductor memory device to which the present invention is applied. A pair of memory cell arrays 1 and 2 each having the same address configuration can be independently accessed from a port A and a port B as shown in the upper and lower parts of the figure. Further, in the write lines from the port A and the port B to the memory cell arrays 1 and 2, the write data from the ports A and B is written to which memory cell array, or both memory cell arrays 1 and 2 are written. Write control units 4 and 5 for selecting whether or not are provided. These write control units 4 and 5 are connected to the write address comparison unit 3 that compares the write address from the port A and the write address from the port B when the write operation is performed simultaneously from the ports A and B. Has been done.

Here, when the write address comparing section 3 determines that the write operation is simultaneously performed from the ports A and B to the same address, the write address is transmitted to the write control sections 4 and 5. . In response to this, the write control units 4 and 5 transfer the write data from the port A to the memory cell array 1
, And the write data from the port B is given priority over the memory cell array 2 to be writable. On the other hand, the read lines from the memory cell arrays 1 and 2 to the ports A and B are used to compare the read data with each other when the data written in the addresses corresponding to each of the memory cell arrays 1 and 2 are read. Read data comparison units 6 and 7 are provided. Here, the read data comparison unit 6 is connected to the port A, and the data comparison unit 7 is connected to the port B.
When the two are different from each other, this is transmitted to the corresponding port, and it is possible to select which data is read.

The operating procedure of this embodiment will be described below. First, normally, write / read operations can be performed in parallel to the memory cell arrays 1 and 2 from each of the ports A and B. Here, when the data write operation is simultaneously performed from the port A and the port B to the same address (for example, An), this is the write address comparison unit 3
Is transmitted to each of the write control units 4 and 5, and the data from the port A is written to the memory cell array 1 with priority.
Data from the port B is preferentially written in the memory cell array 2. Therefore, when such an operation is performed, if the data from the port A and the data from the port B are different from each other, different data may be stored in the same address (An) of the memory cell array 1 and the memory cell array 2. It will be written.

Next, such data is transferred to port A, for example.
When reading from the side, before the actual read operation is performed, the read data comparison unit 6 sets the memory cell arrays 1, 2
Data of the address (An) are compared, and if the data are different, a flag indicating this is transmitted to one processor not shown via the port A. Then, this processor determines which data is to be read from the continuity of data and the history of writing, and one of the selected data is read from the port A.
Similarly, when a read operation is performed from the port B, the read data comparison unit 7 compares the data, and a processor (not shown) on the port B side determines which data is to be read, and according to that. The data will be read. If the memory cells 1 and 2 have the same storage content at the same address, the data is read as it is.

[0012]

As is apparent from the above description, according to the semiconductor memory device of the present invention, even when different data are simultaneously written to the same address from each port, any data is saved and the data is stored from each port. Since it is possible to determine which data to use when reading, the reliability of the stored data is improved without causing an error such as data discontinuity.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a dual port memory to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a conventional dual port memory.

[Explanation of symbols]

 1, 2 memory cell array 3 write address comparison section 4, 5 write control section 6, 7 read data comparison section 11 memory cell array

Claims (1)

[Claims] 1. A semiconductor memory device capable of independently accessing a pair of ports, wherein a pair of storage element groups having addresses corresponding to each other that are simultaneously written / read from the port, and the respective ports are provided. When data is simultaneously written to both of the storage element groups from one to the other, the data from one of the ports can be preferentially written to one of the storage element groups, and the data from the other port of the other can be stored. If the data is different from each other, the control means for giving priority to the element group to enable writing and the data stored in the respective memory element groups at the time of reading data from each port are compared with each other. A semiconductor memory device comprising: a selection unit for selecting whether to read data.