JPH05151769A - Multi port memory - Google Patents

Abstract

PURPOSE:To obtain a multi port memory having plural ports, performing access to a memory cell array independently of respective ports and asynchronously and transferring data at high speed. CONSTITUTION:A circuit performing access to the memory cell array 4 through the memory cell array 4 and the port is mounted at every port. Further, a register 1 storing temporarily a part of the data in the memory cell array and a transfer controller 2 are incorporated. The data is transferred at high speed in the memory since control for writing a content specified by a row address in the register 1 and for reading the content of the register 1 in the memory cell specified by the row address is performed with an instruction from the signal of the port by the transfer controller 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has a plurality of ports,
The present invention relates to a multi-port memory that can access each port independently and asynchronously.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional DRAM shown in, for example, "Fujitsu Semiconductor Device / DATA BOOK 1990 Memory". In the figure, 14 is D
RAM, 4 is a memory cell array which is an array of memory cells for storing 1-bit data, 10 is an address signal terminal for inputting an address signal designated from the outside, and 8 is a row address input to the address signal terminal 10. A RAS terminal for inputting a signal indicating that the column address is input to the address signal terminal 10, a CAS terminal for inputting a signal indicating that a column address is input to the address signal terminal 10, and a reference numeral 5 for inputting signals from the CAS terminal 9 and the address signal terminal 10 to the memory cell array. A column decoder that decodes the column address of 4, 6 is RA
A row decoder that decodes a row address of the memory cell array 4 from input signals of the S terminal 8 and the address signal terminal 10, 7 is a data signal terminal for inputting / outputting data to / from the outside, and 11 is accessing the DRAM 14. WE terminal for inputting a signal indicating that the access is a write operation, 12 is an OE terminal for inputting a signal requesting output of data while accessing the DRAM 14, 3
Reference numeral 7 is a data input buffer that temporarily stores data when writing data input from the data signal terminal 7 to the memory cell array 4, and 38 is a data output buffer that temporarily stores data output to the data signal terminal 7. is there. In this example, there are four data signal terminals 7, eight address signal terminals 10 and four 256-bit × 256-bit memory cells corresponding to each data signal terminal 7, but these values are relatively large. It is possible to change.

FIG. 6 shows, for example, "Fujitsu Semiconductor Device
FIG. 3 is a configuration diagram of a conventional 2-port SRAM shown in “DATA BOOK 1990 Memory”. 27 is a 2-port SRAM, 15 is an arbitration circuit for arbitrating access requests from two ports, 16 is a memory array for storing data, 20 and 21 are address signal terminals for inputting an address signal designated from the outside, of which 20 is a lower address signal terminal, 21 is an upper address signal terminal, 1
8 is a row decoder that decodes the row address of the memory array 16 from the address signal input from the upper address signal terminal 21, 19 is a column decoder that decodes the column address of the memory array 16 from the address signal input from the lower address signal terminal 20, 22 is a data signal terminal for inputting / outputting data to / from the outside, and 23 is 2
A WE terminal for inputting a signal indicating that the access is a write operation while accessing the port SRAM 27, an OE terminal for inputting a signal requesting output of data while accessing the 2-port SRAM 27, 17
Is an I / O buffer for temporarily storing data input / output to / from the data signal terminal 22, and 24 is a 2-port SRAM
A CS terminal for inputting a signal indicating access to 27 and a BUSY terminal for outputting a signal notifying that it is necessary to wait for access as a result of arbitration in the arbitration circuit 15. The 2-port SRAM 27 includes a circuit commonly used by two ports such as the memory array 16 and the arbitration circuit 15, and a circuit necessary for controlling memory access at each port. In this example, the data signal terminal 22 is 8 at each port.
There are 11 address signal terminals 20 and 21, and these values are changed depending on the configuration of the memory array.

FIG. 7 is a diagram showing a configuration example of a control device using a DRAM. In the figure, 35 is a 1-port memory module having one accessed port, 29 and 3
Reference numeral 0 is a controller for reading data stored in the 1-port memory module 35 and writing data to the 1-port memory module 35. 29 is a controller A, 30 is a controller B, 31 is a controller A2
CPU for controlling 9 and controller B30 to read or write to 1-port memory module 35, and 36 for controller A29, controller B30 and CPU31
An arbitration circuit for arbitrating access to the 1-port memory module 35 by the controller A, controller B30 or controller A30 according to an instruction from the arbitration circuit.
It is a transceiver used for switching an access signal to the 1-port memory module 35 by the PU 31. The 1-port memory module 35 includes a plurality of DRAMs 1 according to the data bus width and the required memory size.
It is composed of 4.

FIG. 8 is a diagram showing a configuration example of a control device using a 2-port memory module. In the figure, 28
Is a 2-port memory module having two accessed ports, and 32 is an arbitration circuit for arbitrating access to the 2-port memory module 28 by the controller A 29 and the CPU 31. 2-port memory module 28
Is composed of a plurality of 2-port SRAMs 27 according to the data bus width and the required memory size.

Next, the operation will be described. DRAM14
Is accessed, a signal is first input to the RAS terminal 8 and the address signal terminal 10, and the row decoder 6 generates a row address based on the signal. Next, a signal is input to the CAS terminal 9 and the address signal terminal 10, and the column decoder 5 generates a column address based on the signal. The memory cell array 4 is an array of memory cells and uniquely identifies the memory cells by a row address and a column address. In the example of FIG. 5, by determining the row address and the column address, one of the 256-bit × 256-bit memory cells is designated, and a total of four memory cells are designated. Then, a request from the outside to read or write to those memory cells is determined by a control signal input to the WE terminal 11 and the OE terminal 12. In the case of a read request, the data stored from the designated memory cell is copied to the data output buffer 38 and output from the data signal terminal 7.
In the case of a write request, the signal input from the data signal terminal 7 is stored in the data input buffer 37 and then copied to the designated memory cell.

FIG. 7 shows an example of a control device using the 1-port memory module 35. The 1-port memory module 35 is composed of the DRAM 14. Controller A
29, the controller B30, and the CPU 31 access the 1-port memory module 35. However, since the 1-port memory module 35 has only one port, the arbitration circuit 36 arbitrates access requests from three parties, and controls only one of the three parties to access at one time.

Next, the operation of the 2-port SRAM 27 will be described. When accessing the 2-port SRAM 27,
First, signals are input to the CS terminal 24 and the address signal terminals 20 and 21, and the row decoder 18 generates a row address based on the signals, and the column decoder 19 generates a column address. The memory array 16 is an array of memory cells, and uniquely identifies each memory cell by a row address and a column address. Then, an external request to read or write to the memory cell specified by the row address and the column address is issued by the WE terminal 23.
And the control signal input to the OE terminal 25. In the case of a read request, the data stored from the specified memory cell is copied to the I / O buffer 17,
It is output from the data signal terminal 22. In the case of a write request, the signal input from the data signal terminal 22 is stored in the I / O buffer 17 and then copied to the designated memory cell. The above-described processing for external access can be performed independently at each port, and the access operations for the two ports do not have to be synchronized.

The arbitration circuit 15 includes a CS terminal 24 and an address signal terminal 20, 2 of each port.
By comparing signals input from 1, it is possible to detect that the same memory cell is being accessed simultaneously from two ports. When detecting this, the arbitration circuit 15 outputs a control signal for permitting access to one port and temporarily prohibiting access to the other port to the BUSY terminal 26. This prohibition signal is released after the access to the permitted port is completed.

FIG. 8 shows an example of a control device using the 2-port memory module 28. The 2-port memory module 28 includes a 2-port SRAM 27. The controller B30 accesses the 2-port memory module 28 from the right port. Controller A29 and CPU3
1 accesses the 2-port memory module 28 from the left port. The arbitration circuit 32 arbitrates the access requests of the two parties, and temporarily controls either the controller A 29 or the CPU 31 to access. As described above, when the same memory cell is simultaneously accessed from the two ports, an access prohibition signal is output from the BUSY terminal 26 of the 2-port SRAM 27. The controller 29, 30 or the CPU 31, which has detected this signal, waits the access cycle and waits for the prohibition signal to be released. After being released, the access cycle is restarted.

[0011]

Since the conventional DRAM 14 is configured as described above, access from only one controller is permitted at a time. Therefore, when a plurality of controllers access the DRAM 14, the access is arbitrated by an external circuit. Then, the controller, the access of which is permitted by the arbitration, accesses the DRAM 14. In the meantime, the access of other controllers is kept waiting. Particularly when the controller performs burst transfer, a long time is required for burst transfer because several words to several tens of words are continuously transferred. During that time, the controller that has been waiting for access cannot perform other processing, so that the performance of the controller deteriorates.

On the other hand, since the conventional 2-port SRAM 27 is configured as described above, it is possible to access independently and asynchronously from the two ports unless the addresses accessed from the two ports match. However, in order to realize this, it is necessary to incorporate an arbitration circuit and take a special memory array configuration, and the size of the memory cell mounted in one IC is significantly limited as compared with the DRAM 14 described above. was there.

The present invention has been made in view of the above points, and an object of the present invention is to provide a conventional 2-port S.
It has multiple ports without being greatly limited in memory size like RAM27, and is independent for each port.
It is to obtain a multi-port memory that can be accessed asynchronously and can transfer data at high speed.

[0014]

In order to solve such a problem, a multi-port memory according to the present invention has a memory cell array (an example of a storage unit) for each port, and the memory cell array is accessed through the port. A circuit for doing so (an example of an access means) is mounted. Further, the same number of registers as one column of memory cells in the memory cell array and one transfer controller (an example of transfer means) are incorporated. Then, the transfer controller controls the data transfer for writing the content specified by the row address to the register or reading the content of the register to the column of the memory cell specified by the row address according to an instruction from the port signal. I do.

[0015]

In the multiport memory configured as described above, since the memory cell array (storage unit) and its peripheral circuits (access means) are held for each port, the ports are independent of each port and are asynchronous with that port. The memory cell array can be accessed. Then, the transfer controller (transfer means) can write the data of the memory cell array in the other port to the register, and further transfer the content of the register to an arbitrary address of the memory cell array of the own port. On the contrary, it is possible to write the content of the memory cell array in the own port to the register and transfer the content of the register to the memory cell array of another port. The transfer between the register and the memory cell by this transfer controller is performed for one column of the memory cell by one.
Since it is performed every time and is almost the same as the transfer of 1-bit data between flip-flops inside the memory,
Completed in one access cycle.

[0016]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a 2-port memory 1 showing an embodiment of the present invention.
It is a block diagram of 3. In the figure, 1 is a register for temporarily storing data transferred between the memory cell array 4 of each port, 2 is a transfer controller for controlling data transfer between the memory cell array 4 and the register 1 by a signal from each port, Reference numeral 3 is an SE for inputting a control signal for instructing data transfer between the memory cell array 4 and the register 1.
It is a terminal. FIG. 2 is a block diagram of a control device using the 2-port memory 13 of the present invention. In the figure, 39 is 2
A 2-port memory module including the port memory 13 is an arbitration circuit 33 for arbitrating access from the controller B30 and the CPU 31 to the 2-port memory module 39. The 2-port memory module 39 is composed of a plurality of 2-port memories 13 according to the data bus width and the required memory size.

Next, the operation will be described. The 2-port memory 13 has a conventional DRAM 14 for each of the two ports.
, And the access to the memory cell array 4 of each port can be performed similarly to the conventional DRAM 14.

Data transfer between the memory cell array 4 and the register 1 will be described with reference to FIGS. 3 and 4. Figure 3
Shows a control signal for instructing to write the contents of the memory cell array 4 into the register 1.
In order to instruct the transfer controller 2 to transfer data to and from the register 1, the signal to the SE terminal 3 is turned on before turning on the signal of the RAS terminal 8. Further, in order to instruct the transfer controller 2 to write to the register 1, the signal to the WE terminal 11 is turned on before turning on the signal of the RAS terminal 8. Then, in order to designate a memory cell to be transferred, a row address is input to the address signal terminal 10 at the timing when the RAS terminal 8 is turned on. The transfer controller 2, which has detected the above-mentioned signal changes at the SE terminal 8 and the WE terminal 11, reads out the contents of the memory cell for one column designated by the row address from the memory cell array 4, and writes the contents to the register. Control to do so. In the present embodiment, the number of read memory cells is four times 256 bits, which is 1024.
Is a bit. It goes without saying that the same number of bits are prepared as registers.

FIG. 4 shows control signals for instructing to read the contents of the register 1 into the memory cell array 4. In order to instruct the transfer controller 2 to transfer data to and from the register 1, the signal to the SE terminal 3 is turned on before turning on the signal of the RAS terminal 8. Further, in order to instruct the transfer controller 2 to read from the register 1, the RAS terminal 8
The signal to the WE terminal 11 is turned off before the signal is turned on. Then, in order to designate a memory cell for storing data, a row address is input to the address signal terminal 10 at the timing when the RAS terminal 8 is turned on. The transfer controller 2, which has detected the above-mentioned signal changes at the SE terminal 8 and the WE terminal 11, reads out the contents of the register and controls the contents to be stored in the memory cells for one column designated by the row address. ..

By writing from the memory cell array 4 to the register 1 and reading from the register 1 to the memory cell array 4, data can be transferred at high speed between the memory cell arrays 4.

Next, data transfer between the memory cell arrays 4 in the control device having the configuration shown in FIG. 2 will be described.
The controller A 29 and the CPU 31 access the 2-port memory module 39 from the left port. Arbitration circuit 3
2 arbitrates the access requests of the two parties and temporarily controls either the controller A 29 or the CPU 31 to access. The controller B30 and the CPU 31 access the 2-port memory module 39 from the right port.
The arbitration circuit 33 arbitrates the access requests of the two parties, and temporarily controls either the controller B30 or the CPU 31 to access. In FIG. 2, when data is transferred from the left port memory cell array 4a to the right port memory cell array 4b in the 2-port memory module 39, the CPU 31 first accesses the left port of the 2-port memory module 39. Then, the two-port memory 13 is instructed to perform the write operation from the memory cell array 4a to the register 1 described above. After that, the CPU 31 accesses the right port of the 2-port memory module 39. Then, the 2-port memory 13 is operated so as to perform the read operation from the register 1 to the memory cell array 4b.
Instruct.

Next, an example of an application system of the 2-port memory 13 will be described. For example, in a communication system, data is transferred by dividing the data into transmission units having a predetermined size such as packets and cells. This transmission unit is 1 kilobit (256 bits x 4 =
In the case of 1024 bits), each relay station configures the 2-port memory module 39 with the 2-port memory 13 to enable high-speed transfer of these packets and cells. That is, the reception controller A2 of the relay station
In the case of transferring data from 9 to the controller B30 for transmission, conventionally, since data is moved from the reception buffer to the transmission buffer, it is necessary to access 256 times even if 4 bits can be accessed by one access. In contrast to this, in this example, there are a total of 2 read accesses from the memory cell array 4a corresponding to the conventional receiving buffer to the register 1 and write access from the register 1 to the memory cell array 4b corresponding to the conventional transmitting buffer. You will be able to finish with just one access. In addition,
In this example, the transmission unit is 1 kilobit, but the transmission unit is a size that is an integral multiple of 1 kilobit, a size that is a fraction of an integer
Alternatively, the transfer rate can be increased with other sizes, and the same effect as that of the above-described embodiment can be obtained.

As described above, in this embodiment, the memory cell array, which is an array of memory cells for storing 1-bit data, the port for inputting / outputting an access signal to / from the external memory cell array, and the access A memory provided with a circuit for decoding a signal and controlling access to the memory cell array is provided with a plurality of the ports, and each memory cell array and a circuit for controlling access to the memory cell array are provided for each port. The multiport memory is described which is provided with a register for temporarily storing a unit and a transfer controller for controlling data transfer between the register and the memory cell array.

Further, according to this embodiment, since the memory cell array and its access circuit are mounted for each port, the memory cell array in each port can be accessed independently and asynchronously from each port. Further, since an arbitration circuit such as a 2-port SRAM is unnecessary and the circuit of the DRAM is used, the storage capacity becomes larger than that of the 2-port SRAM.

Further, the contents of the memory cell array in another port can be read by transferring it to an arbitrary address of its own port via a register. Further, by transferring the contents of the memory cell array in the own port to the memory cell array in another port via the register, it is possible to write to the memory cell array in another port.

Furthermore, since the transfer between the register and the memory cell array is carried out inside the memory, it is possible to transfer the number of memory cells designated by the row address all at once, and it is possible to transfer at an extremely high speed.

Example 2. In the above embodiment, the normal access from the port to the memory cell array 4 is in units of 4 bits, and the space between the memory cell array 4 and the register 1 is in units of 1024 bits. Requires the access unit between the memory cell and the register to be larger than the access unit from the port, and has the same effect as the above embodiment.

Example 3. In addition, although the case where the transfer is performed using the register 1 has been shown in the above-described embodiment, the name need not be the register, and may be another storage unit, a memory, or a flip-flop. Any data can be temporarily stored.

Example 4. Although the above embodiment has described the case of two ports, it is needless to say that the present invention can be used with a number of ports larger than two.

[0030]

As described above, according to the present invention, it is possible to obtain a multi-port memory which does not require arbitration and is capable of high-speed data transfer.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a 2-port memory which is an embodiment of the present invention.

FIG. 2 is a configuration diagram of a control device using a 2-port memory that is an embodiment of the present invention.

FIG. 3 is a diagram showing control signals for instructing writing of data from a memory cell array to a register in the 2-port memory according to the embodiment of the present invention.

FIG. 4 is a diagram showing control signals for instructing reading of data in a register to a memory cell array in the 2-port memory according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional DRAM.

FIG. 6 is a configuration diagram of a conventional 2-port SRAM.

FIG. 7 is a configuration diagram of a control device using a conventional DRAM.

FIG. 8 is a configuration diagram of a control device using a conventional 2-port SRAM.

[Explanation of symbols]

 1 Register 2 Transfer Controller 3 SE Terminal 4 Memory Cell Array 5 Column Decoder 6 Row Decoder 7 Data Signal Terminal 8 RAS Terminal 9 CAS Terminal 10 Address Signal Terminal 11 WE Terminal 12 OE Terminal 13 2 Port Memory or Multiport Memory 37 Data Input Buffer 38 Data output buffer

Claims (1)

[Claims] 1. A multi-port memory having the following elements: (a) a plurality of storage units for storing data; (b) a plurality of accesses provided corresponding to the storage units and accessing each storage unit in a predetermined unit. Means, (c) a register provided between the plurality of storage units, and (d) data is transferred between the storage unit and the register in a unit larger than a predetermined unit for accessing the storage unit by the access unit. Transfer means,