JPS61193245A - Memory control system - Google Patents

Abstract

PURPOSE:To enable exchange of computer systems by so constituting the hierarchical structure of a memory device as to be unrestrictedly changeable. CONSTITUTION:When no intermediate buffer WS2 is mounted or when it is unoperated though mounted,a CPU 100, setting a wire 111 to logic '0', switches on an AND circuit 103 and switches off and AND circuit 102. At that time, an access request outputted to a wire 110 from the CPU 100 is given to a MS control circuit 8 through the AND circuit 103. The MS control circuit 8 reads and writes according to the access request when having received the access request from the CPU 100. In other words, when having received a fetch request, the MS control circuit 8 makes access to a MS 3 through a wire 34, selects fetch data from the MS 3 by a selector 101, stores it in a fetch data register 6 and sends it to the CPU 100 through a wire 114.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a storage control method, and particularly to a control method for a storage device forming a hierarchical structure.

[Background of the invention]

Conventionally, a storage device has, for example, a three-layer structure of a main storage device, an intermediate buffer, and a buffer storage, and a copy of some data in the main storage device is stored in the intermediate buffer.

Furthermore, a method is known in which a copy of some data in an intermediate buffer is stored in a buffer storage. For example, 198
In "Nikkei Electronics" published on May 31, 2017, Mr. Toshio Hiraguri and others wrote, "Large computer M-380/382J with improved performance through three-layer memory system and high-density technology.
The three-layer storage device is important in improving the performance of high-end machines such as large computers. However, for lower-level models that do not require much performance, two layers of buffer storage and main storage may be sufficient. However, conventionally, no consideration has been given to easily realizing the transition from three layers to two layers, or from two layers to three layers, and compatibility between these has been impossible.

An example of such a conventional configuration is shown in FIG. In Figure 2,
100 is a central processing unit, and a buffer storage (B
S) 1 is built-in. 2 is intermediate buffer (WS), 3
is the main memory (MS) in which WS2 stores a copy of some data from MS3.

A copy of some data of WS2 is sent to B of the central processing unit 100.
Stored by SI. 4 is a WS address array (WAA) that stores the main memory addresses of data in WS2.
, and a similar address array is in the central processing unit 100
also has against BSI.

Normally, if desired data exists in BS1, the central processing unit 100 obtains the desired data from the BSI in the case of a fetch, and rewrites the corresponding data in the BSI and WS2 with store data in the case of a store.

If the desired data does not exist in the BSI, or if it is a store, the central processing unit 100 sends the WS control circuit 7
A BS access request (fetch request or store request) is issued through line 30, and in the case of a store request, store data is stored in store stack data register 10 through line 20.

When the WS control circuit 7 receives a BS access request from the central processing unit 100, it refers to the WAA 4 and checks whether the desired data exists in the WS 2. When it is found that the desired data exists in WS2, in the case of fetch, it is sent to WS2 through the line 32 based on the reference result of WAA4.
accesses the corresponding area of WS2, stores the fetch data from WS2 in the fetch data register 6, and then
Central processing unit through 1! In the case of a store, selector 9 selects store data in register 10 and stores it in store data register 5.

It is stored in the corresponding area of WS2 indicated by line 32.

If the desired data does not exist in WS2, WS control circuit 7 issues a block transfer request to MS control circuit 8 through line 33.

When the MS control circuit 8 receives a block transfer request from the WS control circuit 7, it accesses the MS 3 through the line 34, and
A block containing desired data is read from the MS3.

This block data is passed through the line 22 to the WS control circuit 7.
under the control of, sequentially.

The data is stored in the WS2 through the selector 9 and the store data register 5. When this block transfer is completed, the WS control circuit 7 re-reads the desired data from the WS 2 and transfers it to the central processing unit 100 in the case of a fetch, and selects the store data in the store stack data register 10 with the selector 9 in the case of a store. Then, the data is stored in the WS2 through the store data register 5.

In addition, when performing block transfer from MS3 to WS2] WS2
If there is no empty square □ in
U method), and if the block of i has been rewritten by the largest number in the WS.

Sequentially, the data of the block is transferred from WS2 to the fetch data register 6, and at the same time, a block transfer request is issued to the MS control circuit 8, and the data is transferred to the MS3 via the line 21, and then to the vacant area of WS2. , the block in which the desired data exists is connected to the MS3 twisted line 22 . Selector 9. Transfer via store data register 5.

In this way, in the configuration shown in FIG. 2, all access requests from the central processing unit 100 are sent to the WS control circuit w47, and exist only between the data line -t+Ws2. Store access in blocks,
Because only fetch exists.

The MS control circuit 8 has only that control function.

Therefore, if WS2 is removed, the entire system becomes inoperable.
It is not possible to make S2 removable.

[Purpose of the invention]

The object of the present invention is to provide a one-layered storage device.

The object of the present invention is to provide a storage control method that enables separation of the intermediate buffer.

[Summary of the invention]

The present invention enables access to the main storage device as well as the intermediate buffer from an access request source such as a central processing unit or input/output device, and allows access to the main storage device not only in block transfers but also in 8-byte and 32-byte units. The main storage device can be accessed directly from the access request source even when the intermediate buffer is removed.

[Embodiments of the invention]

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, a central processing unit 100 has a built-in buffer storage (BS) 1, and normally an intermediate buffer (BS) 1 is built in.
It forms a three-tier storage device together with the main storage device (WS) 2 and the main storage device (MS) 3. That is.

WS2 stores some data of MS3, BSI stores WS
6WS2, which stores a copy of some data of 2, is a WS
The MS 3 is under the control of the control circuit 7 , and the MS 3 is under the control of the MS control circuit 8 . WS address array (WAA) 4 is WS
It stores the main memory address of the data existing in 2.

The central processing unit 100 also has an address array similar to this WAA4 for the BSI.

The central processing unit 100 can issue an access request to either the WS control circuit 7 or the MS control circuit 8 via the AND circuits 102 and 103. Therefore, the MS control circuit 8 can receive access requests from the WS control circuit 7 as well as from the central processing unit 100. Store data from central processing unit 100 is stored in store stack data register 10. After the store data in this register 10 is stored in the store data register 5 via the selector 9, it can be stored in either the WS2 or the MS3. Similarly, data fetched from either WS2 or MS3 can be stored in the fetch data register 6 via the selector 101.

The operation shown in FIG. 1 will be explained below. When the WS2 is incorporated and operated, the central processing unit 100 sets the line 111 to logic "1" to turn on the AND circuit 102 and turn off the AND circuit 103. In this case, the central processing unit 100
An access request issued on line 110 from AND circuit 1
02 to the WS control circuit 7. When the WS control circuit 7 receives an access request from the central processing unit 100, it refers to the WAA 4 and checks whether the desired data exists in the WS 2. If the desired data exists in WS2, the fetch operation fetches the relevant data from WS2 and transfers it to the central processing unit 100 via the line 112, selector 101, fetch register 6, and line 114, and the store operation , the data stored in the store stack data register 10 from the central processing unit 100 through the line 20 to the selector 9 . W via store register 5
Store in S2. If the desired data does not exist in WS2, WS control circuit 7 issues a block transfer request to MS control circuit 8 through line 33.

When the MS control circuit 8 receives a block transfer from the WS control circuit 7, it sequentially reads the data of the corresponding block from the MS 3, and transfers the data to the line 113. Selector 101, fetch data 6
, line 114. The data is sequentially stored in the store data register 5 via the selector 9.

The data in this register 5 is controlled by the WS control circuit 7.
S2 Hesdoor is done. Once this block transfer is finished,
In the case of a fetch, the WS control circuit 7 re-reads the desired data from the WS 2 and transfers it to the central processing unit 100, and in the case of a store, the WS control circuit 7 reads the desired data from the WS 2 and transfers it to the central processing unit 100, and in the case of a store, the WS control circuit 7 reads the desired data from the WS 2 and transfers it to the central processing unit 100.
Store data in WS2.

In this way, when incorporating WS2 and operating it, the second
It is basically the same as the figure.

Next, if WS2 does not exist, or if it does exist but is inactive, the central processing unit 100 sets the line 111 to logic II OPI, turns on the AND circuit 103, and turns off the AND circuit 102. In this case, the central processing unit 1
The access request output from 00 to line 110 is applied to 9MS control circuit 8 via AND circuit 103. M
When the S control circuit 8 receives an access request from the central processing unit 100, it performs normal reading and writing, for example, in units of 8 bytes or 32 bytes, to the MS 3 in accordance with the access request. That is, in the case of a fetch request, the MS control circuit 8 accesses the MS 3 via the line 34, selects the fetch data from the MS 3 using the selector 101, stores it in the fetch data register 6, and transfers the fetch data from the MS 3 to the central processing unit 10 via the line 114.
Send to 0. In addition, in the case of a store request, store data in the store stack data register 10 is selected by the selector 9 and stored in the store data register 5, and the line 34
MS3 is accessed by M
Store in S3.

In the above embodiment, the case where the WS is attached and detached in a three-layer structure of BS, WS, and MS has been described, but the WS and M
Needless to say, the present invention can also be applied to the case where wS is attached and detached in a two-layer S structure.

〔Effect of the invention〕

As is clear from the above description, one aspect of the present invention is as follows.

Since the hierarchical structure of the storage device can be changed freely, the model of the computer system can be easily changed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 1...Buffer storage (BS), 2...Intermediate buffer (WS), 3...Main storage (MS)
, 7...WS control circuit, 8...MS control circuit,
100...Central processing unit, 110...Access request line, 111...WS presence/absence control line. Figure 1

Claims (1)

[Claims] (1) In a storage device having at least a first storage device and a removable second storage device that stores a copy of some data in the first storage device, the read/write data line of the access request source a connecting means for commonly connecting the storage device to both the first and second storage devices; If the access request from the access request source is given to the first storage device side, and the access request from the access request source is given to the second storage device side,
It is checked whether the desired data exists in the second storage device, and if it exists, the second storage device is accessed to perform the read or write operation in response to the access request, and if it does not exist, the data is transferred to the first storage device. When an access request from the access request source is given to the first storage device side, the first control means issues a block transfer request to the first storage device side, and accesses the first storage device to perform reading or processing in response to the access request. The storage device is characterized by comprising second control means that performs a write operation and, when the block transfer request is issued, transfers the block containing the desired data from the first storage device to the second storage device. Memory control method.