JPS6321276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device that enables parallel processing of memory requests.

Computer systems are becoming more and more sophisticated in line with the demands of the times. FIG. 1 and FIG. 2 show the configuration of a general computer processing device. The configuration shown in FIG. Processes write and read requests from unit 4, execution unit 5, and channel unit 3. FIG. 2 shows a configuration in which an execution unit 5-2 is added to an execution unit 5-1 similar to the execution unit 5 of FIG. 1 in order to improve the arithmetic processing capacity. An example of the execution unit 5-2 is an array processor intended for high-speed processing of array operations.
By adding the execution unit 5-2, it is possible to improve the processing capacity, but in order to further improve the processing capacity, it is necessary to increase the processing capacity of the write and read requests in the storage device.

FIG. 3 shows an example of a storage device having a 64.times.64 bit memory array 16. Addresses of memory array 16 consist of row addresses and column addresses. Row addresses A ₀ to A ₅ are applied to row address buffer 10 via line 9, column addresses A ₆ to A ₁₁ are applied to column address buffer 14 via line 13, and row decoder 15 and column decoder 18, respectively. is decoded to select one bit of memory array 16. Clock generators 8 and 12 are each write enabled.
Driven by WE and chip enable CE,
Control reading and writing. Data input buffer 1
7 writes 1 bit data from the data input DI ₁ terminal 20 to the memory array 16, and the data output buffer 19 writes 1 bit data from the data input DI 1 terminal 20 to the memory array 16.
Bit data is output from the data output DO ₁ terminal 21.

When reading, turn on the chip enable CE, decode the addresses specified by the row address and column address by the row decoder 15 and column decoder 18, respectively.
One bit is selected from the memory array 16 and set in the data output buffer 19, and read data is output from the DO ₁ terminal 21. When writing, turn on chip enable CE and write enable WE, and data input buffer 17 is output from DI ₁ terminal 20 based on the address specified by row address and column address.
The write data set in the memory array 16 is written to the memory array 16.

In this way, a storage device only processes one request at a time, and conventionally, in order to increase the processing power of a storage device, it has been divided into multiple banks and interleaved, as seen in main storage devices, or The access time of the memory element itself has been shortened.

However, it is physically difficult to increase the number of banks, and the amount of hardware will also increase.Also, the access time of the memory element tends to increase as the capacity of the memory element becomes larger. For these reasons, it has become difficult to improve the processing capacity of storage devices.

An object of the present invention is to provide a storage device that enables parallel processing of requests and improves processing performance.

Another object of the present invention is to provide a storage device that achieves the above functions with a minimum increase in chip area.

Generally, among the requests to the main memory, the amount of data for writing and reading is large, and the address references may be continuous. for example,
Writing and reading of data in page units (2K bytes or 4K bytes) in the virtual storage system is performed with the auxiliary storage device. In addition, as the demand for larger scale and faster scientific calculations increases, a unit dedicated to performing array operations that handle multidimensional variables and data may be considered, but this unit is similar to the execution unit 5-2 in Figure 2. can be applied to. Since this unit handles array data, the amount of data is large and address references are often continuous.

In the present invention, when address references are continuous and a large amount of data is read from and written to a storage device, a large amount of data can be accessed at once instead of issuing requests for each piece of data one by one. By incorporating functions and making it possible to process in parallel with normal access, the processing capacity of the storage device is improved.

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 4 shows a block diagram of one embodiment of the present invention. In FIG. 4, the same numbers as in FIG. 3 correspond to the same parts. That is, FIG. 4 has the configuration shown in FIG. 3 with a data output buffer 37, a selection circuit 39,
Data output buffer 42, column address buffer 3
8, column decoder 40, count up circuit 41,
Read mode (RM) line 30, read pulse (RP) line 31, inverter 32, AND gate 3
3, 34, and an OR gate 36 are added. Furthermore, the memory array 16 is configured to read out one bit specified by a row address and a column address, and at the same time read out a data group for one row according to the row address at the same time. Furthermore, the column address buffer 14 is provided so as to be shared by the column decoder 18 and the column address buffer 38. The address signal line is also shared halfway.
By doing so, it is possible to minimize the increase in chip area due to increased functionality.

For normal reading, turn on the chip enable CE.
Then, the addresses specified by the row addresses A ₀ to _{A 5} and the column addresses A ₆ to A ₁₁ are decoded by the row decoder 15 and column decoder 18, respectively, and the addresses are decoded from the memory array 16 to 1.
The bit is read and set in the data output buffer 19, and the read data is output from the DO ₁ terminal 21. For this normal read, read mode RM on line 30 is turned OFF. Therefore, AND gate 34 is inactive and prohibits one row of data read from memory array 16 based on the row address from being taken into data output buffer 37. On the other hand, since the read mode RM is applied to the AND gate 33 via the inverter 32,
The AND gate 33 is in an operating state and guarantees the operation of the column decoder 18 and data output buffer 19.

In normal writing, chip enable CE and write enable WE are turned ON, and row address A ₀ ~
A ₅ , data input buffer 1 from DI ₁ terminal 20 based on the address specified by column address A ₆ to _{A 11}
Write the data set to 7 to the memory array.
In this case as well, the read mode of line 30 is turned OFF.

When reading adjacent data at once, read mode RM of line 30 is turned ON. When this read mode RM is ON, the AND gate 33 becomes inactive and the AND gate 34 becomes active instead.
Therefore, during a read operation, data for one row of memory array 16 designated by row addresses A ₀ to _{A 5} is read out and stored in data output buffer 37 as is. At this time, the column address buffer 38 operates simultaneously through the path of the AND gate 34 and the OR gate 36, and the column address A ₆ of the column address buffer 14 is
A ₁₁ is transferred to column address buffer 38. The contents of this column address buffer 38 are stored in the column decoder 4.
0, the selection circuit 39 selects one bit of the data output buffer 37 indicated by the column address, and outputs it from the data output DO ₂ terminal 43 via the data output buffer 42. The contents of the column address buffer 38 are also applied to a count up circuit 41, and the address is counted up by 1 and set in the column address buffer 38 again. This is repeated every time one read pulse RP is applied.

According to the configuration shown in FIG. 4, once one row of data is read from the memory array 16 to the data output buffer 37, the read mode RM is turned OFF and the row address buffer 10 and column address buffer 14 are By setting the address according to the request, the contents of the data output buffer 37 corresponding to the previous request are read out one bit at a time from the DO ₂ terminal 43 using the read pulse RP.
In parallel with this, the memory array 1 is connected via the data input buffer 17 or data output buffer 19.
6, data can be read and written.

FIG. 5 shows an example of a configuration that allows one bit reading and one row reading from the memory array 16. In the figure, in the case of 1-bit readout, the row decoder 1 selects the memory array 16-1 of 64 rows x 64 columns.
One row of data is taken out in response to the output signal No. 5 and input to the selection circuit group 99 via the sense amplifier group 16-2 in correspondence with each bit. The partial column decoder groups 18-1 to 18-64 correspond to the column decoder 18 in FIG. 4, and decode the column address information from the column address buffer 14, and send the decoded output results to the respective corresponding selection circuits. Enter group 99. Note that partial sequence decoder groups 18-1 to 18
-64 is performed only when the signal from the AND gate 33 is ON, and corresponds to a specific bit specified by the column address information among the 64 partial column decoder groups 18-1 to 18-64. It is assumed that only the selected partial sequence decoder outputs an ON signal, and the others output an OFF signal to the selection circuit group. and,
The selection circuit group 99 selects partial column decoders 18-1 to 18-64 from among the data of one row of the memory cell array input from the sense amplifier group 16-2.
Select one bit corresponding to the ON signal from among the output signals of
Transfer to 9.

On the other hand, in the case of reading one row, one row of data is extracted from the memory cell array 16-1 in the same way as in the case of reading one bit. data is directly transferred to the data output buffer 37. AND gate 3 at data output buffer 37
When output 4 is ON, that is, read mode RM is
When ON, one row of data output from memory array 16 is set.

FIG. 6 shows another embodiment of the invention. In the example in Figure 4, it is possible to read data for one row of consecutive addresses in parallel with normal reading and writing, whereas in the example in Figure 6, normal reading and writing can be performed. In parallel with writing, data for one row of consecutive addresses can be written. In FIG. 6, the same numbers as in FIG. 3 correspond to the same parts. Further, the column address buffer 14 is provided so as to be shared by the column decoder 18 and the column address buffer 66, and the address signal lines are also shared halfway, resulting in a structure that minimizes the increase in chip area due to multifunctionalization. This is the same as shown in Figure 4.

During normal 1-bit read/write, write mode on line 52 and write end pulse on line 54
EP is turned OFF. The write mode WM is activated via the inverter 55, and the write end pulse is
EP is applied to the AND gate 60 via the inverter 56, and when the write mode WM and write end pulse EP are OFF, the output of the AND gate 60 is applied to the column decoder 18 and data output buffer 19 via the OR gate 63. given and allows normal reading. Also, the write end pulse EP is given to AND gates 59 and 62 via an inverter 56, and the write end pulse EP
When OFF, the row decoder 15, column decoder 18 and data input buffer 17 are energized and the normal 1
Enable bit writing.

Memory array 16 and data input buffer 65 are interconnected so that one row of data can be read and written between memory array 16 and data input buffer 65. The data input buffer 65 further receives 1-bit write data from the data input DI ₂ terminal 51.
It is designed to be input via 0. The input bit location is the location indicated by the address in column address buffer 66 that is decoded by column decoder 67. Column address buffer 66 is connected to column address buffer 14 and is in write mode WM5.
2 is ON, the column address in the column address buffer 14 is received at the output of the AND gate 57. The contents of column address buffer 66 are incremented by one by count up circuit 68. These are activated every time a write pulse 53 is applied,
While counting up the contents of the column address buffer 66, data from the data input buffer 50 is input into the data input buffer 65 bit by bit at the bit position indicated by the column address buffer 66.

The row address input line 9 is connected to the row address buffer 69, and the write mode WM52 is
When ON, the output of AND gate 57 sets the row address. When the write end pulse EP is applied, the address of the row address buffer 69 is AND
The output of gate 58 is decoded by row decoder 70 and energizes memory array 16 through multiplexer 71 to write one row of data in data input buffer 65 to that row address location.

When attempting to perform a write operation for one line, turn on the write mode WM and input addresses A ₀ to A ₁₁ . Since the write mode WM is ON, addresses are set in the row address buffer 69 and column address buffer 66, and since the write end pulse EP is not applied,
The memory array 16 is activated by decoding by the row decoder 15, and data for one row is transferred to the data input buffer 65.
is read out. When one row of data is read to the buffer 65, a write pulse WP is issued and DI ₂
Write data is inputted to terminal 51 and inputted via data input buffer 50 to the position indicated by column address buffer 66 in data input buffer 65 .
At the same time, the column address buffer 66 is counted up by one by a count up circuit 68. Repeat this operation every time a write pulse WP is issued,
Enter data for a maximum of one line. When data input is completed, a write end pulse EP is applied, the address set in the row address buffer 69 is decoded by the row decoder 70, and the data input buffer 6
Data for one line in 5 is written.

According to the configuration shown in FIG. 6, once one row of data is read from the memory array 16 to the data input buffer 65, the write mode WM is turned OFF,
By setting addresses according to separate requests in the row address buffer 10 and the column address buffer 14, the data input buffer 6 is read bit by bit from the DI ₂ terminal 51 by the write pulse WP.
While inputting data to 5, in parallel, data input buffer 17 and data output buffer 19
Data can be read from and written to the memory array 16 via the memory array 16.

In the example shown in Fig. 4, parallel operations of normal read/write and continuous mode reading using read pulse RP are possible, and in the example shown in Fig. 6, parallel operation of normal reading/writing and continuous mode reading using write pulse WP is possible. Although parallel write operations are possible, these two cases can be combined to also allow normal read write operations and parallel read write operations in continuous mode.

FIG. 7 shows a schematic configuration of a computer processing device including a storage device of the present invention. FIG. 7 shows a storage device 1, a storage control device 2, a channel unit 3, an instruction unit 4, an execution unit 5-1, an execution unit 5-2,
Requests to the storage device 1 constituted by the storage control device 7 are issued from the instruction unit 4, the channel unit 3, the execution unit 5-1, and the execution unit 5-2. 7 to the storage device 1. Among these requests, requests in continuous mode, which is a feature of the present invention, can be considered.
For example, if a page-by-page request in a virtual memory system is issued from the channel unit 3, and if the execution unit 5-2 is a unit dedicated to performing array operations that handle multiple variables and data, then
A memory request is issued when the amount of data is large and address references are continuous. These continuous mode requests are processed only via the storage controller 7.

Reading from the storage device 1 in continuous mode is performed in the following procedure.

(1) The storage control device 7 issues a read request to the storage control device 2, and under the control of the storage control device 2, the read mode terminal RM in the storage device 1 is activated.
Turn on the data output buffer 37 (Figure 4)
Read consecutive data. Thereafter, the storage controller 2 can process normal requests.

(2) The storage control device 7 sends a read pulse RP to the storage device 1, sequentially reads necessary data from the data output buffer 37, and sends the data to the request destination channel unit 3 or execution unit 5-.
Transfer the read data to 2.

Further, writing to the storage device 1 in continuous mode is performed in the following procedure.

(1) The storage control device 7 issues a write request to the storage control device 2, and under the control of the storage control device 2, the write mode WM of the storage device is turned on and the data input buffer 65 (FIG. 6) is sent. Read one continuous row of data. After that, the storage control device 2 can process normal requests until (3).

(2) The storage control device 7 sends a write pulse WP to the storage device 1 and sequentially writes the write data from the channel unit 3 or the execution unit 6 into the data input buffer 65.

(3) After writing the necessary write data to the data input buffer 65 according to (2), the write end pulse EP is turned ON under the control of the storage control device 2.
and writes the value of data input buffer 65 to the memory array.

In continuous mode reading, if all the values in the data output buffer 37 are read and there is more data to read, it is necessary to return from step (2) to step (1). Also, a similar situation occurs when writing, but in this case, after performing step (3), repeat the step again.
We will start from (1).

FIG. 8 is a diagram showing in detail a storage device and a storage control device showing the features of the present invention. 1 is a storage device,
2 and 7 are storage control devices; 100 is a storage element;
101 is an address line, 102 is a write data line,
103 is a request control line, 104 is a read data line, 105 is an address register, 106 is a memory request control circuit, 107 is a multiplexer, 108 is a write data register, 109 is a read data register, 110 is a memory chip enable control line, 111 is a Read mode control line, 1
12 is a write enable control line, 113 is a read data line, 114 is an address line, 115 is a read count line, 116 is a request control line, 117
and 118 is a multiplexer, 119 is an address register, 120 is a read count register,
121 is a memory request control circuit, 122 is a count up circuit, 123 is a count down circuit, 124 is an address detection circuit, 125 is a zero detection circuit, 126 is a read data register, 127
1 is a read pulse control line, 128 is a read mode request control line, 129 is an address register, 1
30 is a row address line, 131 is a column address line, 1
32 is a write data buffer, 133 is a write data line, and 134 and 135 are read data buffers. First, the flow of a normal memory request will be described, and then the flow in continuous mode, which is a feature of the present invention, will be described.

A normal memory request is made by instruction unit 4,
It is issued to the storage controller 2 from the channel unit 3, execution unit 5-1, and execution unit 5-2. At that time, the information on the address line 101 is set in the address register 105, and the information on the address line 101 is set in the address register 105.
Address register 1 of storage device 1 via 07
After being set to 29, it is divided into a row address line 130 and a column address line 131, and set to the row address buffer 10 and column address buffer 14 of the storage element 100, respectively. The request control line 103 is information for identifying writing and reading.
The request is input to the memory request control circuit 106, and if it is a write request, the write enable control line 112 is turned ON to specify writing to the memory element 100. At the same time, information on the write data line 102 is set in the write data register 108 and written to the storage element 100 via the write data buffer 132 of the storage device 1. At this time, the addresses written are the values of the row address buffer 10 and column address buffer 14. Furthermore, if the value of the request control line 103 indicates reading,
After reading the contents of the memory specified by the addresses of the row address buffer 10 and column address buffer 14 described above and setting them in the read data buffer 135, the contents are transferred to the read data line via the read data register 109 of the storage control device 2. 104, the request is transferred to the request destination. Note that when issuing a request to the storage device 1, the memory request control circuit 106 uses the memory chip enable control line 11.
0 is turned ON to enable the storage element 100 to operate.

Next, the flow of memory requests in continuous mode, which is a feature of the present invention, will be described. In this embodiment, the request is limited to read requests only, but as explained in FIG. 6, requests for write can also be made in continuous mode. A request is issued to the storage controller 7 from the execution unit 5-2 or the channel unit 3. Information on address line 114 is set in address register 119 via multiplexer 117, and information on read count line 115 is set in read count register 120 via multiplexer 118. At the same time, the information on the request control line 116 is input to the memory request control circuit 121, and if it is a read request, the read mode request control line 128 is turned ON to notify the memory request control circuit 106 that a request in continuous mode has occurred. tell. Memory request control circuit 106
Now, wait for the completion of the normal memory request (immediately if there is no normal request) and turn on the read mode control line 111. Information on this control line is input to the read mode terminal RM30 of the memory element 100. At the same time, the information in the address register 119 is set in the address register 129 of the storage device 1 via the multiplexer 107, and then divided into a row address line 130 and a column address line 131 and input to the storage element 100. When read mode terminal RM30 is ON, information on row address line 130 is set in row address buffer 10 of storage element 100, and information on column address line 13 is set in row address buffer 10 of storage element 100.
Information of 1 is set in the column address buffer 38, and data for one row is read from the memory array 16 based on the value of the row address buffer 10 and set in the data output buffer 37. When the above processing is completed, the memory request control circuit 106 is released and normal memory request processing becomes possible. Subsequently, the memory request control circuit 121
The read pulse control line 127 is turned ON (turned OFF after a certain period of time), and this information is input to the read pulse terminal RP31 of the storage element 100. In the memory element 100, when the read pulse terminal RP31 is turned ON, 1-bit data is extracted from the previously set data output buffer 37 based on the value of the column address buffer 38, and is sent to the read data buffer 134 via the data output buffer 42. is set to . At the same time, the value of the column address buffer 38 is input to the count up circuit 41, counted up by 1, and the value of the column address buffer 38 is inputted to the count up circuit 41.
is set to . This count up means updating the column address for reading the next 1 bit from the data buffer 37.

Furthermore, the following operations are performed in parallel in the storage control device 7. The value of the address register 119 is counted up by 8 in the count up circuit 122 and then set in the address register 119 again. Assume that the value of the address register 119 indicates a byte address, and if 8 bytes of data are to be read in one read request, the address to be read next needs to be increased by 8. The value of the read count register 120 is counted down by 1 in the countdown circuit 123, and then set in the read count register 120 again. Note that the value of the read count register specifies the number of words (8 bytes) to be read.

The read data set in the read data buffer 134 is transferred to the request destination via the read data register 126 via the read data line 113. After this, the memory request control circuit 121 again reads the next data.
Turn on the read pulse control line 127. From then on,
The above-described operation is repeated as many times as necessary, and reading is completed as follows. That is, the zero detection circuit 125 detects whether the value of the read count register 120 has become zero, and if it becomes zero, sends the information to the memory request control circuit 121 and ends the process.

The memory request control circuit 121 turns on the read mode request control line 128, reads one row of data from the memory array 16 of the storage element 100 to the data output buffer 37, and sequentially reads the data one bit at a time. After reading the data from the data output buffer 37, it is necessary to turn on the read mode request control line 128 again to read one row of data from the memory array 16 to the data output buffer 37. This repeated operation is performed until the value of read count register 120 becomes zero. Data output buffer 3
The address detection circuit 124 detects whether or not the data of No. 7 has been read out.
The detection result is reported to the memory request control circuit 121 and used to determine whether to turn on the read mode request control line 128.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the configuration of a general computer processing device, FIG. 3 is a block diagram showing a conventional general storage device, and FIG. 4 is a block diagram showing an embodiment of the present invention. 5 is a diagram showing a part of FIG. 4 in detail, FIG. 6 is a block diagram showing another embodiment of the present invention, FIG. 7 is a block diagram for explaining the present invention, and FIG. 7 is a block diagram showing details of the storage device and storage control device of FIG. 7. FIG. 10... Row address buffer, 14... Column address buffer, 16... Memory array, 17...
Data input buffer, 18...Data output buffer, 37...Data output buffer, 38...Column address buffer, 39...Selection circuit, 40...Column decoder, 41...Count up circuit, 42...
...Data output buffer, 50 and 65...Data input buffer, 66...Column address buffer,
67... Row decoder, 68... Count up circuit, 69... Row address buffer, 70... Row decoder.

Claims (1)

[Scope of Claims] 1: a memory array; a first means for accessing the memory array by row and column addresses; and a first means for reading and writing data to and from storage locations specified by the row and column addresses; a second means for accessing the memory array according to an address and reading a group of data from a group of storage locations specified by the address; an address buffer to which the row or column address is input; and at least a part of the output signal line from the address buffer; A storage device characterized in that it is provided so as to be shared by the first means and the second means. 2. The storage device according to claim 1, further comprising means for inhibiting the read operation of the first means during a period when the second means is performing the read operation. 3. The storage device according to claim 1 or 2, characterized in that the storage device is configured such that the operations of the first means and the third means can be performed simultaneously. 4 a memory array; first means for accessing said memory array by row and column addresses and reading and writing data to and from storage locations specified by said row and column addresses; a second means for accessing the array and writing a data group to a group of storage locations specified by the address; and a third means for sequentially aligning predetermined data and supplying the aligned data group to the second means. and an address buffer into which the row or column address is input;
A storage device characterized in that at least a part of the output signal line from the address buffer is provided so as to be shared by the first means and the second means. 5. The storage device according to claim 4, further comprising means for inhibiting the write operation of the first means during a period when the second means is performing a write operation. 6. The storage device according to claim 4 or 5, characterized in that the storage device is configured such that the operations of the first means and the third means can be performed simultaneously.