JP3872922B2 - Semiconductor memory device and memory embedded logic LSI - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having a row / column simultaneous access function and a memory-embedded logic LSI.
[0002]
[Prior art]
The bank interleaving function of the semiconductor memory device is a function that executes a series of operations such as word line activation, read / write operation, and precharge operation with a certain time difference in two or more different banks. At this time, a column-related operation may be executed in a certain bank and a row-related operation may be executed in another bank. For example, after activating a word line of a row address specified in a certain bank, a write operation or a read operation (column system) is performed on a memory cell at the intersection of a bit line of a column address specified in the same bank and the word line. This is a case where a word line with a different row address designated by another bank is activated (row-related operation) at the same time as the (operation) is executed.
[0003]
A conventional technique for realizing this row / column simultaneous access function will be described. FIG. 9 is a block diagram showing a configuration of a conventional semiconductor memory device for realizing simultaneous access.
[0004]
The memory cell array 101 is configured by arranging regular memory cells MC having a predetermined capacity in a matrix of rows and columns. The memory cell array 101 is assigned a two-dimensional address space represented by an Nra bit row address and an Nca bit column address. The size of the row address and the column address is determined according to the storage capacity of the memory cell array 101.
[0005]
The row decode circuit 102 is for decoding a row address and selecting a row of the memory cell array 101, and selects a word line WL based on the row address. The column decode circuit 103 decodes a column address and selects a column of the memory cell array 101, and selects a bit line BL based on the column address.
[0006]
The command generation circuit 104 decodes an Ncm-bit coded command and activates the word line WL (row command), and a command for executing read and write operations (column command). Is generated.
[0007]
In operations such as reading and writing, the memory cell MC at the intersection of the word line WL and the bit line BL respectively selected by the row decoding circuit 102 and the column decoding circuit 103 is accessed, and the memory instruction MC operates according to an operation instruction based on the command. Operations such as data reading and writing are performed on the cells MC. However, during a write operation, Nd-bit write data input from the outside is written into the memory cell.
[0008]
The row / column simultaneous access function at the time of bank interleaving is a function for executing a column-related operation in a certain bank and simultaneously executing a row-related operation in another bank. For this reason, it may be necessary to simultaneously issue column addresses and data for column-related operations and row addresses for row-related operations. In addition, it is necessary to issue a row command and a column command. Therefore, as input pins, a column address line 105 for transmitting an Nca bit column address, a data line 106 for transmitting Nd bit data, a row address line 107 for transmitting an Nra bit row address, and A sum Ni (Ni = Nca + Nd + Nra + Ncm) of command lines 108 for transmitting Ncm bit commands is required.
[0009]
Here, the number of bits Ncm of the command line 108 is the number of commands = 2.^NcmIt is calculated from. For example, if the number of commands is 16, the number of bits Ncm is 4 bits. As described above, there is no problem as long as the LSI can prepare input pins independently, but there is a practical limitation on the number of pins.
[0010]
In order to avoid this limitation on the number of pins, a configuration as shown in FIG. 10 is practical. The difference from FIG. 9 is that the pins used for the column address lines 105 and the data lines 106 and the pins used for the row address lines 107 are shared. The Nmx-bit address and data line 110 after the sharing is compared with the sum of the number of bits of the column address line 105 and the data line 106 (Nca + Nd) and the number of bits of the row address line 107 (Nra). If there are as many bits (pins) as possible, they can be shared.
[0011]
For example, if the sum of the number of bits of the column address line 105 and the data line 106 is 12, and the number of bits of the row address line 107 is 13, the address and data can be input with the larger 13 bits. In this example, the common address and data line 110 is Nmx = 13 bits, the signal line is Nra = 13 bits for transmitting the row address, and the signal line for transmitting the column address and data is Nca + Nd + 1 = 13. A bit. One extra bit of the signal line for transmitting the column address and data is Don't Care.
[0012]
If what is input to the common Nmx-bit address and data line 110 is a row address, a row command is also input to the command line 111 for transmitting the command. If what is input to the address and data line 110 is a column address, a column command is also input to the command line 111. Therefore, when a row address is input, a signal for validating the output is output from the command generation circuit 104 to the selector 105, and the row address is input to the row decoding circuit 102. When a column address and data are input, a signal for enabling the output is output from the command generation circuit 104 to the selector 106, and the column address is input to the column decoding circuit 103, thereby enabling data writing. This technique is generally called address multiplexing.
[0013]
[Problems to be solved by the invention]
However, when address multiplexing is performed, it is impossible to execute the row / column simultaneous access function operation seamlessly (seamless state) because the row operation and the column operation cannot be executed simultaneously.
[0014]
In addition, in the test of the row / column simultaneous access function of the semiconductor memory device when the address multiplexing is performed, it is essential to minimize the number of test pins. It is impossible to run and test seamlessly.
[0015]
As described above, in a semiconductor memory device or memory-embedded logic LSI having a row / column simultaneous access function, the operation of the row / column simultaneous access function is seamless when there is a limited number of pins as in the case of address multiplexing. There is a problem that the operation of the row / column simultaneous access function cannot be executed even in a test that requires a reduction in the number of pins.
[0016]
Therefore, the present invention has been made in view of the above-described problem, and a required address or data is latched in advance in the previous operation cycle, and the latched address or data is simultaneously used with the address or data used in the current operation cycle. It is an object of the present invention to provide a semiconductor memory device and a memory-embedded logic LSI capable of realizing a row / column simultaneous access function operation with a small number of pins as in the case of address multiplexing.
[0017]
[Means for Solving the Problems]
  To achieve the above object, the present inventionOf the first embodiment ofA semiconductor memory device has memory cells arranged in a matrix.Having a first bank and a second bankMemory cell array and externalA column address signal and data to which a row address signal is input or whose bit number is smaller than the bit number of the row address signalAn external terminal to whichA data line for writing the data input together with the column address signal to the memory cell, a control circuit for generating a plurality of control signals based on a command input from the outside, and a first circuit generated by the control circuit In response to one control signal, the row address signal input to the external terminal isA first selector for selecting whether to output;A row decode circuit for selecting one of the first bank and the second bank by decoding the row address signal output from the first selector; and a second control generated by the control circuit A latch circuit for storing the column address signal and data input to the external terminal in response to a signal; and first and second input terminals; and the input from the external terminal to the first input terminal. The column address signal and data, or the column address signal and data input from the latch circuit to the second input terminal are selected and output in response to a third control signal generated by the control circuit. 1 and the column address signal output from the first multiplexer in response to a fourth control signal generated by the control circuit. And a second selector for selecting whether to output the data output from the first multiplexer together with the column address signal to the data line, and the column address output from the second selector. A column decode circuit for decoding a signal and selecting one of the columns of the first bank and the second bank, and the row address signal, the column address signal and data are sent to the row decode circuit, When a command to be simultaneously input to the column decode circuit and the data line is input to the control circuit, the control circuit stores the column address signal and data stored in the latch circuit with respect to the first multiplexer. The third control signal for selecting and outputting is output, and the first selector and the second selector are output. The first control signal and the fourth control signal to be set to be output to perform row-related operation on the row selected by the row decoding circuit in the first bank, and at the same time, in the second bank Execute column-related operations on the column selected by the column decode circuitIt is characterized by doing.
[0018]
  In addition, the present inventionOf the second embodiment ofA semiconductor memory device has memory cells arranged in a matrix.Having a first bank and a second bankMemory cell array and externalA column address signal and data to which a row address signal is input or whose bit number is smaller than the bit number of the row address signalAn external terminal to whichA row decoding circuit for decoding the row address signal to select one of the first bank and the second bank;
A column decode circuit for decoding the column address signal to select one of the first bank and the second bank, and an intersection of a row and a column selected by the row decode circuit and the column decode circuit A data line for writing the data input together with the column address signal to a certain memory cell, and provided between the external terminal and the row decoding circuit, and the row address signal to the row decoding circuit. A first selector for selecting whether or not to output, and provided between the external terminal and the column decode circuit, and the column address signal is input to the column decode circuit and together with the column address signal A second selector for selecting whether or not to output data to the data line; and between the external terminal and the second selector; A latch circuit that stores the column address signal and data input to the external terminal, and the column address signal and data input to the external terminal, or the column address signal and data stored in the latch circuit. A multiplexer for selecting and outputting to the second selector and a command for simultaneously inputting the row address signal to the row decode circuit and the column address signal and data to the column decode circuit and the data line are input from the outside. When this is done, the first selector is set to the output state, the multiplexer is made to select and output the column address signal and data stored in the latch circuit, and the second selector is set to the output state. A row selected by the row decode circuit in the first bank. Simultaneously running the row system operation for, running the column system operation on the selected column by the column decode circuit in the second bankIt is characterized by doing.
[0019]
  In addition, the present inventionOf the third embodiment ofA semiconductor memory device has memory cells arranged in a matrix.Having a first bank and a second bankMemory cell array and externalA column address signal and data to which a row address signal is input or whose bit number is smaller than the bit number of the row address signalThe external terminal to which is inputted and the row address signal are decoded.One of the first bank and the second bankA row decode circuit for selecting a row, and decoding the column address signalOne of the first bank and the second bankA column decode circuit for selecting a column and a memory cell at the intersection of a row and a column selected by the row decode circuit and the column decode circuit;ColumnA data line for writing the data input together with the address signal, and provided between the external terminal and the row decoding circuit;lineA first selector for selecting whether or not to output an address signal to the row decoding circuit; and provided between the external terminal and the column decoding circuit,ColumnAddress signal to the column decode circuit; andColumnA second selector for selecting whether to output the data input together with an address signal to the data line; the external terminal;1Between the selector and the input to the external terminal.The row address signalAnd a latch circuit for storing the input to the external terminalRow address signalOr the stored in the latch circuitRow address signalSelect one of the1A multiplexer that outputs to the selector oflineAddress signal to the row decoding circuit,The column address signal and data areColumn decode circuitAnd data line respectivelyWhen a command for simultaneous input is input from the outside,A control circuit for causing the multiplexer to select and output the row address signal stored in the latch circuit, to set the first selector to an output state, and to set the second selector to an output state. In addition, a row-related operation is performed on the row selected by the row decoding circuit in the first bank, and at the same time, a column-related operation is performed on the column selected by the column decoding circuit in the second bank.It is characterized by doing.
[0020]
  In addition, the present inventionOf the fourth embodiment ofMemory-embedded logic LSI has memory cells arranged in a matrixHaving a first bank and a second bankMemory cell array and externalA column address signal and data to which a row address signal is input or whose bit number is smaller than the bit number of the row address signalAn external terminal to which is input, andlineDecoding the address signalOne of the first bank and the second bankA row decoding circuit for selecting a row, andColumnDecoding the address signalOne of the first bank and the second bankA column decode circuit for selecting a column and a memory cell at the intersection of a row and a column selected by the row decode circuit and the column decode circuit;ColumnA data line for writing the data input together with the address signal, and provided between the external terminal and the row decoding circuit;lineA first selector for selecting whether or not to output an address signal to the row decoding circuit; and provided between the external terminal and the column decoding circuit,ColumnAddress signal to the column decode circuit; andColumnA second selector for selecting whether to output the data input together with an address signal to the data line; the external terminal;2Between the selector and the input to the external terminalColumnAddress signalAnd dataAnd a latch circuit for storing the input to the external terminalColumnAddress signalAnd dataOr the stored in the latch circuitColumnAddress signalAnd dataSelect one of the2A multiplexer that outputs to the selector oflineAddress signal to the row decoding circuit,The column address signal and data are supplied to a column decode circuit and a data line, respectively.When the command to input at the same time is input from the outside,Setting the first selector to the output state;Stored in the latch circuit in the multiplexerColumn address signal and dataSelect and output2Set the selector to output stateA control circuit, and performing a row-related operation on a row selected by the row decode circuit in the first bank, and at the same time a column for a column selected by the column decode circuit in the second bank Execute system operationIt is characterized by doing.
[0021]
  In addition, the present inventionOf the fifth embodiment ofMemory-embedded logic LSI has memory cells arranged in a matrixHaving a first bank and a second bankMemory cell array and externalA column address signal and data to which a row address signal is input or whose bit number is smaller than the bit number of the row address signalAn external terminal to which is input, andlineDecode the address signalEither the first bank or the second bankA row decoding circuit for selecting a row, andColumnDecode the address signalEither the first bank or the second bankA column decoding circuit for selecting a column ofA data line for writing the data input together with the column address signal to the memory cell at the intersection of the row and column selected by the row decoding circuit and the column decoding circuit;Provided between the external terminal and the row decoding circuit;lineA first selector for selecting whether or not to output an address signal to the row decoding circuit; and provided between the external terminal and the column decoding circuit,ColumnAddress signal to the column decode circuitAnd the data input together with the column address signal is transferred to the data lineA second selector for selecting whether to output toThe row address signal provided between the external terminal and the first selector and input to the external terminalAnd a latch circuit for storing the input to the external terminallineAddress signal,Or the stored in the latch circuitlineSelect one of the address signals, and select the first select signal.A multiplexer for outputting data to the data decoder, the row address signal to the row decode circuit, and the column address signal and data to the column decode circuit and the data line simultaneously.When a command for inputting to the external circuit is input from the outside, the multiplexer stores the latch circuit in the latch circuit.The row addressSelecting and outputting a signal, and the first selectorAnd a control circuit for setting the second selector to the output state, and simultaneously performing a row-related operation on the row selected by the row decode circuit in the first bank, Execute column-related operation on the column selected by the column decode circuit in the second bankIt is characterized by doing.
[0022]
In the semiconductor memory device or memory-embedded logic LSI having an interface with a small number of pins as in the case of address multiplexing, the present invention provides an address or address required in advance in the previous operation cycle in order to perform row and column operations simultaneously. It is possible to latch the data and issue the address or data latched simultaneously with the address or data used in the current operation cycle. Thereby, the operation of the row / column simultaneous access function can be realized, and the test of this state can be realized.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking as an example a semiconductor memory device having a memory cell array in which a two-dimensional address space of rows and columns is allocated.
[0024]
[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to the first embodiment of the present invention.
[0025]
The semiconductor memory device includes a memory cell array 11 in which memory cells MC are arranged in a matrix of rows and columns, a row decoding circuit 12 that selects a word line WL from an input row address, and a bit from an input column address. A column decode circuit 13 for selecting a line BL and a selector 14 for receiving a row address input to the input terminal IN1 and selecting whether or not to output the row address to the row decode circuit 12 are provided.
[0026]
The semiconductor memory device further includes a latch circuit 15 that latches a column address and data input to the input terminal IN1, a column address and data input to the input terminal IN1, and a column address and data output from the latch circuit 15. The multiplexer 16 receives data, selects one of them, and outputs the data. The selector 17 selects whether or not to output the signal received from the multiplexer 16 to the column decode circuit 13.
[0027]
Further, the semiconductor memory device receives a command input to the input terminal IN2, and generates a command generation circuit 18 that generates various commands, and a simultaneous issue command that is issued when simultaneously starting a row-related operation and a column-related operation. An AND circuit 19 that performs an AND operation with a row command and an AND circuit 20 that performs an AND operation with the simultaneous issue command and the column command are included.
[0028]
The memory cell array 11 is configured by arranging regular memory cells MC having a predetermined capacity in a matrix of rows and columns at the intersections of the word lines WL and the bit lines BL. The memory cell array 11 is assigned a two-dimensional address space represented by an Nra bit row address and an Nca bit column address. The number of bits of the row address and the column address is determined according to the storage capacity of the memory cell array 11. An Nra bit row address, or an Nca bit column address and Nd bit data are input to the input terminal IN1. The input terminal IN1 has the number of pins that can transmit the larger number of bits (Nmx) of Nra bits or (Nca + Nd) bits.
[0029]
In response to the control signal CL 1 from the AND circuit 19, the selector 14 selects whether or not to output a row address to the row decoding circuit 12. The row decode circuit 12 is for decoding a row address and selecting a row of the memory cell array 11, and selects a word line WL based on the row address.
[0030]
An Ncm bit command is input to the input terminal IN2. The command generation circuit 18 decodes an Ncm-bit coded command, causes the latch circuit 15 to latch a column address and data, and / ROW WITH to execute row / column simultaneous access. A COLUMN signal, an / ACTIVE signal (row command) for activating the word line WL, and a signal (column command) for executing a read or write operation are generated. Here, the write operation is taken as an example, and only the / WRITE signal is described. / Represents a bar and represents an inverted signal. The latch circuit 15 sets whether or not to latch the input column address and data in response to / LOAD.
[0031]
In response to / ROW WITH COLUMN, the multiplexer 16 having the first terminal and the second terminal receives a signal input to the first terminal and an output (column address and data) of the latch circuit 15 input to the second terminal. Is selected and output to the selector 17. In other words, the multiplexer 16 processes the column address and data input from the outside as a normal operation (operation that does not issue simultaneously), and the operation that simultaneously issues the column address and data latched in advance by the latch circuit 15. Depending on the case, the output is switched.
[0032]
In response to the control signal CL2 from the AND circuit 20, the selector 17 selects whether or not to output the column address and data output from the multiplexer 16 to the column decode circuit 13 and the data line DL, respectively. The column decode circuit 13 decodes a column address and selects a column of the memory cell array 11, and selects a bit line BL based on the column address.
[0033]
The AND circuit 19 performs an AND operation on / ROW WITH COLUMN and / ACTIVE output from the command generation circuit 18, and outputs a control signal CL1 based on the operation result. The AND circuit 20 performs a logical AND operation on / ROW WITH COLUMN and / WRITE output from the command generation circuit 18, and outputs a control signal CL2 based on the operation result.
[0034]
Next, an operation example of the row / column simultaneous access function of the semiconductor memory device according to the first embodiment will be described.
[0035]
In operations such as reading and writing, the memory cell MC at the intersection of the word line WL and the bit line BL selected by the row decoding circuit 12 and the column decoding circuit 13 is accessed. Then, operations such as data reading and writing are performed on the memory cell by an operation command based on the command. However, during the write operation, externally input write data is input via the data line.
[0036]
The row / column simultaneous access function at the time of bank interleaving is a function for executing a column-related operation in a certain bank and simultaneously executing a row-related operation in another bank. For this reason, it is necessary to simultaneously issue a column address and data for a column-related operation and a row address for a row-related operation. The operation of such a row / column simultaneous access function is as follows, taking a write page operation as an example.
[0037]
2A and 2B are timing charts showing the operation of the row / column simultaneous access function. In FIG. 2A, BANK # 0 and BANK # 1 indicate two banks of the semiconductor memory device. / ACTIVE, / PRECHAGE, / WRITE, and / LOAD indicate commands output from the command generation circuit 18 based on the command CM input to the input terminal IN2. / Represents a bar and represents an inverted signal. The row bank selection signal is supplied by some bits of the row address input to the input terminal IN1. The column bank selection signal is supplied by a column address and a part of data bits input to the input terminal IN1. The row address, column address, and data in FIG. 2A indicate signals input to the input terminal IN1.
[0038]
The column address and data in FIG. 2B are signals latched by the latch circuit 15 and further selected by the multiplexer 16 and output. / ROW WITH COLUMN indicates a command output from the command generation circuit 18 based on a command input to the input terminal IN2.
[0039]
First, an outline of the operation will be described. From the timing charts shown in FIGS. 2A and 2B, there are two cycles T9 and T15 in which row-related operations and column-related operations are simultaneously executed in different banks. In cycle T9, a write (Wt) operation is performed at BANK # 0 and an activation (Act) operation is performed at BANK # 1. At this time, the row (row) address is selected by RBa, the column (column) address is selected by CAe, and the write data is Ae. In cycle T15, activation (Act) operation is performed at BANK # 0, and write (Wt) operation is performed at BANK # 1. At this time, the row (row) side address is selected by RAb, the column (column) side address is selected by CBc, and the write data is Bc.
[0040]
As shown in FIG. 2A, the / LOAD signal is generated from the command generation circuit 18 in cycle T4, and the column address CAe and data Ae are latched in the latch circuit 15. Then, in cycle T9, the command generation circuit 18 generates a / ROW WITH COLUMN signal for simultaneously issuing a row address / column address and data. As a result, the row address RBa input to the input terminal IN1 is issued, and at the same time, the column address CAe and data Ae latched in advance by the latch circuit 15 are issued.
[0041]
Further, the / LOAD signal is generated from the command generation circuit 18 in cycle T12, and the column address CBc and the data Bc are latched in the latch circuit 15. In a cycle T15, the command generation circuit 18 generates a / ROW WITH COLUMN signal for simultaneously issuing a row address / column address and data. As a result, the row address RAb input to the input terminal IN1 is issued, and at the same time, the column address CBc and data Bc latched in advance by the latch circuit 15 are issued.
[0042]
Next, the operation for realizing the row / column simultaneous access function will be described in detail. As shown in FIG. 2A, the row address RAa is input to the input terminal IN1 in the cycle T1. At the same time, the command generation circuit 18 outputs “L” of the / ACTIVE signal instructing activation to the AND circuit 19. The AND circuit 19 outputs “L” of the control signal CL 1 that enables the output to the selector 14. As a result, the selector 14 outputs the row address RAa to the row decode circuit 12. At this time, since the row bank selection signal is “L”, BANK # 0 is activated (Act). The selector 14 validates the output when “L” is input, and invalidates the output when “H” is input. Also, when the row bank selection signal is “L”, BANK # 0 is selected, and when it is “H”, BANK # 1 is selected.
[0043]
The row address RAa is also input to the first terminal of the multiplexer 16 and the latch circuit 15. Since “H” of the / ROW WITH COLUMN signal is input to the multiplexer 16, the multiplexer 16 outputs the row address RAa input to the first terminal to the selector 17. However, since “H” of the / WRITE signal and “H” of the / ROW WITH COLUMN signal are input from the command generation circuit 18 to the AND circuit 20, the “H” of the control signal CL 2 is input from the AND circuit 20 to the selector 17. "Is entered. Therefore, the selector 17 becomes invalid and the row address RAa is not output. The selector 17 validates the output when “L” is input, and invalidates the output when “H” is input. Subsequently, in cycles T2 and T3, BANK # 0 is in a non-operation state.
[0044]
Next, in cycle T4, the column address CAe and the data Ae are input to the input terminal IN1. At the same time, “/ L” of the / LOAD signal is output from the command generation circuit 18 to the latch circuit 15 based on the command input to the input terminal IN2. As a result, the column address CAe and the data Ae are latched in the latch circuit 15. At this time, the column address CAe and the data Ae are also input to the selector 14, but both the / ACTIVE signal and the / ROW WITH COLUMN signal output from the command generation circuit 18 to the AND circuit 19 are "H". “H” of the control signal CL 1 is input from the AND circuit 19 to the selector 14. Therefore, the selector 14 becomes invalid and the column address CAe and data Ae are not output.
[0045]
Next, in cycles T5 to T8, the column address CAa and data Aa, CAb and Ab, CAc and Ac, CAd and Ad input to the input terminal IN1 are sequentially input to the multiplexer 16. At the same time, “ROW” COLUMN “H” is output from the command generation circuit 18 and input to the multiplexer 16 and the first terminal of the AND circuit 20. In the multiplexer 16, since “H” of / ROW WITH COLUMN is input, the column address and data input to the first terminal are selected and output to the selector 17.
[0046]
At this time, “H” of / ROW WITH COLUMN is input to the first terminal of the AND circuit 20, and “L” of the / WRITE signal is input from the command generation circuit 18 to the second terminal of the AND circuit 20. For this reason, “L” of the control signal CL 2 for enabling the output is output from the AND circuit 20 to the selector 17. Accordingly, the selector 17 sequentially outputs the column address CAa and the data Aa, CAb and Ab, CAc and Ac, CAd and Ad to the column decode circuit 13. At this time, since the column bank selection signal is “L”, BANK # 0 is in a write (Wt) state. In the column bank selection signal, BANK # 0 is selected when “L”, and BANK # 1 is selected when “H”.
[0047]
Next, in cycle T9 in which row / column simultaneous issuance is performed, the operation is as follows. As shown in FIG. 2A, in a cycle T9, the row address RBa is input to the input terminal IN1. At the same time, “L” of the / ACTIVE signal is output from the command generation circuit 18 to the AND circuit 19. The AND circuit 19 outputs “L” of the control signal CL 1 that enables the output to the selector 14. As a result, the selector 14 outputs the row address RBa to the row decode circuit 12. At this time, since the row bank selection signal is “H”, BANK # 1 is activated (Act).
[0048]
At the same time, “ROW” COLUMN “L” is output from the command generation circuit 18 and input to the multiplexer 16 and the first terminal of the AND circuit 20. Since the multiplexer 16 receives “L” of / ROW WITH COLUMN, the output from the latch circuit 15 input to the second terminal, that is, the column address CAe and the data Ae are selected and output to the selector 17. The At this time, “LOW” of / ROW WITH COLUMN is input from the command generation circuit 18 to the first terminal of the AND circuit 20, and “L” of / WRITE from the command generation circuit 18 is input to the second terminal of the AND circuit 20. Is entered. For this reason, “L” of the control signal CL 2 for enabling the output is output from the AND circuit 20 to the selector 17. As a result, the selector 17 outputs the column address CAe and the data Ae to the column decode circuit 13. At this time, since the column bank selection signal is “L”, BANK # 0 is in a write (Wt) state.
[0049]
Thereafter, in the cycle T10, as in the cycles T5 to T8, the column address CAf and the data Af are input to the input terminal IN1, and the BANK # 0 enters the write (Wt) state. Further, in cycle T11, BANK # 0 is in a precharge (Prec) state.
[0050]
Next, in cycle T12, as in cycle T4, column address CBc and data Bc are input to input terminal IN1. At the same time, “/ L” of the / LOAD signal is output from the command generation circuit 18 to the latch circuit 15 based on the command input to the input terminal IN2. As a result, the column address CBc and the data Bc are latched in the latch circuit 15. At this time, the column address CBc and the data Bc are also input to the selector 14, but both the / ACTIVE signal and the / ROW WITH COLUMN signal output from the command generation circuit 18 to the AND circuit 19 are "H". “H” of the control signal CL 1 is input from the AND circuit 19 to the selector 14. Therefore, the selector 14 becomes invalid and the column address CBc and data Bc are not output.
[0051]
Next, in cycles T13 and T14, the column address CBa and data Ba, CBb, and Bb input to the input terminal IN1 are sequentially input to the multiplexer 16. At the same time, “ROW” COLUMN “H” is output from the command generation circuit 18 and input to the multiplexer 16 and the first terminal of the AND circuit 20. In the multiplexer 16, since “H” of / ROW WITH COLUMN is input, the column address and data input to the first terminal are selected and output to the selector 17.
[0052]
At this time, “ROW” / COLUMN “H” is input from the command generation circuit 18 to the first terminal of the AND circuit 20, and “L” of the / WRITE signal is input from the command generation circuit 18 to the second terminal of the AND circuit 20. Is entered. For this reason, “L” of the control signal CL 2 for enabling the output is output from the AND circuit 20 to the selector 17. As a result, the selector 17 sequentially outputs the column address CBa and the data Ba, CBb, and Bb to the column decode circuit 13. At this time, since the column bank selection signal is “H”, BANK # 1 is in a write (Wt) state.
[0053]
Next, in cycle T15 in which row / column simultaneous issuance is performed, the operation is as follows. As shown in FIG. 2A, the row address RAb is input to the input terminal IN1 in the cycle T15. At the same time, “L” of the / ACTIVE signal is output from the command generation circuit 18 to the AND circuit 19. The AND circuit 19 outputs “L” of the control signal CL 1 that enables the output to the selector 14. As a result, the selector 14 outputs the row address RAb to the row decode circuit 12. At this time, since the row bank selection signal is “L”, BANK # 0 is activated (Act).
[0054]
At the same time, “ROW” COLUMN “L” is output from the command generation circuit 18 and input to the multiplexer 16 and the first terminal of the AND circuit 20. In the multiplexer 16, since “L” of / ROW WITH COLUMN is inputted, the output from the latch circuit 15 inputted to the second terminal, that is, the column address CBc and the data Bc are selected and outputted to the selector 17. The At this time, “LOW” of / ROW WITH COLUMN is input from the command generation circuit 18 to the first terminal of the AND circuit 20, and “L” of / WRITE from the command generation circuit 18 is input to the second terminal of the AND circuit 20. Is entered. For this reason, the control signal “L” for enabling the output is output from the AND circuit 20 to the selector 17. As a result, the selector 17 outputs the column address CBc and the data Bc to the column decode circuit 13. At this time, since the column bank selection signal is “H”, BANK # 1 is in a write (Wt) state.
[0055]
Thereafter, in cycles T16 and T17, as in cycles T13 and T14, the column address CBd and data Bd,... Are input to the input terminal IN1, and BANK # 1 enters the write (Wt) state.
[0056]
By the operation as described above, even in a semiconductor memory device having a small number of pins as shown in FIG. 1, the operation of the row / column simultaneous access function for simultaneously issuing the row address / column address and data can be realized.
[0057]
As described above, according to the first embodiment, necessary column addresses and data are latched in advance in the previous operation cycle, and the column address latched simultaneously with the row address input in the current operation cycle. By issuing data and data, the operation of the row / column simultaneous access function can be realized with a small number of pins as in the case of address multiplexing.
[0058]
[Second Embodiment]
Next explained is a semiconductor memory device according to the second embodiment of the invention.
[0059]
FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to the second embodiment of the present invention. In the first embodiment, the column address and data are latched in advance and issued simultaneously. In the second embodiment, a row address is latched in advance and is then issued simultaneously.
[0060]
The semiconductor memory device includes a memory cell array 11 in which memory cells MC are arranged in a matrix of rows and columns, a row decoding circuit 12 that selects a word line WL from an input row address, and a bit from an input column address. The column decode circuit 13 for selecting the line BL, the latch circuit 21 for latching the row address inputted to the input terminal IN1, the row address inputted to the input terminal IN1, and the row address outputted from the latch circuit 21 It has a multiplexer 22 that receives and selects one of them and outputs it, and a selector 14 that selects whether or not to output a signal received from the multiplexer 22 to the row decoding circuit 12.
[0061]
The semiconductor memory device further includes a selector 17 that selects whether or not to output the column address and data input to the input terminal IN1 to the column decode circuit 13.
[0062]
Further, the semiconductor memory device receives a command input to the input terminal IN2, and generates a command generation circuit 18 that generates various commands, and a simultaneous issue command that is issued when a row-related operation and a column-related operation are started simultaneously. An AND circuit 19 that performs an AND operation with a row command and an AND circuit 20 that performs an AND operation with the simultaneous issue command and the column command are included.
[0063]
The memory cell array 11 is configured by arranging regular memory cells MC having a predetermined capacity in a matrix of rows and columns at the intersections of the word lines WL and the bit lines BL. The memory cell array 11 is assigned a two-dimensional address space represented by an Nra bit row address and an Nca bit column address. The number of bits of the row address and the column address is determined according to the storage capacity of the memory cell array 11. An Nra bit row address, or an Nca bit column address and Nd bit data are input to the input terminal IN1. The input terminal IN1 has the number of pins that can transmit the larger number of bits (Nmx) of Nra bits or (Nca + Nd) bits.
[0064]
In response to the control signal CL1 from the AND circuit 20, the selector 17 selects whether or not to output a column address and data to the column decode circuit 13 and the data line DL, respectively. The column decode circuit 13 decodes a column address and selects a column of the memory cell array 11, and selects a bit line BL based on the column address.
[0065]
An Ncm bit command is input to the input terminal IN2. The command generation circuit 18 decodes an Ncm-bit coded command, and / LOAD signal for causing the latch circuit 21 to latch a row address, and / COLUMN WITH ROW signal for executing simultaneous row / column access. A / ACTIVE signal (row command) for activating the word line WL and a signal (column command) for executing a read or write operation are generated. Here, the write operation is taken as an example, and only the / WRITE signal is described. The latch circuit 21 sets whether or not to latch the input row address in response to / LOAD.
[0066]
The multiplexer 22 having the first terminal and the second terminal responds to / COLUMN WITH ROW, and either the signal input to the first terminal or the output (row address) of the latch circuit 21 input to the second terminal. Is selected and output to the selector 14. In other words, the multiplexer 22 processes a row address input from the outside as a normal operation (operation that does not issue simultaneously) and a case that processes the row address that is latched in advance by the latch circuit 21 as an operation. Switch the output.
[0067]
In response to the control signal CL 1 from the AND circuit 19, the selector 14 selects whether or not to output the row address output from the multiplexer 22 to the row decode circuit 12. The row decode circuit 12 is for decoding a row address and selecting a row of the memory cell array 11, and selects a word line WL based on the row address.
[0068]
The AND circuit 19 performs a logical AND operation on / COLUMN WITH ROW and / ACTIVE output from the command generation circuit 18, and outputs a control signal CL1 based on the operation result. The AND circuit 20 performs a logical AND operation on / COLUMN WITH ROW and / WRITE output from the command generation circuit 18, and outputs a control signal CL2 based on the operation result.
[0069]
Next, an operation example of the row / column simultaneous access function of the semiconductor memory device according to the second embodiment will be described.
[0070]
Similar to the first embodiment, the row / column simultaneous access function at the time of bank interleaving is a function for executing a column-related operation in a certain bank and simultaneously executing a row-related operation in another bank. For this reason, it is necessary to simultaneously issue a column address and data for a column-related operation and a row address for a row-related operation. The operation of such a row / column simultaneous access function is as follows, taking a write page operation as an example.
[0071]
4A and 4B are timing charts showing the operation of the row / column simultaneous access function. As in the first embodiment, BANK # 0 and BANK # 1 in FIG. 4A indicate two banks included in the semiconductor memory device. / ACTIVE, / PRECHAGE, / WRITE, and / LOAD indicate commands output from the command generation circuit 18 based on the command CM input to the input terminal IN2. / Represents a bar and represents an inverted signal. The row bank selection signal is supplied by some bits of the row address input to the input terminal IN1. The column bank selection signal is supplied by a column address and a part of data bits input to the input terminal IN1. The row address, column address, and data in FIG. 4A indicate signals input to the input terminal IN1.
[0072]
The row address in FIG. 4B indicates a signal that is latched by the latch circuit 21 and further selected by the multiplexer 22 and output. / COLUMN WITH ROW indicates a command output from the command generation circuit 18 based on a command input to the input terminal IN2.
[0073]
The description of the part that operates in the same manner as the operation in the first embodiment is omitted, and only the operation of the different part is described below. From the timing charts shown in FIGS. 4A and 4B, there are two cycles T9 and T15 in which row-related operations and column-related operations are simultaneously executed in different banks. In cycle T9, a write (Wt) operation is performed at BANK # 0 and an activation (Act) operation is performed at BANK # 1. At this time, the row (row) address is selected by RBa, the column (column) address is selected by CAe, and the write data is Ae. In cycle T15, activation (Act) operation is performed at BANK # 0, and write (Wt) operation is performed at BANK # 1. At this time, the row (row) side address is selected by RAb, the column (column) side address is selected by CBc, and the write data is Bc.
[0074]
As shown in FIG. 4A, the / LOAD signal is generated from the command generation circuit 18 in cycle T4, and the row address RBa is latched in the latch circuit 21. Then, in cycle T9, the command generation circuit 18 generates a / COLUMN WITH ROW signal for simultaneously issuing a row address / column address and data. As a result, the column address CAe and the data Ae input to the input terminal IN1 are issued, and at the same time, the row address RBa latched in advance by the latch circuit 21 is issued.
[0075]
Further, the / LOAD signal is generated from the command generation circuit 18 at cycle T12, and the row address RAb is latched in the latch circuit 21. Then, in cycle T15, the command generation circuit 18 generates a / COLUMN WITH ROW signal for simultaneously issuing a row address / column address and data. As a result, the column address CBc and the data Bc input to the input terminal IN1 are issued, and at the same time, the row address RAb latched in advance by the latch circuit 21 is issued.
[0076]
With the above-described operation, even in a semiconductor memory device having a few pins as shown in FIG. 3 and having a configuration for latching a row address, a row / column for simultaneously issuing a row address / column address and data. The simultaneous access function can be operated.
[0077]
As described above, according to the second embodiment, a necessary row address is latched in advance in the previous operation cycle, and the row address latched simultaneously with the column address and data input in the current operation cycle. , The row / column simultaneous access function can be realized with a small number of pins as in the case of address multiplexing.
[0078]
[Third Embodiment]
Next explained is a semiconductor memory device according to the third embodiment of the invention.
[0079]
FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to the third embodiment of the present invention. The semiconductor memory device according to the third embodiment is configured to test the operation of the row / column simultaneous access function.
[0080]
The semiconductor memory device includes a memory cell array 11 in which memory cells MC are arranged in a matrix of rows and columns, a row decoding circuit 12 that selects a word line WL from an input row address, and a bit from an input column address. A column decode circuit 13 for selecting a line BL; a multiplexer 31 for receiving a row test address (test path) and a normal row address (normal path 31a) inputted to the input terminal IN1, and selecting and outputting one of them; The selector 14 receives the row address output from the multiplexer 31 and selects whether or not to output the row address to the row decoding circuit 12.
[0081]
The semiconductor memory device further latches the column test address and test data input to the input terminal IN1, and outputs the column test address and test data input to the input terminal IN1 from the latch circuit 15. Receiving a column test address and test data, selecting and outputting one of them, and receiving a column test address (test path) and a normal column address (normal path 32a) output from the multiplexer 16 A multiplexer 32 that selects and outputs one of them, and a multiplexer 33 that receives the test data (test path) and normal data (normal path 33a) output from the multiplexer 16 and selects and outputs either of them. , The multiple And a column address received from the service 32 whether to output to the row decoder 13, and a selector 17 for selecting whether to output the data received from the multiplexer 33 to the data lines DL.
[0082]
Further, the semiconductor memory device receives a command input to the input terminal IN2, and generates a command generation circuit 18 that generates various commands, and a simultaneous issue command that is issued when simultaneously starting a row-related operation and a column-related operation. An AND circuit 19 that performs an AND operation with a row command and an AND circuit 20 that performs an AND operation with the simultaneous issue command and the column command are included.
[0083]
The memory cell array 11 is configured by arranging regular memory cells MC having a predetermined capacity in a matrix of rows and columns at the intersections of the word lines WL and the bit lines BL. The memory cell array 11 is assigned a two-dimensional address space represented by an Nra bit row address and an Nca bit column address. The number of bits of the row address and the column address is determined according to the storage capacity of the memory cell array 11. An Nra bit row test address, or an Nca bit column test address and Nd bit test data are input to the input terminal IN1. The input terminal IN1 has a number of pins that can transmit the larger number of bits (Nmx) of Nra bits or Nca + Nd bits.
[0084]
The multiplexer 31 having the first terminal and the second terminal responds to the test mode control signal / TM (TM bar) and receives the row test address input to the first terminal and the second terminal. One of the outputs (row address) of the normal path 31 a is selected and output to the selector 14. In response to the control signal CL 1 from the AND circuit 19, the selector 14 selects whether to output the row test address or the row address output from the multiplexer 31 to the row decode circuit 12. The row decode circuit 12 is for decoding a row test address or a row address and selecting a row of the memory cell array 11, and selects a word line WL based on the row test address or the row address.
[0085]
An Ncm bit command is input to the input terminal IN2. The command generation circuit 18 decodes an Ncm-bit coded command, causes the latch circuit 15 to latch a column test address and test data, and / LOAD signal to execute row / column simultaneous access. A ROW WITH COLUMN signal, an / ACTIVE signal (row command) for activating the word line WL, and a signal (column command) for executing a read or write operation are generated. Here, the write operation is taken as an example, and only the / WRITE signal is described. The latch circuit 15 sets whether or not to latch the input column test address and test data in response to / LOAD.
[0086]
In response to / ROW WITH COLUMN, the multiplexer 16 having the first terminal and the second terminal receives the column test address and test data input to the first terminal and the output of the latch circuit 15 input to the second terminal ( Column test address or test data) is selected and output to the multiplexer 32 and the multiplexer 33. In other words, the multiplexer 16 processes the column test address and test data input from the outside as normal operations (operations not simultaneously issued) and simultaneously issues the column test address and test data latched in advance by the latch circuit 15. The output is switched between when processing as an operation.
[0087]
The multiplexer 32 having the first terminal and the second terminal is input to the column test address input to the first terminal and the second terminal in response to the control signal / TM (TM bar) for the test mode. One of the outputs (column address) of the normal path 32 a is selected and output to the selector 17. A multiplexer 33 having a first terminal and a second terminal is responsive to a test mode control signal / TM (TM bar) and receives test data input to the first terminal and normal input to the second terminal. One of the outputs (data) of the path 33 a is selected and output to the selector 17.
[0088]
In response to the control signal CL2 from the AND circuit 20, the selector 17 selects whether to output the signals output from the multiplexer 32 and the multiplexer 33 to the column decode circuit 13 and the data line DL, respectively. The column decode circuit 13 decodes a column test address or a column address and selects a column of the memory cell array 11, and selects a bit line BL based on the column test address or the column address.
[0089]
The AND circuit 19 performs an AND operation on / ROW WITH COLUMN and / ACTIVE output from the command generation circuit 18, and outputs a control signal CL1 based on the operation result. The AND circuit 20 performs a logical AND operation on / ROW WITH COLUMN and / WRITE output from the command generation circuit 18, and outputs a control signal CL2 based on the operation result.
[0090]
Next, an operation example of the row / column simultaneous access function of the semiconductor memory device according to the third embodiment will be described.
[0091]
Similar to the first embodiment, the row / column simultaneous access function at the time of bank interleaving is a function for executing a column-related operation in a certain bank and simultaneously executing a row-related operation in another bank. For this reason, it is necessary to simultaneously issue a column address and data for a column-related operation and a row address for a row-related operation. The operation of such a row / column simultaneous access function is as follows, taking a write page operation as an example.
[0092]
FIGS. 6A and 6B are timing charts showing the operation of the row / column simultaneous access function. As in the first embodiment, BANK # 0 and BANK # 1 in FIG. 6A indicate two banks included in the semiconductor memory device. / TM, / ACTIVE, / PRECHAGE, / WRITE, and / LOAD indicate commands output from the command generation circuit 18 based on the command CM input to the input terminal IN2. / Represents a bar and represents an inverted signal. The row bank selection signal is supplied by some bits of the row address input to the input terminal IN1. The column bank selection signal is supplied by a column address and a part of data bits input to the input terminal IN1. A row test address, a column test address, and test data in FIG. 6A indicate signals input to the input terminal IN1.
[0093]
The column test address in FIG. 6B is a signal latched by the latch circuit 15 and further selected by the multiplexer 16 and output. / ROW WITH COLUMN indicates a command output from the command generation circuit 18 based on a command input to the input terminal IN2.
[0094]
From the timing charts shown in FIGS. 6A and 6B, there are two cycles T9 and T15 in which row-related operations and column-related operations are simultaneously executed in different banks. In cycle T9, a write (Wt) operation is performed at BANK # 0 and an activation (Act) operation is performed at BANK # 1. At this time, the row (row) address is selected by RBa, the column (column) address is selected by CAe, and the write data is Ae. In cycle T15, activation (Act) operation is performed at BANK # 0, and write (Wt) operation is performed at BANK # 1. At this time, the row (row) side address is selected by RAb, the column (column) side address is selected by CBc, and the write data is Bc.
[0095]
The description of the part that operates in the same manner as the operation in the first embodiment is omitted, and only the operation of the different part is described below.
[0096]
As shown in FIG. 6A, the test mode control signal / TM becomes “L” in cycle T1, and the operation enters the test mode state. In cycle T4, the / LOAD signal is generated from the command generation circuit 18, and the column test address CAe and the test data Ae are latched in the latch circuit 15. Then, in cycle T9, the command generation circuit 18 generates a / ROW WITH COLUMN signal for simultaneously issuing a row test address / column test address and test data. As a result, the row test address RBa input to the input terminal IN1 is issued, and at the same time, the column test address CAe and test data Ae latched in advance in the latch circuit 15 are issued as shown in FIG. 6B.
[0097]
Further, the / LOAD signal is generated from the command generation circuit 18 in cycle T12, and the column test address CBc and the test data Bc are latched in the latch circuit 15. Then, in cycle T15, the command generation circuit 18 generates a / ROW WITH COLUMN signal for simultaneously issuing a row test address / column test address and test data. As a result, the row test address RAb input to the input terminal IN1 is issued, and at the same time, the column test address CBc and the test data Bc latched in advance in the latch circuit 15 are issued as shown in FIG. 6B.
[0098]
With the configuration as described above, the operation of the row / column simultaneous access function for simultaneously issuing a row address / column address and data can be realized even in a memory-embedded logic LSI that requires a reduction in the number of test pins.
[0099]
As described above, according to the third embodiment, necessary column addresses and data are latched in advance in the previous operation cycle, and the column address latched at the same time as the row address input in the current operation cycle. By issuing data and data, the operation of the row / column simultaneous access function can be realized with a small number of pins as in the case of address multiplexing.
[0100]
[Fourth Embodiment]
Next explained is a semiconductor memory device according to the fourth embodiment of the invention.
[0101]
FIG. 7 is a circuit diagram showing a configuration of a semiconductor memory device according to the fourth embodiment of the present invention. The semiconductor memory device according to the fourth embodiment is configured to test the operation of the row / column simultaneous access function as in the third embodiment.
[0102]
The semiconductor memory device includes a memory cell array 11 in which memory cells MC are arranged in a matrix of rows and columns, a row decoding circuit 12 that selects a word line WL from an input row address, and a bit from an input column address. A column decode circuit 13 for selecting a line BL, a latch circuit 21 for latching a row test address inputted to the input terminal IN1, a row test address inputted to the input terminal IN1, and a row test outputted from the latch circuit 21 A multiplexer 22 that receives an address and selects and outputs one of them, and a row test address (test path) and a normal row address (normal path 31a) output from the multiplexer 22 are selected and selected. And output multiplexer 31, and the multiplexer 31 Receive et output row address, and a selector 14 for selecting whether to output the row address to the row decoder circuit 12.
[0103]
Further, the semiconductor memory device receives a column test address (test path) and a normal column address (normal path 32a) inputted to the input terminal IN1, selects one of them and outputs it, and an input terminal. A multiplexer 33 that receives the test data (test path) and normal data (normal path 33a) input to IN1 and selects and outputs either of them, and the column address received from the multiplexer 32 are supplied to the column decode circuit 13. And a selector 17 for selecting whether to output the data received from the multiplexer 33 to the data line DL.
[0104]
Further, the semiconductor memory device receives a command input to the input terminal IN2, and generates a command generation circuit 18 that generates various commands, and a simultaneous issue command that is issued when simultaneously starting a row-related operation and a column-related operation. An AND circuit 19 that performs an AND operation with a row command and an AND circuit 20 that performs an AND operation with the simultaneous issue command and the column command are included.
[0105]
The memory cell array 11 is configured by arranging regular memory cells MC having a predetermined capacity in a matrix of rows and columns at the intersections of the word lines WL and the bit lines BL. The memory cell array 11 is assigned a two-dimensional address space represented by an Nra bit row address and an Nca bit column address. The number of bits of the row address and the column address is determined according to the storage capacity of the memory cell array 11. An Nra bit row test address, or an Nca bit column test address and Nd bit test data are input to the input terminal IN1. The input terminal IN1 has a number of pins capable of transmitting the larger number of bits (Nmx) of Nra bits or Nca + Nd bits.
[0106]
The multiplexer 32 having the first terminal and the second terminal is input to the column test address input to the first terminal and the second terminal in response to the control signal / TM (TM bar) for the test mode. One of the outputs (column address) of the normal path 32 a is selected and output to the selector 17. A multiplexer 33 having a first terminal and a second terminal is responsive to a test mode control signal / TM (TM bar) and receives test data input to the first terminal and normal input to the second terminal. One of the outputs (data) of the path 33 a is selected and output to the selector 17.
[0107]
In response to the control signal CL2 from the AND circuit 20, the selector 17 selects whether to output the signals output from the multiplexer 32 and the multiplexer 33 to the column decode circuit 13 and the data line DL, respectively. The column decode circuit 13 decodes a column test address or a column address and selects a column of the memory cell array 11, and selects a bit line BL based on the column test address or the column address.
[0108]
An Ncm bit command is input to the input terminal IN2. The command generation circuit 18 decodes an Ncm-bit coded command, and / LOAD signal for causing the latch circuit 21 to latch the row test address, and / COLUMN WITH ROW for executing row / column simultaneous access. A signal, an / ACTIVE signal (row command) for activating the word line WL, and a signal (column command) for executing a read or write operation are generated. Here, the write operation is taken as an example, and only the / WRITE signal is described. The latch circuit 21 sets whether or not to latch the input row test address in response to / LOAD.
[0109]
In response to / COLUMN WITH ROW, the multiplexer 22 having the first terminal and the second terminal receives the row test address input to the first terminal and the output (row test) of the latch circuit 21 input to the second terminal. Address) is selected and output to the multiplexer 31. In other words, the multiplexer 22 processes the row test address input from the outside as a normal operation (operation that does not issue simultaneously) and the case that processes the row test address latched in advance by the latch circuit 21 as an operation that issues simultaneously. Then, the output is switched.
[0110]
A multiplexer 31 having a first terminal and a second terminal is responsive to a test mode control signal / TM (TM bar) to receive a row test address inputted to the first terminal and a normal inputted to the second terminal. One of the outputs (row addresses) of the path 31a is selected and output to the selector 14. In response to the control signal CL 1 from the AND circuit 19, the selector 14 selects whether to output the row test address or the row address output from the multiplexer 31 to the row decode circuit 12. The row decode circuit 12 is for decoding a row test address or a row address and selecting a row of the memory cell array 11, and selects a word line WL based on the row test address or the row address.
[0111]
The AND circuit 19 performs a logical AND operation on / COLUMN WITH ROW and / ACTIVE output from the command generation circuit 18, and outputs a control signal CL1 based on the operation result. The AND circuit 20 performs a logical AND operation on / COLUMN WITH ROW and / WRITE output from the command generation circuit 18, and outputs a control signal CL2 based on the operation result.
[0112]
Next, an operation example of the row / column simultaneous access function of the semiconductor memory device according to the fourth embodiment will be described.
[0113]
Similar to the second embodiment, the row / column simultaneous access function at the time of bank interleaving is a function for executing a column-related operation in a certain bank and simultaneously executing a row-related operation in another bank. For this reason, it is necessary to simultaneously issue a column address and data for a column-related operation and a row address for a row-related operation. The operation of such a row / column simultaneous access function is as follows, taking a write page operation as an example.
[0114]
FIGS. 8A and 8B are timing charts showing the operation of the row / column simultaneous access function. As in the second embodiment, BANK # 0 and BANK # 1 in FIG. 8A indicate two banks included in the semiconductor memory device. / TM, / ACTIVE, / PRECHAGE, / WRITE, and / LOAD indicate commands output from the command generation circuit 18 based on the command CM input to the input terminal IN2. / Represents a bar and represents an inverted signal. The row bank selection signal is supplied by some bits of the row address input to the input terminal IN1. The column bank selection signal is supplied by a column address and a part of data bits input to the input terminal IN1. The row test address, column test address, and test data in FIG. 8A indicate signals input to the input terminal IN1.
[0115]
The row test address in FIG. 8B indicates a signal that is latched by the latch circuit 21 and further selected by the multiplexer 22 and output. / COLUMN WITH ROW indicates a command output from the command generation circuit 18 based on a command input to the input terminal IN2.
[0116]
From the timing charts shown in FIGS. 8A and 8B, there are two cycles T9 and T15 in which row-related operations and column-related operations are simultaneously executed in different banks. In cycle T9, a write (Wt) operation is performed at BANK # 0 and an activation (Act) operation is performed at BANK # 1. At this time, the row (row) address is selected by RBa, the column (column) address is selected by CAe, and the write data is Ae. In cycle T15, activation (Act) operation is performed at BANK # 0, and write (Wt) operation is performed at BANK # 1. At this time, the row (row) side address is selected by RAb, the column (column) side address is selected by CBc, and the write data is Bc.
[0117]
The description of the part that operates in the same manner as the operation in the second embodiment is omitted, and only the operation of the different part is described below.
[0118]
As shown in FIG. 8A, in the cycle T1, the test mode control signal / TM becomes "L", and the operation enters the test mode state. In cycle T 4, the / LOAD signal “L” is generated from the command generation circuit 18, and the row test address RBa is latched in the latch circuit 21. In cycle T9, the command generation circuit 18 generates a / COLUMN WITH ROW signal for simultaneously issuing a row test address / column test address and test data. As a result, the column test address CAe and the test data Ae input to the input terminal IN1 are issued, and at the same time, the row test address RBa previously latched in the latch circuit 21 is issued as shown in FIG. 8B.
[0119]
Further, the / LOAD signal is generated from the command generation circuit 18 in cycle T12, and the row test address RAb is latched in the latch circuit 21. Then, in cycle T15, the command generation circuit 18 generates a / COLUMN WITH ROW signal for simultaneously issuing a row test address / column test address and test data. As a result, the column test address CBc and the test data Bc input to the input terminal IN1 are issued, and at the same time, the row test address RAb latched in advance in the latch circuit 21 is issued as shown in FIG. 8B.
[0120]
With the configuration as described above, the operation of the row / column simultaneous access function for simultaneously issuing a row address / column address and data can be realized even in a memory-embedded logic LSI that requires a reduction in the number of test pins.
[0121]
As described above, according to the fourth embodiment, necessary row addresses are latched in advance in the previous operation cycle, and the row address latched simultaneously with the column address and data input in the current operation cycle. , The row / column simultaneous access function can be realized with a small number of pins as in the case of address multiplexing.
[0122]
【The invention's effect】
As described above, according to the present invention, a necessary address or data is latched in advance in the previous operation cycle, and the latched address or data is issued simultaneously with the address or data used in the current operation cycle. As in the case of address multiplexing, it is possible to provide a semiconductor memory device and a memory-embedded logic LSI capable of realizing the row / column simultaneous access function operation with a small number of pins.
[Brief description of the drawings]
1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a timing chart showing an operation of a row / column simultaneous access function in the semiconductor memory device.
FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 4 is a timing chart showing an operation of a row / column simultaneous access function in the semiconductor memory device.
FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.
FIG. 6 is a timing chart showing the operation of the row / column simultaneous access function in the semiconductor memory device.
FIG. 7 is a circuit diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.
FIG. 8 is a timing chart showing an operation of a row / column simultaneous access function in the semiconductor memory device.
FIG. 9 is a block diagram showing a first configuration example of a conventional semiconductor memory device.
FIG. 10 is a block diagram showing a second configuration example of a conventional semiconductor memory device.
[Explanation of symbols]
11 ... Memory cell array
12 ... Row decode circuit
13 ... Column decode circuit
14 ... Selector
15 ... Latch circuit
16 ... Multiplexer
17 ... Selector
18 ... Command generation circuit
19 ... AND circuit
20 ... AND circuit
21 ... Latch circuit
22: Multiplexer
31 ... Multiplexer
31a ... Normal pass
32 ... Multiplexer
32a ... Normal pass
33 ... Multiplexer
33a ... Normal pass
BL ... Bit line
DL ... Data line
IN1 ... Input terminal
IN2 ... Input terminal
MC: Memory cell
WL ... Word line

Claims (10)

A memory cell array having a first bank and a second bank in which memory cells are arranged in a matrix;
From the outside, a row address signal is input, or an external terminal to which a column address signal and data whose number of bits is smaller than the number of bits of the row address signal is input,
A data line for writing the data input together with the column address signal to the memory cell;
A control circuit for generating a plurality of control signals based on a command input from the outside;
A first selector for selecting whether to output the row address signal input to the external terminal in response to a first control signal generated by the control circuit;
A row decoding circuit for decoding the row address signal output from the first selector and selecting one of the first bank and the second bank ;
A latch circuit for storing the column address signal and data input to the external terminal in response to a second control signal generated by the control circuit;
First, a second input terminal, said column address signal and a data input the column address signals and data inputted from the external terminal to the first input terminal or from the latch circuit, the second input terminal A first multiplexer that selects and outputs one of these in response to a third control signal generated by the control circuit;
In response to a fourth control signal generated by the control circuit, the column address signal output from the first multiplexer is output from the first multiplexer to the column decode circuit and together with the column address signal. A second selector for selecting whether to output the data to the data line ;
A column decode circuit for decoding the column address signal output from the second selector to select one of the first bank and the second bank ;
When a command for simultaneously inputting the row address signal, the column address signal, and data to the row decode circuit, the column decode circuit, and a data line is input to the control circuit, the control circuit includes the first Outputs the third control signal for selecting and outputting the column address signal and data stored in the latch circuit to the multiplexer of, and setting the first selector and the second selector to the output state Outputting the first control signal and the fourth control signal ,
Performing a row-related operation on a row selected by the row decode circuit in the first bank and simultaneously executing a column-related operation on a column selected by the column decode circuit in the second bank. A semiconductor memory device. A memory cell array having a first bank and a second bank in which memory cells are arranged in a matrix;
From the outside, a row address signal is input, or an external terminal to which a column address signal and data whose number of bits is smaller than the number of bits of the row address signal is input,
A row decoding circuit for decoding the row address signal to select one of the first bank and the second bank ;
A column decode circuit for decoding the column address signal to select one of the first bank and the second bank ;
A data line for writing the data input together with the column address signal to a memory cell at the intersection of a row and a column selected by the row decoding circuit and the column decoding circuit;
A first selector which is provided between the external terminal and the row decode circuit and selects whether or not to output the row address signal to the row decode circuit;
Provided between the external terminal and the column decode circuit, and selects whether to output the column address signal to the column decode circuit and the data input together with the column address signal to the data line. A second selector;
A latch circuit provided between the external terminal and the second selector and storing the column address signal and data input to the external terminal;
A multiplexer for said column address signal and the data input to the external terminal, or selects one of the stored said column address signal and data to the latch circuit, and outputs to the second selector,
When the command for simultaneously inputting the row address signal to the row decode circuit and the column address signal and data to the column decode circuit and the data line is input from the outside, the first selector is set to an output state. And a control circuit for causing the multiplexer to select and output the column address signal and data stored in the latch circuit, and to set the second selector to an output state ,
Performing a row-related operation on a row selected by the row decode circuit in the first bank and simultaneously executing a column-related operation on a column selected by the column decode circuit in the second bank. A semiconductor memory device. A memory cell array having a first bank and a second bank in which memory cells are arranged in a matrix;
From the outside, a row address signal is input, or an external terminal to which a column address signal and data whose number of bits is smaller than the number of bits of the row address signal is input,
A row decoding circuit for decoding the row address signal to select one of the first bank and the second bank ;
A column decode circuit for decoding the column address signal and selecting one of the first bank and the second bank;
A data line for writing the data input together with the column address signal to a memory cell at the intersection of a row and a column selected by the row decoding circuit and the column decoding circuit;
A first selector which is provided between the external terminal and the row decode circuit and selects whether or not to output the row address signal to the row decode circuit;
Provided between the external terminal and the column decode circuit, and selects whether to output the column address signal to the column decode circuit and the data input together with the column address signal to the data line. A second selector;
A latch circuit that is provided between the external terminal and the first selector and stores the row address signal input to the external terminal;
A multiplexer for said row address signal is inputted to the external terminal, or selects one of the row address signal stored in the latch circuit, and outputs to the first selector,
When a command for simultaneously inputting the row address signal to the row decode circuit and the column address signal and data to the column decode circuit and the data line is input from the outside, the command is stored in the latch circuit in the multiplexer. A control circuit for selecting and outputting the row address signal and setting the first selector to the output state and setting the second selector to the output state ,
Performing a row-related operation on a row selected by the row decode circuit in the first bank and simultaneously executing a column-related operation on a column selected by the column decode circuit in the second bank. A semiconductor memory device. The control circuit includes:
The command received from the outside, and based on the command, a simultaneous issue command for simultaneously executing the row-related operation and the column-related operation, a row-related command for executing the row-related operation, and the column-related operation A command generation circuit for generating a column-related command for executing
A first AND circuit that performs an AND operation on the simultaneous issue command and the row-related command, and outputs a signal indicating whether or not to set the first selector to an output state in accordance with an operation result of the AND operation; ,
A second AND circuit that performs a logical product with the simultaneous issue command and the column command, and outputs a signal indicating whether or not to set the second selector to an output state in accordance with an operation result of the logical product; The semiconductor memory device according to claim 2, further comprising: The row address signal, the column address signal, and the data that are input to the external terminal are a row test address signal, a column test address signal, and test data that are used during a test operation, respectively, and the command that is input from the outside Is the test command used during the test operation,
A second multiplexer having first and second input terminals between the external terminal and the first selector, and a third and fourth input terminal between the first multiplexer and the second selector. A third multiplexer having
The second multiplexer responds to a control signal indicating that a test operation is in progress, and the row test address signal input to the first input terminal or a normally used row input to the second input terminal. Select one of the address signals and output it to the first selector,
The third multiplexer receives the column test address signal output from the first multiplexer that is input to the third input terminal in response to the control signal, or the column address that is normally used that is input to the fourth input terminal. 3. The semiconductor memory device according to claim 1, wherein any one of the signals is selected and output to the second selector. The row address signal, the column address signal, and the data that are input to the external terminal are a row test address signal, a column test address signal, and test data that are used during a test operation, respectively, and the command that is input from the outside Is the test command used during the test operation,
A second multiplexer having first and second input terminals between the external terminal and the second selector, and a third and fourth input terminal between the first multiplexer and the first selector. A third multiplexer having
The second multiplexer responds to a control signal indicating that a test operation is in progress, and the column test address signal input to the first input terminal or the normally used column input to the second input terminal Select one of the address signals and output it to the second selector,
The third multiplexer receives the row test address signal output from the first multiplexer that is input to a third input terminal in response to the control signal, or a normally used row address that is input to a fourth input terminal. 4. The semiconductor memory device according to claim 3 , wherein any one of the signals is selected and output to the first selector. A memory cell array having a first bank and a second bank in which memory cells are arranged in a matrix;
From the outside, a row address signal is input, or an external terminal to which a column address signal and data whose number of bits is smaller than the number of bits of the row address signal is input,
A row decoding circuit for decoding the row address signal to select one of the first bank and the second bank ;
A column decode circuit for decoding the column address signal to select one of the first bank and the second bank ;
A data line for writing the data input together with the column address signal to a memory cell at the intersection of a row and a column selected by the row decoding circuit and the column decoding circuit;
A first selector which is provided between the external terminal and the row decode circuit and selects whether or not to output the row address signal to the row decode circuit;
Provided between the external terminal and the column decode circuit, and selects whether to output the column address signal to the column decode circuit and the data input together with the column address signal to the data line. A second selector;
A latch circuit provided between the external terminal and the second selector and storing the column address signal and data input to the external terminal;
A multiplexer for said column address signal and the data input to the external terminal, or selects one of the stored said column address signal and data to the latch circuit, and outputs to the second selector,
When the command for simultaneously inputting the row address signal to the row decode circuit and the column address signal and data to the column decode circuit and the data line is input from the outside, the first selector is set to an output state. And a control circuit for causing the multiplexer to select and output the column address signal and data stored in the latch circuit, and to set the second selector to an output state ,
Performing a row-related operation on a row selected by the row decode circuit in the first bank and simultaneously executing a column-related operation on a column selected by the column decode circuit in the second bank. A memory-embedded logic LSI that is characterized. The row address signal, the column address signal, and the data that are input to the external terminal are a row test address signal, a column test address signal, and test data that are used during a test operation, respectively, and the command that is input from the outside Is the test command used during the test operation,
A second multiplexer having first and second input terminals between the external terminal and the first selector, and a third and fourth input terminal between the first multiplexer and the second selector. A third multiplexer having
The second multiplexer responds to a control signal indicating that a test operation is in progress, and the row test address signal input to the first input terminal or a normally used row input to the second input terminal. Select one of the address signals and output it to the first selector,
The third multiplexer receives the column test address signal output from the first multiplexer that is input to the third input terminal in response to the control signal, or the column address that is normally used that is input to the fourth input terminal. 8. The memory-embedded logic LSI according to claim 7, wherein either one of the signals is selected and output to the second selector.   A memory cell array having a first bank and a second bank in which memory cells are arranged in a matrix;
  From the outside, a row address signal is input, or an external terminal to which a column address signal and data whose number of bits is smaller than the number of bits of the row address signal is input,
  A row decoding circuit for decoding the row address signal to select one of the first bank and the second bank;
  A column decode circuit for decoding the column address signal to select one of the first bank and the second bank;
  A data line for writing the data input together with the column address signal to a memory cell at the intersection of a row and a column selected by the row decoding circuit and the column decoding circuit;
  A first selector which is provided between the external terminal and the row decode circuit and selects whether or not to output the row address signal to the row decode circuit;
  Provided between the external terminal and the column decode circuit, and selects whether to output the column address signal to the column decode circuit and the data input together with the column address signal to the data line. A second selector;
  A latch circuit that is provided between the external terminal and the first selector and stores the row address signal input to the external terminal;
  A multiplexer that selects one of the row address signal input to the external terminal or the row address signal stored in the latch circuit and outputs the selected signal to the first selector;
  When a command for simultaneously inputting the row address signal to the row decode circuit and the column address signal and data to the column decode circuit and a data line is input from the outside, the command is stored in the latch circuit in the multiplexer. And a control circuit for selecting and outputting the row address signal and setting the first selector to an output state and setting the second selector to an output state,
  Performing a row-related operation on a row selected by the row decode circuit in the first bank, and simultaneously performing a column-related operation on a column selected by the column decode circuit in the second bank. A memory-embedded logic LSI that is characterized.   The row address signal, the column address signal, and the data that are input to the external terminal are a row test address signal, a column test address signal, and test data that are used during a test operation, respectively, and the command that is input from the outside Is a test command used during test operation,
  A second multiplexer having first and second input terminals between the external terminal and the second selector, and a third and fourth input terminal between the first multiplexer and the first selector. A third multiplexer having
  The second multiplexer responds to a control signal indicating that a test operation is in progress, and the column test address signal input to the first input terminal or the normally used column input to the second input terminal Select one of the address signals and output it to the second selector,
  The third multiplexer receives the row test address signal output from the first multiplexer that is input to a third input terminal in response to the control signal, or a normally used row address that is input to a fourth input terminal. 10. The memory-embedded logic LSI according to claim 9, wherein either one of the signals is selected and output to the first selector.

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