KR100903694B1 - Semiconductor device and data writing method - Google Patents

Abstract

Provided is a semiconductor device capable of simultaneously writing many bits without increasing the chip size. The semiconductor device includes a write data bus for writing data to a memory cell, a read data bus for reading data from the memory cell, and a first data for writing data to the memory cell using the read data bus during high-speed writing. A write amplifier, a second write amplifier that writes data to the memory cell using the write data bus at high-speed writing, and a first sense amplifier to read verified data from the memory cell using the read data bus. And a second sense amplifier that reads the verified data from the memory cell using a write data bus.

Flash, read, write, high speed, bus

Description

Semiconductor Device and Data Writing Method {SEMICONDUCTOR DEVICE AND DATA WRITING METHOD}

The present invention relates to a semiconductor device and a data writing method.

Although flash memory is widely used as a nonvolatile semiconductor device capable of electrically rewriting data, the data rewrite time of the flash memory is very long compared to other semiconductor storage devices such as DRAM and SRAM, and controls the flash memory. The controller cannot access the flash memory during data rewrite execution.

In recent years, in order to solve such a disadvantage, a dual operation type flash memory has been developed that can divide the inside of the flash memory into a plurality of banks and read data from another bank while rewriting data in one bank. . In this case, the bank refers to a memory bank that is composed of one block or a group consisting of two or more blocks arbitrarily combined and capable of simultaneously acting on data processing.

Next, a description will be given of a conventional dual operation type flash memory. 1 is a block diagram of a conventional dual operation type flash memory. As shown in FIG. 1, the flash memory 1 includes a cell array 2, a read sense amplifier 3, a write sense amplifier 4, and a write amplifier 5. do. The cell array 2 includes a plurality of banks BANK0 to BANKn. Memory cells in each bank BANK0 to BANKn are managed in sector units. The Y gate 21 is connected to the read data buses RDB0 to RDBm and the write data buses WDB0 to WDBm through the bit lines BL.

The read sense amplifier 3 reads data from the memory cell using the read data buses RDB0 to RDBm. The write sense amplifier 4 reads verification data from the memory cell using the write data buses WDB0 to WDBm. The write amplifier 5 writes data to the memory cells using the write data buses WDB0 to WDBm. In such a dual operation type flash memory, data in another bank can be read while rewriting data in one bank.

In addition, Patent Document 1 proposes such a dual operation type flash memory.

Patent Document 1: US Patent No. 6240040

However, in such dual operation type flash memory 1, when an internal power supply is used when writing to a memory cell, the bit is written at a time due to the limitation of the current capability of the high voltage generation circuit mounted on the chip. Because of the limited number, writing at high speed is not possible. On the other hand, when performing high-speed writing using an external power supply, there is no limit to the number of bits to be written at one time. Therefore, high-speed writing can be achieved by writing many bits at the same time. Writing at the same time requires the write data bus for the number of bits, and there is a problem that the chip size increases if the write data bus is increased.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device and a semiconductor write method capable of simultaneously writing many bits without increasing the chip size.

In order to solve the above problems, the present invention provides a data bus for writing data to a memory cell, a read data bus for reading data from the memory cell, and the read data bus at a predetermined write time. It is a semiconductor device including a first write amplifier for writing data into a card. According to the present invention, in the case of having a large number of read data buses such as a burst mode structure or a page mode structure, for example, at the time of high-speed writing, these read data buses are used as write data buses. The bits can be written at the same time and can be written at high speed. In addition, since data is written using an unused data bus during high-speed writing, the chip size does not increase because there is no need to separately install a data bus for writing.

The semiconductor device also includes a second write amplifier that writes data into the memory cell using the write data bus at a predetermined write time. According to the present invention, by using the write data bus and the read data bus for writing data, more bits can be written to the memory cell at the same time, and the data can be written at high speed.

The semiconductor device also includes a shield wiring for shielding the read data bus, and a third write amplifier for writing data into the memory cell using the shield wiring at a predetermined writing time. According to the present invention, since the shield wiring of each read data bus is used as the write data bus at the time of high-speed writing, more bits can be written simultaneously into the memory cell, and writing can be performed at high speed.

The present invention is a semiconductor device including a shield wiring for shielding a read data bus for reading data from a memory cell, and a third write amplifier for writing data into the memory cell using the shield wiring at a predetermined writing time. . According to the present invention, when the shield wiring of the read data bus is used as the write data bus at the time of high-speed writing, many bits can be written simultaneously into the memory cell, and data can be written at high speed. The semiconductor device of the present invention also includes a write data bus for writing data to the memory cells.

The semiconductor device also includes a first sense amplifier that reads verification data from the memory cell using the read data bus. According to the present invention, by using the read data bus for reading verification data, data can be read out from the memory cell at high speed.

The semiconductor device also includes a second sense amplifier that reads verification data from the memory cell using the write data bus. According to the present invention, by using the write data bus and the read data bus for reading verification data, data can be read from the memory cell at high speed.

The semiconductor device also includes a third sense amplifier that reads verification data from the memory cell using the shield wiring. According to the present invention, the shield wiring is used to read verification data, so that data can be read from the memory cell at high speed.

The semiconductor device also includes a sense amplifier that reads data from the memory cell using the read data bus. According to the present invention, data can be read from a memory cell using a read data bus.

The semiconductor device also includes a cell array including a plurality of banks capable of reading data from memory cells of the second bank while writing data into the memory cells of the first bank. According to the present invention, high-speed reading of data suitable for dual operation operation is enabled.

The semiconductor device further includes a cell array including a plurality of banks capable of reading data from the memory cells of the second bank while writing data into the memory cells of the first bank, and provided for each of the banks, and the read data. And a sense amplifier that reads data from the memory cell using a bus. According to the present invention, even when a sense amplifier for writing is provided for each bank, data can be written to the memory cell at high speed by using the shield wiring.

The semiconductor device also includes a cell array including a plurality of banks capable of reading data from memory cells of a second bank while writing data into memory cells of a first bank, wherein the read data bus includes: It is installed every time. According to the present invention, even when the read data bus is provided for each bank, data can be written to the memory cell at high speed by using the shield wiring of the read data bus.

The semiconductor device also generates a cell array including a plurality of banks capable of reading data from the memory cells of the second bank while writing data into the memory cells of the first bank, and a selection signal for selecting the banks. And a selection circuit. According to the present invention, a bank for writing data at high speed can be selected.

The semiconductor device also includes switch means for connecting the first write amplifier to the read data bus at a predetermined writing time. According to the present invention, the first write amplifier can be connected to the read data bus so that data can be written to the memory cell at high speed.

The semiconductor device also includes switch means for connecting the third write amplifier to the shield wiring at a predetermined writing time. According to the present invention, data can be written to the memory cell at high speed by connecting the third write amplifier to the shield wiring.

The semiconductor device also includes a cell array including a plurality of banks capable of reading data from memory cells of a second bank while writing data into memory cells of a first bank, and the read data bus of the plurality of banks. Switch means for selecting a bank to be connected to. According to the present invention, memory cells in each bank can be connected to the read data bus.

The semiconductor device further includes a cell array including a plurality of banks capable of reading data from memory cells of a second bank while writing data into memory cells of a first bank, and the plurality of banks at a predetermined write time. And switch means for selecting a bank to be connected to the shield wiring. According to the present invention, the memory cells in each bank can be connected to the shield wiring.

The read data bus is composed of more data buses than the write data bus. According to the present invention, data can be written to a memory cell at high speed by using more read data buses than write data buses in the case of a burst mode structure and a page mode structure. The semiconductor device is a semiconductor memory device.

The present invention provides a method of writing data into a memory cell using a write data bus, reading data from the memory cell using a read data bus, and using the read data bus at a predetermined write time. This is a data writing method that includes writing data into a cell. According to the present invention, for example, when there are many read data buses such as burst mode structures and page mode structures, these read data buses are used as write data buses for high-speed writing, for example, so that many bits can be written simultaneously. It is possible to provide a data writing method of a semiconductor device which can be written at high speed. In addition, by writing data using an unused data bus during high-speed writing, there is no need to provide a data bus for writing separately, so that the chip size does not increase.

The data writing method of the present invention also includes writing data into the memory cell using the write data bus at a predetermined writing time. According to the present invention, by using the write data bus and the read data bus for writing data, more bits can be written at the same time, and the data can be written at high speed.

The data write method of the present invention also includes writing data into the memory cell using shield wiring for shielding the read data bus at a predetermined write time. According to the present invention, since the shield wiring of each read data bus is used as a write data bus at the time of high-speed writing, more bits can be written at the same time and writing at high speed can be performed.

According to the present invention, a data write method includes reading data from a memory cell using a read data bus and writing data to the memory cell using a shield wire for shielding the read data bus at a predetermined write time. It is a way. According to the present invention, since the shield wiring of each read data bus is used as a write data bus at the time of high-speed writing, many bits can be written at the same time and data can be written at high speed.

The data write method also includes reading verification data from the memory cell using the read data bus. According to the present invention, it is possible to read data from a memory cell at high speed by using a read data bus for reading verification data.

The data write method also includes reading verification data from the memory cell using the write data bus. According to the present invention, by using the write data bus and the read data bus for reading verification data, data can be read out from the memory cell at high speed.

The data write method also includes reading verification data from the memory cell using the shield wire. According to the present invention, it is possible to read data from a memory cell at high speed by using a shield wiring for reading verification data.

The data writing method also includes generating a selection signal for selecting a plurality of banks each including the memory cells. According to the present invention, a bank for writing data at high speed can be selected.

The data write method also includes reading data from memory cells of the second bank while writing data to the memory cells of the first bank of the plurality of banks. According to the present invention, a dual operation type semiconductor device can be provided.

Effects of the Invention

According to the present invention, it is possible to provide a semiconductor device and a semiconductor writing method capable of simultaneously writing many bits without increasing the chip size.

1 is a block diagram of a conventional dual operation type flash memory.

2 is a configuration diagram of a semiconductor device according to the first embodiment.

3 is a diagram illustrating a configuration of generating a bank selection signal of the semiconductor device 10 according to the first embodiment.

4 is a diagram showing a bank selection circuit according to the first embodiment.

Fig. 5 is a timing chart at the time of high speed writing of the semiconductor device according to the first embodiment.

6 is a configuration diagram of a semiconductor device according to the second embodiment.

7 is a timing chart at the time of high-speed writing of the semiconductor device according to the second embodiment.

8 is a configuration diagram of a semiconductor device according to the third embodiment.

9 is a timing diagram at the time of high-speed writing of the semiconductor device according to the third embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

Example  One

2 is a configuration diagram of a semiconductor device according to the first embodiment. As shown in FIG. 2, the semiconductor device 10 includes a core cell array 2, a read sense amplifier 3, a write sense amplifier 4, a write amplifier 5, and a write sense amplifier 11. And a write amplifier 12. In addition, the semiconductor device 10 includes write data buses WDB0 to WDBm, read data buses RDB0 to RDBm, and shield wirings VSD. The same parts as in FIG. 1 will be described with the same reference numerals.

The semiconductor device 10 may be a semiconductor memory device such as a flash memory packaged alone, or may be provided as part of a semiconductor device such as a system LSI. This semiconductor device 10 is of a dual operation type that can read data of another part while data is written or written. The semiconductor device 10 can write data to a memory cell at a normal speed during a dual operation operation, and can write data to the memory cell at a high speed by prohibiting the dual operation operation at a high speed writing.

The core cell array 2 includes a plurality of banks BANK0 to BANKn capable of reading data from memory cells of the second bank while writing data to the memory cells of the first bank. The memory cells of each bank BANK0 to BANKn are composed of a plurality of sectors. The Y gate 21 is connected to the read data buses RDB0 to RDBm and the write data buses WDB0 to WDBm through the bit lines BL. The write data buses WDB0 to WDBm are for writing data to memory cells. The read data buses RDB0 to RDBm are for reading data from memory cells. The shield wiring VSD is for shielding the read data buses RDB0 to RDBm.

The read sense amplifier 3 is a current comparison circuit, which reads data from a memory cell using read data buses RDB0 to RDBm, compares the read current of the memory cell with the reference current, and amplifies the current difference. To print. The write sense amplifier 4 reads the verification data from the memory cell using the write data buses WDB0 to WDBm during normal writing and high speed writing. The write amplifier 5 writes data to a memory cell using write data buses WDB0 to WDBm at the time of normal writing and high-speed writing.

The write sense amplifier 11 is a sense amplifier for high speed programming. The write sense amplifier 11 reads verification data from a memory cell using read data buses RDB0 to RDBm at high-speed writing. The write sense amplifier 11 can also perform program verification for 2 words at the same time. In addition, since the read data bus RDBm is connected to the read sense amplifier 3, instead of adding the write sense amplifier 11, the read data bus RDBm is used to read verification data using the read sense amplifier 3; You can do it. The write amplifier 12 writes data to a memory cell using the read data buses RDB0 to RDBm at the high-speed writing.

The NMOS transistors 80 and 81 are switch means for connecting the write sense amplifier 11 and the write amplifier 12 to the read data buses RDB0 to RDBm during high-speed writing.

The bit lines BL of the banks BANK0 to BANKn are connected to the read data buses RDB0 to RDBm through the NMOS transistors 600 to 6n3 to which the bank selection signals RSEL00 to RSEL1n serve as gate inputs. The bit lines BL of the banks BANK0 to BANKn are connected to the write data buses WDB0 to WDBm through the NMOS transistors 700 to 7n3 to which the bank selection signals WSEL00 to WSEL1n are gated. . At this time, m is an I / O number, for example, an integer of 0 to 15.

When the bank BANKn is in the read state, the bank select signal RSEL0n or RSEL1n becomes high level, and the read sense amplifier 3 reads data through the read data buses RDB0 to RDBm. At this time, 16 bits (one word) can be read simultaneously. When the bank BANKn is in the program state or the verify state, the bank select signal WSEL0n or WSELln is at a high level, and the write sense amplifier 4 and the write amplifier 5 are written to the write data buses WDB0 to WDBm. Program or verify via As a result, 16-bit (1 word) writing is performed simultaneously.

Normally, the bank selection signals RSELOn, RSEL1n, WSELOn, and WSEL1n are controlled for each of the banks BANK1 to BANKn, so that read and write can be performed simultaneously. This realizes the dual operation function.

At high-speed writing, the signal FPGM is at a high level, and the write sense amplifier 11 and the write amplifier 12 for high-speed writing are connected to the data buses RDB0 to RDBm through the NMOS transistors 80 and 81. do. The bank BANKn is selected by the bank selection signals RSEL0n and WSEL1n being high, the bank selection signals RSEL1n and WSEL0n being low, and the transistors indicated by dotted lines are turned on and the signal PGM is turned on. At this high time, the number of bits twice as large as normal writing can be simultaneously written, and program verification can be performed when the signal PGMV is high. This realizes simultaneous writing of two words (32 bits).

3 is a diagram showing a configuration of generating a bank selection signal of the semiconductor device 10 according to the first embodiment. As shown in FIG. 3, the semiconductor device 10 includes a control logic 13, an address buffer 14, and a bank selection circuit 15. The control logic 13 receives an external command, generates a signal Read, a signal Write, a signal FPGM, and sends them to the address buffer 14. External commands include commands such as write commands and fast write commands.

The address buffer 14 receives the signals Read and the signal Write signal FPGM from the external address A (i) and the control logic 13, and reads the internal addresses RA (i) and RAB (i) for reading and the bank selection signal for reading ( RBSELn), write internal addresses WA (i) and WAB (i), and write bank select signal WBSELn are generated. At this time, the read internal address RAB (i) is an inverted signal of the write internal address RA (i). The write internal address WAB (i) is an inverted signal of the read internal address WA (i). The bank select circuit 15 generates select signals RSEL0n, RESEL1n, WSEL0n, and WSEL1n for selecting the banks BANK0 to BANKn.

Next, the bank selection circuit 15 will be described. 4 is a diagram illustrating a configuration of the bank select circuit 15 that generates a bank select signal. The bank select circuit 15 includes circuits 151 to 157 and is a circuit that generates bank select signals RSEL0n, RSEL1n, WSEL0n, and WSEL1n. The circuit 151 includes a NAND circuit 511 and an inverter 512 and generates a signal FWBSELn from the signal WBSELn and the signal FPGM. The circuits 152 and 153 are circuits forcibly bringing the bank selection signals RSEL0n and WSEL1n high during the high speed programming of the bank BANKn.

Circuit 152 includes NOR circuit 521 and inverter 522 and generates signal FWA (j) from signal WA (j) and signal FPGM. The circuit 153 includes a NAND circuit 531 and inverters 532 and 533 and generates a signal FWAB (j) from the signal WAB (j) and the signal FPGM. In the circuits 154 to 157, the inverter circuits 154a to 157a are circuits for level shifting an input signal having a VCC level to an output signal having a VPP level. The circuit 154 includes a NAND circuit 541, NMOS transistors 542 and 543, and PMOS transistors 544 and 545, and generates a bank select signal RSEL1n from the signals RBSELn and signal RA (j). .

Circuit 155 includes NAND circuits 551 and 552, NOR circuit 553, NMOS transistors 554 and 555, and PMOS transistors 556 and 557, and signals RBSELn, signals RAB (j), and signals The bank selection signal RSEL0n is generated from (FWBSELn) and the signal FWA (j). The circuit 156 includes a NAND circuit 561, NMOS transistors 562 and 563, and PMOS transistors 564 and 565, and generates a bank select signal WSEL1n from the signal WBSELn and the signal FWA (j). .

The circuit 157 includes a NAND circuit 571, NMOS transistors 572 and 573, and PMOS transistors 574 and 575, and generates a bank select signal WSEL0n from the signal WBSELn and the signal FWAB (j). . Normally, the signal RBSELn from the address buffer 14 goes high when in the bank BANKn read state, and the signal WBSELn goes high when in the write state, and the read addresses RAB (j) and RA (j). Selects the bank selection signals RSEL0n and RSEL1n, and selects the signals WSELOn and WSEL1n with the write addresses WAB (j) and WA (j). At high speed writing, the signal FPGM goes high. In addition, regardless of the signals WA (j) and WAB (j), the internal signal FWA (j) becomes HIGH and FWAB (j) goes low, thereby selecting the bank selection signals RSEL0n and WSEL1n. Is carried out.

Next, the operation at the high speed writing of the semiconductor device according to the first embodiment will be described. Fig. 5 is a timing chart at the time of high speed writing of the semiconductor device according to the first embodiment. In the high-speed write, the user inputs two addresses and two data (a total of 32 bits in 16 bits each) together with the high-speed write command FPGM. At this time, the address input inputs the highest address A (j) for column selection (select transistors 6n0 to 6n3, 7n0 to 7n3) by switching high and low, and the other addresses are the same as A (i). Data are latched in the respective write amplifiers 5 and 12. Then, program verification is started when the signal PGMV becomes high.

In the program verification, as shown in Fig. 4, FWA (j) and FWAB (j) are forced to high and low, respectively, HIGH and LOW, and the selected bank BANKn has the bank selection signals RSEL0n and WSEL1n. It is always high and the bank select signals RSEL1n and WSEL0n are always low. In the program verify period in which the signal PGMV is high, the verify data is supplied to the read data buses RDB0 to RDBm and the write data buses WDB0 to WDBm, and program verification is performed simultaneously for 32 bits (for two words).

Next, in the program period when the signal PGM is high, the program voltage is supplied to the read data buses RDB0 to RDBm and the write data buses WDB0 to WDBm, and 32-bit simultaneous writing is performed. Next, in the program verify period in which the signal PGMV is high, the verify data flows to the read data buses RDB0 to RDBm and the write data buses WDB0 to WDBm, and program verification is performed simultaneously for 32 bits (for two words). If the verification passes, the high-speed writing ends and the signal FPGM goes low. Subsequently, when high-speed writing of other data is performed, the same operation is performed again by inputting the FPGM command.

According to the first embodiment, since a flash memory capable of simultaneously reading and writing has a read data bus and a write data bus, simultaneous execution of read and write is prohibited during high-speed writing, so that the read data bus and the write data bus are prohibited. Using all as write data buses, many bits can be written simultaneously and written at high speed. Since the data bus for writing does not need to be installed separately, the chip size does not increase.

Example 2

Next, Example 2 will be described. 6 is a configuration diagram of a semiconductor device according to the second embodiment. As shown in FIG. 6, the semiconductor device 110 includes a core cell array 2, a read sense amplifier 3, a write sense amplifier 4, a write amplifier 5, and a write sense amplifier 11. And a write amplifier 12. The semiconductor device 110 also includes a control logic 13, an address buffer 14, and a bank selection circuit 15 as in the first embodiment. The semiconductor device 110 is a dual operation type capable of reading out data of another part while data is written or written, and has a burst mode or a page mode.

The write data buses WDB0 to WDBm are for writing data to memory cells. The read data buses RDB0m to RDB1m are for reading data from memory cells. The read data buses RDB0m to RDB1m include more data buses than the write data buses WDB0 to WDBm. In the burst mode or page mode structure, multiple words (in this example, two words) are accessed at the same time for reading. Therefore, the read data bus RDB0m and the read data bus RDB1m are simultaneously connected to the input / output terminal I / Om. Two words of data are read on two buses. The shield wiring VSD is for shielding the read data buses RDB00 to RDB1m.

The core cell array 2 includes a plurality of banks BANK0 to BANKn capable of reading data from memory cells of the second bank while writing data to the memory cells of the first bank. The memory cells of the banks BANK0 to BANKn are composed of a plurality of sectors. The read sense amplifier 3 is a current comparison circuit, which reads data from a memory cell using read data buses RDB0m to RDB1m, compares the read current and the reference current of the memory cell, amplifies the current difference, and outputs the result. do.

The write sense amplifier 4 normally reads verification data from the memory cell using the write data buses WDB0 to WDBm at the time of writing. The write sense amplifier 4 reads verification data from a memory cell by using the read data buses RDB00 to RDB0m during high-speed writing. The write amplifier 5 writes data using the write data buses WDB0 to WDBm during normal writing. The write amplifier 5 reads verification data from the memory cell using the read data buses RDB00 to RDB0m at the high-speed writing.

The write sense amplifier 11 is a sense amplifier for high speed programming. The write sense amplifier 11 reads verification data from a memory cell by using read data buses RDB10 to RDB1m during high-speed writing. The write sense amplifier 11 can also simultaneously perform program verification for two words each. The write amplifier 12 writes data to the memory cells using the read data buses RDB10 to RDB1m at the high-speed writing. When the NMOS transistors 80 to 83 write at high speed, the write sense amplifier 4, the write amplifier 5, the write sense amplifier 11, and the write amplifier 12 are connected to the read data buses RDB00 to RDB1m. It is a switch means to connect.

The bit lines BL of the banks BANK0 to BANKn are connected to the read data buses RDB00 to RDB1m through the NMOS transistors 600 to 6n3 to which the bank selection signals RSEL0 to RSELn serve as gate inputs. The bit lines BL of the banks BANK0 to BANKn are connected to the write data buses WDB0 to WDBm through the NMOS transistors 700 to 7n3 to which the bank selection signals WSEL00 to WSEL1n are gated. . M is an I / O number, for example, becomes an integer of 0-15.

When the banks BANK0 to BANKn are in the read state, the bank select signal RSELn becomes high level, and the read sense amplifier 3 reads word data through the read data buses RDB00 to RDB1m. . When the bank BANKn is in the program or verify state, the bank select signal WSELOn or WSEL1n becomes high level, and the write sense amplifier 4 and the write amplifier 5 have one word through the write data buses WDB0 to WDBm. Perform a program or verification.

Normally, the bank select signals RSELn, WSELOn, and WSEL1n are controlled for each of the banks BANKO to BANKn, so that read and write can be executed simultaneously. Thus, the dual operation function is realized. At high-speed writing, the signal FPGM is at a high level, and the write sense amplifier 4, the write amplifier 5, the write sense amplifier 11, and the write amplifier 12 use the NMOS transistors 80 to 83. It is connected to the read data buses RDB00 to RDB1m through which two words can be simultaneously programmed or verified.

As described above, since the second embodiment has more read data buses RDB00 to RDB1m than the write data buses WDB0 to WDBm, the write data buses RDB00 to RDB1m are simultaneously written to a plurality of bits using only the read data buses RDB00 to RDB1m. Is carried out. In this case, the control of the bank selection signals RSELn, WSELOn, and WSEL1n is simplified.

7 is a timing chart at the time of high-speed writing of the semiconductor device according to the second embodiment. At high-speed writing of the bank BANKn, the signal FPGM and the bank select signal RSELn go high. In the program verify period in which the signal PGMV is high, verify data flows to the read data buses RDB0m and RDB1m, and program verify is performed. Next, in the program period when the signal PGM is high, the program voltage is supplied to the read data buses RDB0m and RDB1m, and 32-bit simultaneous writing is performed.

Next, in the program verification period in which the signal PGMV is high, the verification data flows to the read data buses RDB0m and RDB1m, the program verification is performed, and if the program verification passes, the high-speed writing ends and the signal FPGM It goes low. Subsequently, when high-speed writing of other data is performed again, the FPGM command is input again.

According to the second embodiment, the memory is a memory having a read data bus for a plurality of words, such as a burst mode structure or a page mode structure, and at the time of high-speed writing, these read data buses are used as write data buses. It can write at the same time and can write at high speed.

Example  3

Next, Example 3 will be described. 8 is a configuration diagram of a semiconductor device according to the third embodiment. The third embodiment is an example in which a plurality of read data buses exist for each bank. As shown in FIG. 8, the semiconductor device 210 includes a core cell array 2, a plurality of read sense amplifiers 3a to 3n, a write sense amplifier 4, a write amplifier 5, a write sense The amplifier 11 includes a light amplifier 120. The semiconductor device 210 also includes a control logic 13, an address buffer 14, and a bank select circuit 15, similarly to the first embodiment.

The semiconductor device 2200 is of a dual operation type that can read other portions of data while writing or writing data, and has a page mode and a burst mode. The write data buses WDB0 to WDBm are for writing data to memory cells. The read data buses RDB000 to RDBn1m are for reading data from memory cells. The read data buses RDB000 to RDBn1m are provided for each of the banks BANK0 to BANKn. The shield wiring VSD is for shielding the read data buses RDB000 to RDBn1m.

The core cell array 2 includes a plurality of banks BANK0 to BANKn capable of reading data from memory cells of the second bank while writing data to the memory cells of the first bank. The memory cells of the banks BANK0 to BANKn are composed of a plurality of sectors. Each read sense amplifier 3a to 3n reads data from the memory cell using the read data buses RDB000 to RDBn1m. The read sense amplifiers 3a to 3n are provided for each bank.

The write sense amplifier 4 normally reads verification data from the memory cell using the write data buses WDB0 to WDBm at the time of writing. The write amplifier 5 writes data to a memory cell using the write data buses WDB0 to WDBm at the time of normal writing. The write sense amplifier 11 is a sense amplifier for high speed programming. The write sense amplifiers 4 and 11 read the verification data from the memory cell by using the shield wiring VSD during high-speed writing. The write sense amplifier 11 can also simultaneously perform program verification for two words each. The write amplifiers 5 and 120 write data into the memory cells using the shield wiring VSD at high speed writing.

The NMOS transistors 80 to 83 are switches for connecting the write sense amplifier 4, the write amplifier 5, the write sense amplifier 11, and the write amplifier 120 to the shield wiring VSD during high-speed writing. Means. The NMOS transistors 800 to 8n4 are switch means for connecting the bit line BL to the shield wiring VSD through the read data buses RDB000 to RDBn1m at the high-speed writing.

The bit line BL of the bank BANKn is connected to the read data buses RDBn0n to RDBn1m through the NMOS transistors 6n0 to 6n3 to which the bank selection signal RSELn is a gate input, so that reading of two words is possible. Is carried out. The bit line BL of the bank BANKn is connected to the write data buses WDB0 to WDBm through the NMOS transistors 7n0 and 7n2 or 7n1 and 7n3 to which the bank selection signals WSEL0n to WSEL1n are gate inputs. Then, one word program is implemented. At this time, m is an I / O number, and becomes an integer of 0-15, for example.

Each read data bus RDBO00 to RDBn1m is shielded by a shield wiring VSD in order to alleviate the influence of the adjacent read data bus. Since the shield wiring VSD is bank common, this shield wiring VSD is used as a data bus for high-speed writing. In the normal case, the signal FGPMB is at a high level, and the shield wiring VSD is connected to the ground VSS through the NMOS transistors 90 to 95. At high-speed writing, the signal FGPMB goes low and is separated from ground VSS. The signal FPGM becomes high level, and the write data amplifiers RDBn00 to RDBn0m of the bank BANKn include the write sense amplifier 4 and the write amplifier 5 in the write sense amplifier 4 and the write amplifier 5. The read data buses RDBn10 to RDBn1m of the bank BANKn are connected to 120 to simultaneously perform high-speed writing and verifying every two words.

9 is a timing diagram at the time of high-speed writing of the semiconductor device according to the third embodiment. When the bank BANKn is fast written, the signal FPGM and the bank select signal RSELn go high. In the program verification period in which the signal PGMV is high, verification data flows into the shield wiring VSD, and program verification is performed. Next, in the program period when the signal PGM is high, the program voltage is supplied to the shield wiring VSD, and 32-bit simultaneous writing is performed.

Next, during the program verification period in which the signal PGMV is high, the verification data flows into the shield wiring VSD, and program verification is performed. When the program verification passes, the high-speed writing is terminated, and the signal FPGM goes low. It becomes Subsequently, when the high-speed writing of other data is performed, the FPGM instruction is input again, and the same operation is performed.

According to the third embodiment, when there is a read data bus for each bank, since the shield wiring of each read data bus is used as the write data bus at the high-speed writing, many bits can be written at the same time and the writing can be performed at high speed. have.

In addition, in the first and second embodiments, high speed writing can also be realized by using the shield wiring VSD.

Further, the write amplifier 12, the write amplifier 5, the write amplifier 5 and the write amplifier 120, the write sense amplifier 11, the write sense amplifier 4, the write sense amplifier 4 and The write sense amplifier 11 and the bank selection circuit 15 are the first write amplifier, the second write amplifier, the third write amplifier, the first sense amplifier, the second sense amplifier, and the third sense amplifier in the claims. And a selection circuit respectively. The NMOS transistors 600 to 6n3 are switch means for selecting a bank to be connected to the read data bus among the plurality of banks.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to this specific embodiment, A various deformation | transformation and a change are possible within the scope of the summary of this invention described in a claim.

Claims (28)

A write data bus for writing data to the memory cells; A read data bus for reading data from the memory cells; And And a first write amplifier for writing data to the memory cell using the read data bus at a predetermined write time. The semiconductor device of claim 1, wherein the semiconductor device comprises: And a second write amplifier for writing data to the memory cells using the write data bus at a predetermined write time. The semiconductor device of claim 1, wherein the semiconductor device comprises: Shield wires for shielding the read data bus; And And a second write amplifier writing data into the memory cell using the shield wires at a predetermined writing time. Shield lines for shielding a read data bus that reads data from the memory cells; And And a write amplifier which writes data into the memory cell using the shield wires at a predetermined write time. The semiconductor device of claim 4, wherein the semiconductor device comprises: And a write data bus for writing data to the memory cells. The semiconductor device according to any one of claims 1 to 3, wherein And a sense amplifier using the read data bus to read verified data from the memory cell. The semiconductor device according to any one of claims 1 to 3, wherein And a sense amplifier that reads the verified data from the memory cell using the write data bus. The semiconductor device according to any one of claims 3 to 5, wherein And a sense amplifier that reads the verified data from the memory cell using the shield wires. The semiconductor device according to any one of claims 1 to 4, wherein And a sense amplifier which reads data from the memory cell using the read data bus. The semiconductor device according to any one of claims 1 to 5, wherein And a cell array including a plurality of banks capable of reading data from memory cells of the second bank while writing data into the memory cells of the first bank. The semiconductor device according to any one of claims 3 to 5, wherein A cell array comprising a plurality of banks capable of reading data from memory cells of a second bank while writing data into memory cells of a first bank; And And a sense amplifier provided in each bank to read data from the memory cell using the read data bus. The semiconductor device according to any one of claims 3 to 5, wherein And a cell array including a plurality of banks capable of reading data from the memory cells of the second bank while writing data into the memory cells of the first bank, wherein the read data bus is provided for each bank. There is a semiconductor device characterized by the above-mentioned. The semiconductor device according to any one of claims 1 to 5, wherein A cell array comprising a plurality of banks capable of reading data from memory cells of a second bank while writing data into memory cells of a first bank; And And a selection circuit for generating a selection signal for selecting the bank. The semiconductor device according to any one of claims 1 to 3, wherein And switching means for connecting said first write amplifier to said read data bus upon predetermined writing. The semiconductor device of claim 3, wherein the semiconductor device comprises: And switching means for connecting the second light amplifier to the shield wiring at a predetermined writing time. The semiconductor device according to any one of claims 1 to 3, wherein A cell array comprising a plurality of banks capable of reading data from memory cells of a second bank while writing data into memory cells of a first bank; And And switching means for selecting a bank connected to the read data bus among the plurality of banks. The semiconductor device according to any one of claims 3 to 5, wherein A cell array comprising a plurality of banks capable of reading data from memory cells of a second bank while writing data into memory cells of a first bank; And And switching means for selecting a bank to be connected to the shield wiring among the plurality of banks at a predetermined writing time. The method according to any one of claims 1 to 3 and 5, And the read data bus comprises more data buses than the write data bus. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is a semiconductor memory device. Writing data into the memory cell using the write data bus; Reading data from the memory cell using a read data bus; And And writing data into the memory cell using the read data bus at a predetermined writing time. The method of claim 20, wherein the data writing method is And writing data to the memory cell using the write data bus at a predetermined write time. The method of claim 20, wherein the data writing method is And writing data into the memory cell using a shield wire for shielding the read data bus at a predetermined write time. Reading data from the memory cell using the read data bus; And And writing data into the memory cell using a shield wire for shielding the read data bus at a predetermined write time. The method according to any one of claims 20 to 23, wherein the data writing method is And reading the verified data from the memory cell using the read data bus. 23. The method of claim 20, wherein the data writing method is And reading the verified data from the memory cell using the write data bus. The method of claim 22 or 23, wherein the data writing method is And reading the verified data from the memory cell using the shield wire. The method according to any one of claims 20 to 23, wherein the data writing method is And generating a selection signal for selecting a plurality of banks each including the memory cells. The method according to any one of claims 20 to 23, wherein the data writing method is And reading data from the memory cells of the second bank while writing the data into the memory cells of the first bank of the plurality of banks.

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