KR102545465B1 - Storage controller and storage device comprising the same - Google Patents

Abstract

A storage controller and a storage device including the same are provided. A storage controller according to some embodiments is a storage controller that writes first data by performing a program on a first memory cell N times (where N is a natural number greater than 1), and includes a first logical address for the first data; A flash conversion layer that performs address mapping using a mapping table storing mapping information between first physical addresses for 1 data, data where the first data is invalid before the Nth program is performed on the first memory cell a write amplification (WAF) manager that checks whether data is invalid, and a central processing unit that does not perform an N-th program for the first memory cell when the first data is invalid data

Description

Storage controller and storage device including the same

The present invention relates to a storage controller and a storage device including the same.

A storage device including a NAND flash memory can be used in a variety of modern systems, from micro-electronic devices to media servers. At this time, in a storage device including a NAND flash, write amplification (WAF) is generated by garbage collection and may cause irregular performance of the storage device.

Also, a host communicating with the storage device may transmit a trim command notifying that data existing in a specific area of the storage device is no longer used, to the storage device. The storage device may receive a trim command and perform a flush operation on corresponding data.

That is, in order to improve the performance of the storage device, there is a need to improve write amplification characteristics and improve flush operation speed.

A technical problem to be solved by the present invention is to provide a storage controller with improved write amplification (WAF) characteristics and improved flush operation speed.

Another technical problem to be solved by the present invention is to provide a storage device including a storage controller with improved write amplification characteristics and improved flush operation speed.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a storage controller according to some embodiments of the present invention is a storage controller that writes first data by performing a program N (where N is a natural number greater than 1) times in a first memory cell, A flash conversion layer that performs address mapping using a mapping table storing mapping information between a first logical address for data and a first physical address for first data, and an N-th program is performed in the first memory cell Before, a Write Amplification (WAF) manager checks whether the first data is invalid data, and if the first data is invalid data, performs an N-th program on the first memory cell. It includes a central processing unit that does not.

In order to achieve the above technical problem, a storage device according to some embodiments of the present invention is a storage device that writes first data by performing a program N times (where N is a natural number greater than 1) in a first memory cell. A non-volatile memory device including a memory cell, and a storage controller configured to write first data to a first memory cell, wherein the storage controller includes a first logical address for the first data and a first logical address for the first data. A flash translation layer that performs address mapping using a mapping table storing mapping information between physical addresses, and checking whether the first data is invalid data before the Nth program is performed on the first memory cell. and a write amplification (WAF) manager that does not perform an N-th program on the first memory cell when the first data is invalid.

In order to achieve the above technical problem, a storage device according to some embodiments of the present invention performs a program N (N is a natural number greater than 1) times on a first block and a second block to store first data in the first block. , and write second data to a second block, a non-volatile memory device including a first block and a second block, and first data to be written to the first block, and second data to the second block 2 A storage controller for recording data, wherein the storage controller checks whether an open memory cell exists in the first block or the second block before performing an Nth program on the first block and the second block. Write including a detector and a memory cell compressor for moving memory cells programmed N-1 times in a first block or a second block to another block when an open memory cell exists in the first block or the second block and compressing the memory cell and a central processing unit that executes an Nth program on a first block and a second block after the memory cell is compressed through an amplification manager and a memory cell compressor.

Details of other embodiments are included in the detailed description and drawings.

1 is a block diagram illustrating a storage system according to some embodiments.
FIG. 2 is an exemplary block diagram illustrating the nonvolatile memory device of FIG. 1 .
FIG. 3 is an exemplary circuit diagram for explaining the blocks of FIG. 2 .
4 are graphs for describing a program operation of a storage device according to some embodiments.
5 is a block diagram illustrating a write amplification manager according to some embodiments.
6 is a flowchart illustrating an operation of the write amplification manager of FIG. 5 according to some embodiments.
7 is a block diagram illustrating another write amplification manager according to some embodiments.
8 is a flowchart illustrating an operation of another write amplification manager of FIG. 7 according to some embodiments.
9 is a block diagram illustrating another write amplification manager according to some embodiments.
10 is a flowchart illustrating an operation of another write amplification manager of FIG. 9 according to some embodiments.
11 to 13 are diagrams for explaining operations of the storage controller according to the exemplary embodiments described above with reference to FIGS. 5 to 10 .
14 is a block diagram illustrating another write amplification manager according to some embodiments.
15 is a flowchart illustrating an operation of another write amplification manager of FIG. 14 according to some embodiments.
16 and 17 are diagrams for explaining operations of the write amplification manager according to some embodiments described with reference to FIGS. 14 and 15 .
18 is an exemplary block diagram illustrating a storage system to which a storage device according to some embodiments is applied.
19 is an exemplary block diagram illustrating a data center to which a storage device according to some embodiments is applied.

1 is a block diagram illustrating a storage system according to some embodiments.

Referring to FIG. 1 , a storage system 10 may include a host 100 and a storage device 200 . Also, the storage device 200 may include a storage controller 210 and a non-volatile memory device 220 . Also, according to an exemplary embodiment of the present invention, the host 100 may include a host controller 110 and a host memory 120 . The host memory 120 may function as a buffer memory for temporarily storing data to be transmitted to the storage device 200 or data transmitted from the storage device 200 .

The storage device 200 may include storage media for storing data according to a request from the host 100 . As an example, the storage device 200 may include a solid state drive (SSD). When the storage device 200 is, for example, an SSD, the storage device 200 may be a device conforming to the non-volatile memory express (NVMe) standard. The host 100 and the storage device 200 may respectively generate and transmit packets according to adopted standard protocols.

When the nonvolatile memory device 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array.

According to an embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 120 may be integrated on the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory included in the application processor, or may be a non-volatile memory or a memory module disposed outside the application processor.

The host controller 110 stores data (eg, write data) in the buffer area of the host memory 120 in the nonvolatile memory device 220 or stores data (eg, read data) in the nonvolatile memory device 220. You can manage the operation of saving to the buffer area.

The storage controller 210 may include a host interface 211 , a memory interface 212 , and a central processing unit (CPU) 213 . In addition, the storage controller 210 includes a flash translation layer (FTL) 214, a write amplification (WAF) manager 215, a buffer memory 216, and an error correction code (ECC) 217. An engine and encryption/decryption (Encryption/Decryption) engine 218 may be further included. The storage controller 210 may further include a working memory (not shown) into which the flash translation layer (FTL) 214 is loaded, and the central processing unit 213 executes the flash translation layer, thereby a non-volatile memory device. Data write and read operations for 220 can be controlled.

The host interface 211 may transmit/receive packets with the host 100 . A packet transmitted from the host 100 to the host interface 211 may include a command or data to be written to the non-volatile memory device 220, and is transmitted from the host interface 211 to the host 100. The packet may include a response to a command or data read from the non-volatile memory device 220 .

A command transmitted from the host 100 to the host interface 211 may be, for example, a write, read, or trim command.

The memory interface 212 may transmit data to be written to the nonvolatile memory device 220 to the nonvolatile memory device 220 or may receive data read from the nonvolatile memory device 220 . Such a memory interface 212 may be implemented to comply with standards such as Toggle or Open NAND Flash Interface (ONFI).

The flash translation layer 214 may perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from the host 100 into a physical address used to actually store data in the nonvolatile memory device 220 .

For example, the flash conversion layer 214 may store a mapping table in which a first logical address for first data and first physical address information mapped thereto are recorded. That is, when performing an address mapping operation on the first data, the flash conversion layer 214 may refer to a mapping table to perform the address mapping operation.

Wear-leveling is a technique for preventing excessive deterioration of a specific block by ensuring that blocks in the non-volatile memory device 220 are uniformly used. For example, firmware balancing erase counts of physical blocks It can be realized through technology. Garbage collection is a technique for securing usable capacity in the nonvolatile memory device 220 by copying valid data of a block to a new block and then erasing the old block.

The ECC engine 217 may perform error detection and correction functions for read data read from the nonvolatile memory device 220 . More specifically, the ECC engine 217 may generate parity bits for write data to be written in the non-volatile memory device 220, and the parity bits generated in this way are used together with the write data in the non-volatile memory. may be stored within device 220 . When data is read from the non-volatile memory device 220, the ECC engine 217 corrects an error in the read data using parity bits read from the non-volatile memory device 220 together with the read data, and the error is corrected. Read data can be output.

The encryption/decryption engine 218 may perform at least one of an encryption operation and a decryption operation on data input to the storage controller 210 .

For example, the encryption/decryption engine 218 may perform an encryption operation and/or a decryption operation using a symmetric-key algorithm. In this case, the encryption/decryption engine 218 may perform an encryption and/or decryption operation using, for example, an Advanced Encryption Standard (AES) algorithm or a Data Encryption Standard (DES) algorithm.

Also, for example, the encryption/decryption engine 218 may perform an encryption operation and/or a decryption operation using a public key encryption algorithm. In this case, the encryption/decryption engine 218 may perform encryption using a public key during an encryption operation, and decryption using a private key during a decryption operation, for example. For example, the encryption/decryption engine 218 may use Rivest Shamir Adleman (RSA), Elliptic Curve Cryptography (ECC), or Diffie-Hellman (DH) encryption algorithms.

Without being limited thereto, the encryption/decryption engine 218 performs an encryption operation and/or a decryption operation using a quantum cryptography technology such as Homomorphic Encryption (HE), Post-Quantum Cryptography (PQC), or Functional Encryption (FE). can do.

The write amplification manager 215 may help improve the performance of the storage device according to some embodiments when a program is performed on a memory cell included in the nonvolatile memory device 220 . For example, the write amplification manager 215 may improve write amplification characteristics of a storage device according to some embodiments. Also, for example, the write amplification manager 215 may improve the speed of a flush operation of a storage device according to some embodiments.

In this regard, first, the structure of the non-volatile memory device 220 will be reviewed through FIG. 2 .

FIG. 2 is an exemplary block diagram illustrating the nonvolatile memory device of FIG. 1 .

Referring to FIG. 2 , the nonvolatile memory device 300 of FIG. 2 may correspond to the nonvolatile memory device 220 of FIG. 1 .

With continued reference to FIG. 2 , the nonvolatile memory device 300 includes a control logic circuit 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. can do. Although not shown in FIG. 2 , the nonvolatile memory device 300 may further include the memory interface circuit 212 shown in FIG. 1 , and may also include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like. may further include.

The control logic circuit 320 may generally control various operations within the nonvolatile memory device 300 . The control logic circuit 320 may output various control signals in response to the command CMD and/or the address ADDR from the memory interface circuit 310 . For example, the control logic circuit 320 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array 330 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. there is. The memory cell array 330 may be connected to the page buffer unit 340 through bit lines BL, and may include word lines WL, string select lines SSL, and ground select lines GSL. It can be connected to the row decoder 360 through

In an exemplary embodiment, the memory cell array 330 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference. are combined In an exemplary embodiment, the memory cell array 330 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings disposed along row and column directions.

The page buffer 340 may include a plurality of page buffers PB1 to PBn (n is an integer greater than or equal to 3), and the plurality of page buffers PB1 to PBn may include a plurality of bit lines BL. Each of the memory cells may be connected. The page buffer 340 may select at least one bit line from among the bit lines BL in response to the column address Y-ADDR. The page buffer 340 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer 340 may apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer 340 may detect data stored in a memory cell by sensing a current or voltage of a selected bit line.

The voltage generator 350 may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 350 may generate a program voltage, a read voltage, a program verify voltage, an erase voltage, and the like as the word line voltage VWL.

The row decoder 360 may select one of the plurality of word lines WL and select one of the plurality of string select lines SSL in response to the row address X-ADDR. For example, during a program operation, the row decoder 360 may apply a program voltage and a program verify voltage to the selected word line, and during a read operation, may apply a read voltage to the selected word line.

Blocks included in the memory cell array 330 will be described with reference to FIG. 3 by taking the first block BLK1 as an example. Of course, the description of the first block BLK1 can also be applied to the other blocks BLK2 to BLKz.

FIG. 3 is an exemplary circuit diagram for explaining the blocks of FIG. 2 .

Referring to FIG. 3 , a 3D V-NAND structure applicable to the nonvolatile memory devices of FIGS. 1 and 2 is shown. When the nonvolatile memory device is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks BLK1 to BLKz of FIG. 2 may be expressed as an equivalent circuit as shown in FIG. 3 .

The memory block BLK1 shown in FIG. 3 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, the plurality of memory NAND strings NS11 to NS33 included in the memory block BLK1 may be formed in a direction perpendicular to the substrate.

3, the memory block BLK1 may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. there is. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1 , MC2 , ..., MC8 , and a ground select transistor GST. 3 shows that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., MC8, but is not necessarily limited thereto.

The string select transistor SST may be connected to corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be connected to corresponding word lines WL1 , WL2 , ..., WL8 , respectively. Some of the word lines WL1 , WL2 , ..., WL8 may correspond to dummy word lines. The ground select transistor GST may be connected to corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines (eg, WL1) having the same height may be commonly connected, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 may be separated from each other. Although the memory block BLK1 is illustrated in FIG. 3 as being connected to eight word lines WL1, WL2, ..., WL8 and three bit lines BL1, BL2, and BL3, it is not necessarily limited thereto. no.

4 are graphs for describing a program operation of a storage device according to some embodiments.

Although this figure has been described as an example of programming 3-bit data, it is not limited thereto, and examples of programming 2-bit data and 1-bit data can be described as a matter of course.

Referring to FIGS. 1 , 3 and 4 , the storage controller 210 may write data to the non-volatile memory device 220 . For example, the storage controller 210 may write first data in the first memory cell MC1 of the nonvolatile memory device 220 . At this time, the storage controller 210 may write the first data in the first memory cell MC1 by performing the program N times (where N is a natural number greater than 1). That is, when writing data to the memory cells of the nonvolatile memory device 220, the storage controller 210 may write the data by performing a multi-program.

In the following description, data is recorded through program execution twice, but the operation of the storage device 200 according to some embodiments is not limited thereto, and data is recorded through program execution N times. Of course, it can also be applied to motion.

The first program operation (1st PGM) may be performed so that each memory cell has a state corresponding to 3-bit data among eight states (E, P11, P12, P13, P14, P15, P16, P17). As shown in FIG. 4 , the eight states E and P11 to P17 may be adjacent to each other without a read margin. That is, during the first program operation (1st PGM), 3-bit data can be roughly programmed.

In an exemplary embodiment, the first program operation (1st PGM) may be performed according to an incremental step pulse programming (ISPP) technique in which a program voltage increases by a predetermined increment when a program loop is repeated.

In an exemplary embodiment, the first program operation (1st PGM) may include a verify operation. During the verification operation, the verification operation may be performed only for at least one program state. For example, in the first program operation (1st PGM), verification operations for program states P12, P14, and P16 are performed, whereas verification operations for program states P11, P13, P15, and P17 are performed. may not be performed. That is, if the program states P12, P14, and P16 pass the verification, the first program operation (1st PGM) may end.

The 2nd program operation (2nd PGM) can be performed to reprogram the rough states (P11 to P17) formed through the 1st program operation (1st PGM) into more detailed states (P21 to P27). there is. Here, states P21 to P27 may be adjacent to each other with a predetermined read margin, as shown in FIG. 4 . That is, in the second program operation (2nd PGM), 3-bit data programmed in the first program operation (1st PGM) can be reprogrammed. As described above, the 3-bit data used in the 2nd program operation (2nd PGM) is the same as that used in the 1st program operation (1st PGM). As shown in FIG. 4 , states P11 of memory cells subjected to a first program operation (1st PGM) may be reprogrammed to a state P21 during a second program operation (2nd PGM). This means that the threshold voltage distribution corresponding to the state P21 of the memory cells in which the second program operation (2nd PGM) was performed is the threshold voltage distribution corresponding to the state P11 of the memory cells in which the first program operation (1st PGM) was performed. It can be made more narrow. In other words, the verification voltage VR21 for verifying the states P21 of the memory cells on which the 2nd program operation (2nd PGM) has been performed determines the states P11 of the memory cells on which the 1st program operation (1st PGM) has been performed. It may be higher than the verification voltage (VR11) for verification.

In an exemplary embodiment, the second program operation (2nd PGM) may be performed according to ISPP technology.

In an exemplary embodiment, the second program operation (2nd PGM) may include a verification operation. A verification operation can be performed for all program states. When all program states P21 to P27 pass the verification, the second program operation (2nd PGM) ends, and data writing can be completed.

At this time, the write amplification manager 215 performs a second program operation on the memory cell to which the first program operation has been performed, and before data writing is completed, the memory cell to which the second program operation is performed has invalid data ( Invalid data), and the second program operation can be performed.

Without being limited thereto, for example, in the case of the storage device 200 in which data is written through N times of programming, the write amplification manager 215 performs the Nth program operation on the memory cell in which the N−1th program operation has been performed. Before data writing is completed by performing , it may be checked whether a memory cell in which the N th program operation is performed is invalid data, and then the N th program operation may be performed.

In addition, the write amplification manager 215 first performs an operation of detecting a block including an open memory cell before completing the writing of data by performing a second program operation on the memory cell for which the first program operation has been performed, and , If a block including an open memory cell is detected, the memory cell on which the first program operation has been performed may be moved to the block including the open memory cell, compression may be performed, and a second program operation may be performed.

Without being limited thereto, for example, in the case of the storage device 200 in which data is written through N times of programming, the write amplification manager 215 performs the Nth program operation on the memory cell in which the N−1th program operation has been performed. Before completing data writing by performing , an operation of detecting a block including an open memory cell is first performed, and if a block including an open memory cell is detected, the block containing the open memory cell is the N-1th block. A memory cell on which a program operation has been performed may be moved to perform compression, and an Nth program operation may be performed.

Through the operation of the write amplification manager 215 , write amplification characteristics of the storage device 200 according to some embodiments may be improved. Also, a flush operation speed of the storage device 200 may be improved.

Hereinafter, the structure and operation of the write amplification manager 215 will be described in detail. Hereinafter, the storage device 200 according to some embodiments will be described as having data written into memory cells through two program executions, but a description of this will be described as a storage device in which data are written into memory cells through N program executions. Of course, it can also be applied to the device 200.

5 is a block diagram illustrating a write amplification manager according to some embodiments.

Hereinafter, a case in which the storage controller 210 writes first data into the first memory cell MC1 through two program executions will be described as an example. Also, it is assumed that one program has already been performed on the first memory cell MC1 and the second and last program execution operation remains in order to write the first data.

Referring to FIGS. 1 , 3 and 5 , the write amplification manager 215 includes a flash translation layer checker 2150 . The flash conversion layer checker 2150 may communicate with the flash conversion layer 214 and check whether the first data is invalid by referring to a mapping table in the flash conversion layer 214 .

For example, as a result of referring to the mapping table in the flash translation layer 214, the flash translation layer checker 2150 determines that the first physical address corresponding to the first logical address for the first data is not mapped. 1 Data can be judged as invalid data.

As another example, as a result of referring to the mapping table in the flash translation layer 214, the flash translation layer checker 2150 determines the first data if a trim command is transmitted from the host 100 for the first data. It can be judged as invalid data.

The storage controller 210, more specifically, the central processing unit 213 of the storage controller 210 receives a result of determining that the first data is invalid from the write amplification manager 215, for the first memory cell. The second program operation is not performed.

Through this, it is possible to prevent unnecessary programming of the word line (eg, the first word line WL1) connected to the first memory cell MC1.

The operation of the storage device 200 including the above-described write amplification manager 215 will be reviewed through a flowchart.

6 is a flowchart illustrating an operation of the write amplification manager of FIG. 5 according to some embodiments.

Referring to FIGS. 1, 3, 5, and 6 , a first program operation is performed to write first data to the first memory cell MC1 (S100).

Thereafter, it is determined whether the first data is invalid data in the flash translation layer 214 through the flash translation layer checker 2150 in the write amplification manager 215 (S110).

If it is determined that the first data is valid data in the flash conversion layer 214 (N), a second program operation is performed on the first memory cell MC1 to write the second data (S220).

Otherwise, if it is determined that the first data is invalid data in the flash conversion layer 214 (Y), the second program operation is not performed on the first memory cell MC1 and the program operation is stopped. do.

7 is a block diagram illustrating another write amplification manager according to some embodiments.

1, 3 and 7, the write amplification manager 215 includes a buffer memory checker 2152. The buffer memory checker 2152 may communicate with the buffer memory 216 to check whether the first data in the buffer memory 216 is invalid.

For example, if it is determined that the first data in the buffer memory 216 is overwritten data, the buffer memory inspector 2152 may determine that the first data is invalid data. For example, a host transmits a write command to first data in the buffer memory 216, and the first data may remain on standby in the buffer memory 216 until it is programmed into the non-volatile memory device. At this time, when the storage controller 210 transmits a write completion command for the first data to the host, and the host recognizing this transmits a write command for the first data again, an overwrite is performed for the first data. may be judged to have been

The storage controller 210, more specifically, the central processing unit 213 of the storage controller 210 receives a result of determining that the first data is invalid from the write amplification manager 215, for the first memory cell. The second program operation is not performed.

Through this, it is possible to prevent unnecessary programming of the word line (eg, the first word line WL1) connected to the first memory cell MC1.

The operation of the storage device 200 including the above-described write amplification manager 215 will be reviewed through a flowchart.

8 is a flowchart illustrating an operation of another write amplification manager of FIG. 7 according to some embodiments.

Referring to FIGS. 1, 3, 7, and 8 , a first program operation is performed to write first data to the first memory cell MC1 (S200).

Thereafter, it is determined whether the first data is invalid data in the buffer memory 216 through the buffer memory checker 2152 in the write amplification manager 215 (S210).

If it is determined that the first data is valid data in the buffer memory 216 (N), a second program operation is performed on the first memory cell MC1 to write the second data (S220).

Otherwise, if it is determined that the first data is invalid data in the buffer memory 216 (Y), the second program operation is not performed on the first memory cell MC1 and the program operation is stopped. .

9 is a block diagram illustrating another write amplification manager according to some embodiments.

Referring to FIG. 9 , the write amplification manager 215 may include both the flash translation layer checker 2150 described with reference to FIGS. 5 and 6 and the buffer memory checker 2152 described with reference to FIGS. 7 and 8 . . That is, the write amplification manager 215 according to some embodiments may determine whether the first data is invalid through parallel operations of the flash translation layer inspector 2150 and the buffer memory inspector 2152. .

An operation of the write amplification manager 215 of FIG. 9 according to some embodiments will be described through a flowchart of FIG. 10 .

10 is a flowchart illustrating an operation of another write amplification manager of FIG. 9 according to some embodiments.

Referring to FIGS. 1, 3, 9, and 10 , a first program operation is performed to write first data to the first memory cell MC1 (S300).

Thereafter, it may be determined whether the first data is invalid data in the buffer memory 216 through the buffer memory checker 2152 (S310). In addition, it is possible to determine whether the first data is invalid data in the flash conversion layer 214 through the flash conversion layer checker 2150 (S320). The operation of the buffer memory checker 2152 and the operation of the flash translation layer checker 2150 may be performed in parallel.

If the first data is determined to be invalid data in the buffer memory 216 through the buffer memory checker 2152 (Y), the second program operation for the first memory cell MC1 is not performed. .

In addition, if the first data is determined to be invalid data in the flash conversion layer 214 through the flash conversion layer checker 2150 (Y), a second program operation for the first memory cell MC1 is performed. does not perform

That is, through the buffer memory inspector 2152, the first data is determined as valid data in the buffer memory 216 (N), and through the flash translation layer inspector 2150, the first data is determined as the flash translation layer 214 ), a second program for the first memory cell MC1 may be performed (N).

Through this, it is possible to prevent unnecessary programming of the word line (eg, the first word line WL1) connected to the first memory cell MC1.

5 to 10, operations of the storage controller 210 according to some of the above-described embodiments will be described with simplified block diagrams.

11 to 13 are diagrams for explaining operations of the storage controller according to the exemplary embodiments described above with reference to FIGS. 5 to 10 .

1, 5, 7, 9, and 11 to 13, a plurality of word lines WL5 to WL8 extending in a first direction and a second direction crossing the first direction Memory cells MC1 to MC12 may be formed at points where the plurality of string selection lines SSL1 to SSL3 intersect.

At this time, it is assumed that the data written in the tenth memory cell MC10 and the eleventh memory cell MC11 are determined to be invalid data through the buffer memory inspector 2152 and/or the flash translation layer inspector 2150. do. At this time, the tenth memory cell MC10 and the eleventh memory cell MC11 are defined as invalid memory cells Invalid mc.

If the storage controller 210 writes data to the memory cells MC1 to MC12 through two programs, all memory cells MC1 to MC12 do not check the validity of the data before performing the second program. If a program is performed for , an unnecessary program operation is performed on the fifth word line WL5 to which the tenth memory cell MC10 and the eleventh memory cell MC11 are connected, as shown in FIG. 12 .

Referring to FIG. 12 as an example, in order to perform two multi-programs on the memory cells MC1 to MC12, the first memory cell MC1 to the sixth memory cell MC6 are sequentially numbered from 0 to 5. The first program can be executed. Thereafter, a second program may be performed in the order of 6 to 8 from the first memory cell MC1 to the third memory cell MC3. Thereafter, the first program may be performed in the order of 9 to 11 from the seventh memory cell MC7 to the ninth memory cell MC9. Thereafter, the second program may be performed in the order of 12 to 14 from the fourth memory cell MC4 to the sixth memory cell MC6. Thereafter, the first program may be performed in the order of 15 to 17 from the tenth memory cell MC10 to the twelfth memory cell MC12. Thereafter, a second program may be performed in the order of 18 to 20 from the seventh memory cell MC7 to the ninth memory cell MC9 . Since the memory cells after the twelfth memory cell MC12 are omitted, the operation of programming in the order of 21 to 23 is not shown in FIG. 12, but after the programming in the order of 21 to 23 is performed, the tenth memory cell A second program may be performed in the order of 24 to 26 from (MC10) to the twelfth memory cell (MC12). That is, the storage controller 210 writes data to the memory cells MC1 to MC12 through two programs, and before performing the second program, data validity is not checked, and all the memory cells MC1 to MC12 If a program is performed for , an unnecessary program operation is performed on the fifth word line WL5 to which the tenth memory cell MC10 and the eleventh memory cell MC11 are connected, as shown in FIG. 12 .

Accordingly, as shown in FIG. 13 , the storage controller 210 writes data to the memory cells MC1 to MC12 through two programs. Prior to performing the second program, the data is written through the write amplification manager 215 If the second program is performed after determining the validity of , as shown in FIG. 13 , an unnecessary program operation is performed on the fifth word line WL5 to which the 10th memory cell MC10 and the 11th memory cell MC11 are connected. may not

14 is a block diagram illustrating another write amplification manager according to some embodiments.

1 and 14 , the write amplification manager 215 of the storage controller 210 according to some embodiments includes an open memory cell detector 2154 and a memory cell compressor 2156.

The write amplification manager 215 may find a block in which an open memory cell exists, through the open memory cell detector 2154, before performing a final program operation for writing data into the memory cell.

For example, the open memory cell detector 2154 may check whether there are open memory cells in the second block before performing a second program to write the first data in the first block. The open memory cell detector 2154 is not limited to the second block and may check whether an open memory cell exists in a third block or the like.

An open memory cell, for example, before performing a second program for writing first data in a first block, among word lines on which the first program is executed, among blocks other than the first block, is never programmed. A location of an unopened memory cell may be defined as an open memory cell.

For example, before performing the second program on the third word line located at a certain height from the string select transistor of the first block, the third' from the string select transistor of the second block has the same height as the third word line. If it is determined that a location of a memory cell that has never been programmed in a word line exists, the location may be defined as an open memory cell.

Thereafter, in order to write the first data in the first block, before the second program is performed, the memory cell where the second program is to be executed is moved to the position of the open memory cell through the memory cell compressor 2156, cells can be compressed.

Through this, word lines unnecessarily programmed in the first block may be removed.

If open memory cells are also present in the first block, memory cells of a block having a smaller number of memory cells to be moved may be moved between the first block and the second block. That is, a memory cell in which a second program is to be executed may be moved to a block having a small number of open memory cells among the first block and the second block.

If an open memory cell exists in the third block, a memory cell to be programmed second in the first block may be moved to an open memory cell in the third block, and the memory cell may be compressed.

The operation for this will be reviewed through the flowchart of FIG. 15 .

15 is a flowchart illustrating an operation of another write amplification manager of FIG. 14 according to some embodiments.

1, 14, and 15, in order to record first data in the first block and second data in the second block, for each of the first block and the second block, a first program This is performed (S400).

Thereafter, in order to record the first data in the first block and the second data in the second block, before performing a second program on each of the first block and the second block, the first block or the second block Whether an open memory cell exists in the block is checked through the open memory cell detector 2154 (S410).

If it is determined that no open memory cell exists in the first block or the second block (N), a second program is performed on each of the first block and the second block (S330).

Otherwise, if it is determined that an open memory cell exists in the first block or the second block (Y), the memory cell where the second program is to be executed is moved to the location where the open memory cell exists, and the memory cell is compressed. It is performed through the cell compressor 2156 (S320).

Thereafter, a second program is performed on the first block and the second block (S330).

The above description with reference to FIGS. 14 and 15 will be described with reference to FIGS. 16 and 17, which are drawings showing simplified blocks.

16 and 17 are diagrams for explaining operations of the write amplification manager according to some embodiments described with reference to FIGS. 14 and 15 .

Referring to FIGS. 1 , 14 , 16 , and 17 , it may be checked whether open memory cells are present in the first block BLK1 and the second block BLK2 . This is for explanation, and it is needless to say that it is possible to check whether an open memory cell is present in any block present in the nonvolatile memory device 220 .

Each of the first block BLK1 and the second block BLK2 includes a fourth word line WL4 to an eighth word line WL8 . Also, each of the first block BLK1 and the second block BLK2 includes a first string selection line SSL1 to a third string selection line SSL3 . That is, the fourth word line WL4 to eighth word lines WL8 and the first string select line SSL1 to third string select line SSL3 are provided in each of the first block BLK1 and the second block BLK2. ) may intersect memory cells (memory cells MC1a to MC15a in the first block BLK1 and memory cells MC1b to MC15b in the second block BLK2).

For example, it is assumed that the memory cells MC1a to MC6a of the first block BLK1 and the memory cells MC1b to MC6b of the second block BLK2 are memory cells whose programming has been completed.

Also, it is assumed that a first program is performed on the memory cells MC7a to MC11a in order to write the first data in the first block BLK1. At this time, it is assumed that the first program is performed on the memory cells MC7b to MC10b to write the second data in the second block BLK2.

That is, among the word lines WL5 and WL6 including the first programmed memory cell in the first block BLK1, the word line including the unprogrammed memory cell, that is, the open memory cell, is the fifth word line. It becomes the memory cell MC12a of (WL5).

The open memory cell detector 2154 detects the memory cell MC12a of the first block BLK1 as an open memory cell and writes second data into the second block BLK2 through the memory cell compressor 2156. , among the word lines WL5 and WL6 on which the second program is to be performed, the memory cell MC10b of the word line WL5 including the unprogrammed memory cell is moved as shown in FIG. 17 to change the memory cell. Compress.

In FIG. 16 , the open memory cell is defined as the memory cell MC12a, but is not limited thereto, and the memory cells MC11b and MC12b of the second block BLK2 are defined as open memory cells, and the first block BLK1 Compression may be performed by moving the memory cells MC10a and MC11a of the second block BLK2 to the positions of the memory cells MC11b and MC12b.

Through this, as shown in FIG. 17 , compression is performed by moving the first programmed memory cell at the location of the memory cell MC10b in the second block BLK2 to the open memory cell location MC12a in the first block BLK1, When the second program is executed, word lines on which the program is unnecessarily executed in the second block BLK2 may be reduced.

Through this, write amplification characteristics and flush speed of the storage device 200 according to some embodiments may be improved.

18 is an exemplary block diagram illustrating a storage system to which a storage device according to some embodiments is applied.

The storage system 1000 of FIG. 18 is basically a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an internet of things (IOT) device. It may be a mobile system. However, the storage system 1000 of FIG. 18 is not necessarily limited to a mobile system, and may be used in a personal computer, a laptop computer, a server, a media player, or a navigation device. It may be an automotive device or the like.

Referring to FIG. 18 , the storage system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and additionally includes an image capturing device. device 1410, user input device 1420, sensor 1430, communication device 1440, display 1450, speaker 1460, power supplying device 1470 and a connecting interface 1480.

The main processor 1100 may control the overall operation of the storage system 1000 and, more specifically, the operation of other components constituting the storage system 1000 . The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor 1100 may include one or more CPU cores 1110 and may further include a controller 1120 for controlling the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. Depending on embodiments, the main processor 1100 may further include an accelerator 1130 that is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. Such an accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and may be physically independent from other components of the main processor 1100. It may be implemented as a separate chip.

The memories 1200a and 1200b may be used as main memory devices of the storage system 1000 and may include volatile memories such as SRAM and/or DRAM, but may include non-volatile memories such as flash memory, PRAM, MRAM, and/or RRAM. may also include The memories 1200a and 1200b may also be implemented in the same package as the main processor 1100 .

The storage devices 1300a and 1300b may function as non-volatile storage devices that store data regardless of whether or not power is supplied, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and non-volatile memories (NVMs) 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. can Non-volatile memory (1320a, 1320b) may include a flash memory of a 2-dimensional (2D) structure or a 3-dimensional (3D) V-NAND (Vertical NAND) structure, but other types of PRAM and / or RRAM, etc. It may also include non-volatile memory.

The storage devices 1300a and 1300b may be included in the storage system 1000 while being physically separated from the main processor 1100 or implemented in the same package as the main processor 1100 . In addition, since the storage devices 1300a and 1300b have a form such as a solid state device (SSD) or a memory card, other components of the storage system 1000 can be provided through an interface such as a connection interface 1480 to be described later. It may be coupled to be detachable with elements. The storage devices 1300a and 1300b may be devices to which standard rules such as UFS (Universal Flash Storage), eMMC (embedded multi-media card), or NVMe (non-volatile memory express) are applied, but are not necessarily limited thereto. It's not.

At least one of the storage devices 1300a and 1300b may be the storage device 200 described above with reference to FIGS. 1 to 17 .

The photographing device 1410 may capture a still image or a video, and may be a camera, a camcorder, and/or a webcam.

The user input device 1420 may receive various types of data input from a user of the storage system 1000, and may use a touch pad, a keypad, a keyboard, a mouse, and/or a touch pad. Alternatively, it may be a microphone or the like.

The sensor 1430 can detect various types of physical quantities that can be obtained from the outside of the storage system 1000 and convert the sensed physical quantities into electrical signals. The sensor 1430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device 1440 may transmit and receive signals with other devices outside the storage system 1000 according to various communication protocols. Such a communication device 1440 may be implemented by including an antenna, a transceiver, and/or a modem (MODEM).

The display 1450 and the speaker 1460 may function as output devices that output visual information and auditory information to the user of the storage system 1000 , respectively.

The power supply device 1470 may appropriately convert power supplied from a battery (not shown) and/or an external power source built into the storage system 1000 and supply it to each component of the storage system 1000 .

The connection interface 1480 may provide a connection between the storage system 1000 and an external device that is connected to the storage system 1000 and can exchange data with the system 1000. The connection interface 1480 is an ATA (ATA) Advanced Technology Attachment), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVMe, IEEE Implemented in various interface methods such as 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded universal flash storage), CF (compact flash) card interface, etc. It can be.

19 is an exemplary block diagram illustrating a data center to which a storage device according to some embodiments is applied.

Referring to FIG. 19 , a data center 3000 is a facility that stores various types of data and provides services, and may also be referred to as a data storage center. The data center 3000 may be a system for operating a search engine and database, and may be a computing system used by companies such as banks or government agencies. The data center 3000 may include application servers 3100_1 to 3100_n and storage servers 3200_1 to 3200_m. The number of application servers 3100_1 to 3100_n and the number of storage servers 3200_1 to 3200_m may be variously selected according to embodiments, and the number of application servers 3100_1 to 3100_n and storage servers 3200_1 to 3200_m 3200_m) may be different from each other.

The application server 3100_1 or the storage server 3200_1 may include at least one of processors 3110 and 3210 and memories 3120 and 3220 . Taking the storage server 3200_1 as an example, the processor 3210_1 may control overall operations of the storage server 3200_1, access the memory 3220, and send instructions and/or data loaded into the memory 3220. can run The memory 3220 includes DDR double data rate synchronous DRAM (SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, and/or non-volatile DIMM (NVMDIMM). ) can be. According to embodiments, the number of processors 3210_1 and the number of memories 3220 included in the storage server 3200_1 may be variously selected. In one embodiment, processor 3210_1 and memory 3220 may provide a processor-memory pair. In one embodiment, the number of processors 3210_1 and memories 3220 may be different from each other. The processor 3210_1 may include a single-core processor or a multi-core processor. The above description of the storage server 3200_1 may be similarly applied to the application server 3100_1. According to embodiments, the application server 3100_1 may not include the storage device 3150. The storage server 3200_1 may include one or more storage devices 3250_1. The number of storage devices 3250_1 included in the storage server 3200_1 may be variously selected according to embodiments.

The application servers 3100_1 to 3100_n and the storage servers 3200_1 to 3200_m may communicate with each other through the network 3300 . The network 3300 may be implemented using Fiber Channel (FC) or Ethernet. At this time, FC is a medium used for relatively high-speed data transmission, and an optical switch providing high performance/high availability may be used. According to the access method of the network 3300, the storage servers 3200_1 to 3200_m may be provided as file storage, block storage, or object storage.

In one embodiment, network 3300 may be a storage-only network, such as a Storage Area Network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to FC Protocol (FCP). As another example, the SAN may be an IP-SAN using a TCP/IP network and implemented according to the iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In another embodiment, network 3300 may be a generic network such as a TCP/IP network. For example, the network 3300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

Hereinafter, the application server 3100_1 and the storage server 3200_1 will be mainly described. The description of the application server 3100_1 may be applied to other application servers 3100_n, and the description of the storage server 3200_1 may also be applied to other storage servers 3200_m.

The application server 3100_1 may store data requested by a user or client to be stored in one of the storage servers 3200_1 to 3200_m through the network 3300 . Also, the application server 3100_1 may acquire data requested by a user or client to read from one of the storage servers 3200_1 to 3200_m through the network 3300 . For example, the application server 3100_1 may be implemented as a web server or a database management system (DBMS).

The application server 3100_1 may access the memory 3120_n or the storage device 3150_n included in another application server 3100_n through the network 3300, or may access the storage servers 3200_1- through the network 3300. The memories 3220_1 to 3220_m or the storage devices 3250_1 to 3250_m included in the 3200_m may be accessed. Accordingly, the application server 3100_1 may perform various operations on data stored in the application servers 3100_1 to 3100_n and/or the storage servers 3200_1 to 3200_m. For example, the application server 3100_1 may execute a command for moving or copying data between the application servers 3100_1 to 3100_n and/or the storage servers 3200_1 to 3200_m. At this time, the data is transferred from the storage devices 3250_1-3250_m of the storage servers 3200_1-3200_m through the memories 3220_1-3220_m of the storage servers 3200_1-3200_m or directly to the application servers 3100_1-3100_n. may be moved to the memories 3120-3120n of Data traveling through the network 3300 may be encrypted data for security or privacy.

Taking the storage server 3200_1 as an example, the interface 3254_1 may provide a physical connection between the processor 3210_1 and the controller 3251_1 and a network interconnect (NIC) 3240_1 and the controller 3251_1. . For example, the interface 3254_1 may be implemented in a Direct Attached Storage (DAS) method that directly connects the storage device 3250_1 with a dedicated cable. Also, for example, the interface 3254_1 may include Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), and Peripheral SATA (PCI). Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), It may be implemented in various interface methods such as UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), and/or CF (compact flash) card interface.

The storage server 3200_1 may further include a switch 3230_1 and a NIC 3240_1. The switch 3230_1 may selectively connect the processor 3210_1 and the storage device 3250_1 or selectively connect the NIC 3240_1 and the storage device 3250_1 under the control of the processor 3210_1.

In one embodiment, the NIC 3240_1 may include a network interface card, a network adapter, and the like. The NIC 3240_1 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, or the like. The NIC 3240_1 may include an internal memory, a digital signal processor (DSP), a host bus interface, and the like, and may be connected to the processor 3210_1 and/or the switch 3230_1 through the host bus interface. The host bus interface may be implemented as one of the examples of the interface 3254_1 described above. In one embodiment, the NIC 3240_1 may be integrated with at least one of the processor 3210_1 , the switch 3230_1 , and the storage device 3250_1 .

In the storage servers 3200_1-3200_m or application servers 3100_1-3100_n, the processor transmits commands to the storage devices 3150_1-3150_n and 3250_1-3250_m or memories 3120_1-3120_n and 3220_1-3220_m to program data. or can lead. In this case, the data may be error-corrected data through an Error Correction Code (ECC) engine. The data is data subjected to data bus inversion (DBI) or data masking (DM) processing, and may include Cyclic Redundancy Code (CRC) information. The data may be encrypted data for security or privacy.

The storage devices 3150_1 to 3150_n and 3250_1 to 3250_m may transmit control signals and command/address signals to the NAND flash memory devices 3252_1 to 3252_m in response to a read command received from the processor. Accordingly, when data is read from the NAND flash memory devices 3252_1 to 3252_m, the RE (Read Enable) signal may be input as a data output control signal and output data to the DQ bus. A Data Strobe (DQS) may be generated using the RE signal. Command and address signals may be latched in the page buffer according to a rising edge or a falling edge of a write enable (WE) signal.

The controller 3251_1 may control overall operations of the storage device 3250_1. In one embodiment, the controller 3251_1 may include static random access memory (SRAM). The controller 3251_1 may write data into the NAND flash 3252_1 in response to a write command, or may read data from the NAND flash 3252_1 in response to a read command. For example, a write command and/or a read command may be received from a processor 3210_1 in a storage server 3200_1, a processor 3210_m in another storage server 3200_m, or a processor 3110_1 or 3110_n in application servers 3100_1 or 3100_n. can be provided. The DRAM 3253_1 may temporarily store (buffer) data to be written to the NAND flash 3252_1 or data read from the NAND flash 3252_1. Also, the DRAM 3253_1 may store meta data. Here, the meta data is user data or data generated by the controller 3251_1 to manage the NAND flash 3252_1. The storage device 3250_1 may include a Secure Element (SE) for security or privacy.

The controller 3251_1 may be the storage controller 210 described above with reference to FIGS. 1 to 17 , and the storage device 3250_1 may be the storage device 200 described above with reference to FIGS. 1 to 17 .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in a variety of different forms, and those skilled in the art in the art to which the present invention belongs A person will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

DESCRIPTION OF SYMBOLS 10: storage system 100: host 110: host controller 120: host memory 200: storage device 210: storage controller 211: host interface 212: memory interface 213: central processing unit 214: flash translation layer 215: write amplification manager 216: buffer memory 217: ECC engine 218: Encryption/decryption engine 220: Non-volatile memory device 2150: Flash translation layer checker 2152: Buffer memory checker 2154: Open memory cell detector 2156: Memory cell compressor

Claims (20)

A storage controller that writes first data by performing a program N (N is a natural number greater than 1) times in a first memory cell,
a flash conversion layer performing address mapping using a mapping table storing mapping information between a first logical address for the first data and a first physical address for the first data;
a write amplification (WAF) manager checking whether the first data is invalid data before an Nth program is performed on the first memory cell; and
a central processing unit not performing an N-th program on the first memory cell when the first data is invalid;
writing second data by performing a program N times in a second memory cell connected to the same word line as the first memory cell;
If the first data is invalid data,
The first memory cell does not perform the Nth program;
The second memory cell writes the second data by performing a program N times. According to claim 1,
Further comprising a buffer memory for storing the first data,
The write amplification manager,
and a buffer memory checker configured to check whether the first data stored in the buffer memory is invalid. According to claim 1,
The write amplification manager,
and a flash translation layer checker configured to communicate with the flash translation layer and check whether the first data in the mapping table is invalid. According to claim 1,
and when the first data is invalid data, the first data is trimmed data. According to claim 1,
Where the first data is invalid data, the first data is not mapped to the mapping table. delete According to claim 1,
A storage controller configured to program a third memory cell connected to the same word line as the first memory cell and the second memory cell N times. A storage device that writes first data by performing a program N (N is a natural number greater than 1) times in a first memory cell,
a non-volatile memory device including the first memory cell; and
a storage controller to write the first data to the first memory cell;
The storage controller,
a flash conversion layer performing address mapping using a mapping table storing mapping information between a first logical address for the first data and a first physical address for the first data;
a write amplification (WAF) manager checking whether the first data is invalid data before an Nth program is performed on the first memory cell; and
a central processing unit not performing an N-th program on the first memory cell when the first data is invalid;
The write amplification manager,
and a flash translation layer checker configured to communicate with the flash translation layer and check whether the first data in the mapping table is invalid. According to claim 8,
The storage controller,
Further comprising a buffer memory for storing the first data,
The write amplification manager,
and a buffer memory checker configured to check whether the first data stored in the buffer memory is invalid. delete According to claim 8,
and when the first data is invalid data, the first data is trimmed data. According to claim 8,
If the first data is invalid data, the first data is not mapped to the mapping table. According to claim 8,
writing second data by performing a program N times in a second memory cell connected to the same word line as the first memory cell;
If the first data is invalid data,
The first memory cell does not perform the Nth program;
The storage device of claim 1 , wherein the second memory cell writes the second data by performing a program N times. According to claim 13,
and performing programming N times on a third memory cell connected to the same word line as the first memory cell and the second memory cell. delete delete delete delete delete delete

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