KR20080088172A - Double data rate nand flash memory device - Google Patents

Double data rate nand flash memory device Download PDF

Info

Publication number
KR20080088172A
KR20080088172A KR1020070030737A KR20070030737A KR20080088172A KR 20080088172 A KR20080088172 A KR 20080088172A KR 1020070030737 A KR1020070030737 A KR 1020070030737A KR 20070030737 A KR20070030737 A KR 20070030737A KR 20080088172 A KR20080088172 A KR 20080088172A
Authority
KR
South Korea
Prior art keywords
control signal
data
input
output
flash memory
Prior art date
Application number
KR1020070030737A
Other languages
Korean (ko)
Inventor
정민중
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070030737A priority Critical patent/KR20080088172A/en
Publication of KR20080088172A publication Critical patent/KR20080088172A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Abstract

The present invention relates to a NAND flash memory device, comprising: a counter for performing address counting at rising and falling edges of an input or output control signal for input or output of data according to an operation selection control signal; ; A first data mux for performing data input / output control at the rising edge of the input control signal or the falling edge of the output control signal and the operation selection control signal and is enabled according to the falling edge or output control signal of the input control signal. And a second data mux to perform data input / output control at the rising edge.

Description

Double data rate nand flash memory device

1A is a timing diagram of a data input operation of a flash memory.

1B is a timing diagram of a data output operation of a flash memory.

2 is a block diagram illustrating a structure for data input and output of a flash memory.

3A is a timing diagram of a data input operation of a DDR NAND flash memory according to an embodiment of the present invention.

3B is a timing diagram of a data output operation of a DDR NAND flash memory according to an embodiment of the present invention.

4 is a block diagram illustrating a structure for data input / output of a DDR flash memory according to an exemplary embodiment of the present invention.

* Brief description of the main parts of the drawings *

400: DDR NAND flash memory 410: IO pad

420: first data mux 430: second data mux

440: counter

The present invention relates to a flash memory device, and more particularly to a double data rate flash memory device capable of supporting the speed of a double data rate (DDR).

A NAND flash memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines extending along rows and a plurality of bit lines extending along columns and a plurality of cell strings respectively corresponding to the bit lines.

Semiconductor devices such as the flash memory device operate according to a periodic clock. At this time, the circuit is manufactured differently according to when the clock is input. The flash memory device operates in a rising edge or a falling edge.

1A is a timing diagram of a data input operation of a flash memory, and FIG. 1B is a timing diagram of a data output operation of a flash memory.

Referring to FIG. 1A, in a data input operation of a flash memory device, data is input through an IO pad at a rising edge of an input control signal WE.

In addition, referring to FIG. 1B, in a data output operation of a flash memory device, data is output through an IO pad at a falling edge of an output control signal RE (Read Enable).

The flash memory for inputting and outputting data as described above includes the following configuration.

2 is a block diagram illustrating a structure for data input and output of a flash memory.

2 is a diagram illustrating only some blocks of a flash memory for data input and output.

Referring to FIG. 2, the flash memory device includes a plurality of IO pads 210, a data mux 220 and a counter 230 for controlling data input and output from the IO pads 210.

The IO pads 210 are connected to externally connected pins in the package configuration of the flash memory device to input and output data, and the data mux 220 is connected to a main cell (not shown) of the flash memory device. A data input / output connection between a redundant data line connected to a line or a redundancy cell (not shown) and the plurality of IO pads 210 is performed.

That is, when the input address is a repair address, data input / output is performed by connecting a redundancy data line and the IO pads 210. If the input address is not a repair address, the main data line and the IO pads 210 are connected.

Meanwhile, the data mux 220 is connected to control signals from pads (not shown) that receive an input control signal WE or an output control signal RE among other pins (not shown) in addition to the IO pads 210. Accordingly, the data input / output direction between the IO pads 210 and the main data line or the redundancy data line is determined. For example, when the input control signal WE is input to the data mux 220, the data mux 220 outputs data input from the IO pads 210 as a main data line or a redundancy data line. When the output control signal RE is input to the data mux 220, the data mux 220 transmits data output from the main data line or the redundancy data line to the IO pads 210.

In addition, the counter 230 counts an address for operation at the rising edge or the falling edge of the input control signal WE or the output control signal RE. A program or read operation of data is performed according to the address counting signal of the counter 230. The program or read operation of data is the same as that of a general flash memory device.

As described above, the flash memory device generally performs data input / output at the falling edge or rising edge of the control signal. However, as data input / output speeds are increasingly required, methods for increasing data input / output speeds have been proposed.

Accordingly, an aspect of the present invention is to provide a double data rate flash memory device capable of providing a higher data input / output speed by providing a double data rate (DDR) function in a flash memory.

A double data rate flash memory device according to an aspect of the present invention for achieving the above technical problem,

A NAND flash memory device, comprising: a counter for performing address counting at rising and falling edges of an input or output control signal for input or output of data according to an operation selection control signal; A first data mux for performing data input / output control at the rising edge of the input control signal or the falling edge of the output control signal and the operation selection control signal and is enabled according to the falling edge or output control signal of the input control signal. And a second data mux to perform data input / output control at the rising edge.

When the operation selection control signal is enabled, the counter may perform address counting at rising and falling edges of the input control signal or the output control signal.

When the operation selection control signal is disabled, the counter may perform address counting at a rising edge or a falling edge of an input control signal or an output control signal.

When the operation selection control signal is disabled, the second data mux is disabled.

The double data rate NAND flash memory device may further include a user selection pad for inputting an operation selection control signal for enabling a double data rate operation.

The first data mux or the second data mux is connected to an IO line connected to IO pads input and output from the outside and to a data line from a memory cell of the double data rate NAND flash memory device to control an input control signal or an output. Selecting and connecting the data input / output direction according to the signal is characterized in that the connection.

The double data rate NAND flash memory device includes a memory cell array including a plurality of memory cells capable of storing data; An X decoder and a Y decoder for selecting a memory cell of the memory cell array according to an address provided by the logic unit; And a page buffer for programming or reading data in memory cells selected by the X decoder and the Y decoder.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3A is a timing diagram of a data input operation of a DDR NAND flash memory according to an embodiment of the present invention, and FIG. 3B is a timing diagram of a data output operation of a DDR NAND flash memory according to an embodiment of the present invention.

Referring to FIG. 3A, a double data rate (DDR) NAND flash memory device according to an exemplary embodiment of the present invention may include a rising edge and a falling edge of an input control signal WE (write enable) and an output control signal RE (read enable). Perform data input and output.

That is, as shown in FIG. 3A, it can be seen that data is input through IO at the falling edge and the rising edge of the input control signal WE.

In addition, referring to FIG. 3B, data is output through the IO at the falling edge and the rising edge of the output control signal RE.

The DDR flash memory device according to the embodiment of the present invention operating as described above with reference to FIGS. 3A and 3B will be described in more detail as follows.

4 is a block diagram illustrating a structure for data input / output of a DDR flash memory according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the implemented DDR flash memory 400 includes a plurality of IO pads 410, a first data mux 420, a second data mux 430, and a counter 440. Include. In this case, the DDR NAND flash memory includes a configuration of a NAND flash memory device including a main memory cell array (not shown), a redundancy memory cell array (not shown), and a page buffer circuit (not shown), such as a general NAND flash memory. 4 is a simplified block diagram of data input / output for explaining an embodiment of the present invention.

The IO pad 410 is a pad connected to pins connected to an external device in the package of the DDR flash memory 400 to input and output data, through which data or programmed data to be programmed is input or output.

The first data mux 420 and the second data mux 420 are connected to the plurality of IO pads 410 through the IO line (a), and also through the data line (b) a memory cell, that is, the main cell (Not shown) or a redundancy cell (not shown). Strictly speaking, it can be said that a page buffer (not shown) operating for data program and reading of the memory cell is connected to an IO controller (not shown).

In addition, the first data mux 420 operates according to the inversion signal WEb and the output control signal RE of the input control signal, and the second data mux 430 inverts the input control signal WE and the output control signal. It operates in accordance with the signal REb.

The first data mux 420 and the second data mux 430 select a general data input / output operation or a DDR data input / output operation according to an operation selection control signal SDA input through a user select pad. .

That is, when the SDA signal is input, the DDR data input / output operation is performed. When the SDA signal is not input, the general data input / output operation is performed. In this case, the general data input / output operation is performed only at the rising edge or the falling edge of the input control signal WE or the output control signal RE, and the DDR data input / output operation performs the data input / output operation at both the rising edge and the falling edge. To do.

Accordingly, when the SDA signal for the DDR data input / output operation is input, the first data mux 420 operates on a falling edge of the input control signal WE, that is, a rising edge of the inversion signal WEb of the input control signal. It operates on the falling edge of the output control signal RE.

In addition, the second data mux 430 operates on the rising edge of the input control signal WE, in contrast to the first data mux 420, or on the rising edge of the output control signal RE, that is, the inverted signal of the output control signal. It operates at the falling edge of (REb).

That is, the first data mux 420 and the second data mux 430 alternately perform an operation of performing data I / O at both the rising edge and the poly edge of the I / O control signal WE or RE.

The counter 440 outputs an address counting signal Address by performing address counting according to the input / output control signal WE or RE inputted according to the SDA signal and its inverted signal WEB or REb. An operation for programming or reading data is performed according to the address counting signal.

Referring to the operation of the DDR flash memory 400 according to an embodiment of the present invention in more detail as follows.

First, when no SDA signal is input, only one of the first data mux 420 or the second data mux 430 operates. According to an embodiment of the present invention, when the SDA signal is not input and is disabled, the first data mux 420 operates and the second data mux 430 is disabled.

The counter 440 outputs an address counting signal at the rising edge of the input control signal WE, and outputs an address counting signal at the falling edge of the output control signal RE.

Data is inputted and outputted through the data line b and the IO line a in accordance with the address counting signal. The operation at this time is the same as the data input / output operation of a general flash memory device.

When the user inputs an SDA signal for executing DDR data input / output to the DDR NAND flash memory 400 according to an exemplary embodiment of the present invention, the counter 440 may determine a rising edge and a falling edge of the input / output control signal WE or RE. Each address is counted to output an address signal.

The data is programmed or read according to the increased address signal, and the data input or output after being programmed or read is input / output to the IO pad 410 through the first data mux 420 and the second data mux 430.

That is, the first data mux 420 processes data at the rising edge of the input control signal WE and the falling edge of the output control signal RE. The second data mux 430 processes data at the falling edge of the input control signal WE and the rising edge of the output control signal RE, which are different phases.

4, the first data mux 420 operates at the rising edge of the inversion signal WEb of the input control signal and the falling edge of the output control signal RE. The second data mux 430 may be operated at the rising edge of the input control signal WE and the falling edge of the inversion signal REb of the output control signal.

By this operation, data may be input and output at the rising edge and the falling edge of the input / output control signal WE or RE in the DDR input / output operation, respectively. Therefore, the speed can be improved over the data input / output operation of the general NAND flash memory.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the double data rate NAND flash memory device according to the present invention operates data input / output operations at both the rising edge and the falling edge of the control signal, thereby enabling high speed data input / output.

Claims (8)

In the NAND flash memory device, A counter for performing address counting on rising and falling edges of an input control signal or an output control signal for input or output of data according to an operation selection control signal; A first data mux for performing data input / output control at the rising edge of the input control signal or the falling edge of the output control signal; A second data mux enabled according to the operation selection control signal and performing data input / output control at a falling edge of the input control signal or a rising edge of the output control signal; Double data rate NAND flash memory device comprising a. The method of claim 1, When the operation selection control signal is enabled, And the counter performs address counting at the rising edge and the falling edge of the input control signal or the output control signal. The method of claim 1, When the operation selection control signal is disabled, And the counter performs address counting at a rising edge or a falling edge of an input control signal or a polling control signal. The method of claim 1, When the operation selection control signal is disabled, And the second data mux is disabled. The method of claim 1, The double data rate NAND flash memory device, And a user selection pad for inputting an operation selection control signal to enable the double data rate operation. The method of claim 1, The first data mux or the second data mux, IO lines connected to IO pads input and output from the outside, And a data input / output direction selected according to an input control signal or an output control signal to be connected to a data line from a memory cell of the double data rate NAND flash memory device. The method of claim 1, The double data rate NAND flash memory device, A memory cell array including a plurality of memory cells capable of storing data; An X decoder and a Y decoder for selecting a memory cell of the memory cell array according to an address provided by the logic unit; And And a page buffer for programming or reading data in memory cells selected by the X decoder and the Y decoder. The method of claim 1, And the first mux operates irrespective of the operation selection signal.
KR1020070030737A 2007-03-29 2007-03-29 Double data rate nand flash memory device KR20080088172A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070030737A KR20080088172A (en) 2007-03-29 2007-03-29 Double data rate nand flash memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070030737A KR20080088172A (en) 2007-03-29 2007-03-29 Double data rate nand flash memory device

Publications (1)

Publication Number Publication Date
KR20080088172A true KR20080088172A (en) 2008-10-02

Family

ID=40150495

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070030737A KR20080088172A (en) 2007-03-29 2007-03-29 Double data rate nand flash memory device

Country Status (1)

Country Link
KR (1) KR20080088172A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8553477B2 (en) 2011-02-28 2013-10-08 Hynix Semiconductor Inc. Data interface circuit, nonvolatile memory device including the same and operating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8553477B2 (en) 2011-02-28 2013-10-08 Hynix Semiconductor Inc. Data interface circuit, nonvolatile memory device including the same and operating method thereof

Similar Documents

Publication Publication Date Title
TWI590250B (en) Apparatuses and methods for configuring i/os of memory for hybrid memory modules
JP5016841B2 (en) Nonvolatile semiconductor memory device
US7808825B2 (en) Non-volatile memory device and method of programming the same
US9373379B2 (en) Active control device and semiconductor device including the same
US10410696B2 (en) Methods and apparatuses for command shifter reduction
JP2008108418A (en) Flash memory device and method of programming multi-pages in the same
US10629248B2 (en) Semiconductor devices configured to store bank addresses and generate bank group addresses
US11133054B2 (en) Semiconductor devices performing for column operation
KR102384962B1 (en) Semiconductor memory device
JP2005317176A (en) Memory device with identification information
JP4582551B2 (en) Semiconductor device and data writing method
JP5010263B2 (en) Nonvolatile semiconductor memory device
JP4889343B2 (en) Semiconductor memory device
CN107093447B (en) Memory device
KR20080088172A (en) Double data rate nand flash memory device
US20100329027A1 (en) Nonvolatile memory device and method of operating the same
US8335895B2 (en) System and device having alternative bit organization
JP2008159168A (en) Semiconductor storage device
KR101155113B1 (en) Non volatile memory device and method of operating the same
KR100898123B1 (en) Apparatus for controlling nand flash memory
CN109545262B (en) Semiconductor memory device and method for controlling the same
KR100903694B1 (en) Semiconductor device and data writing method
KR20090000370A (en) Memory device and erase verifying method of therefor
KR20230036356A (en) Address latch, address control circuit and semiconductor apparatus including the address control circuit
KR100543205B1 (en) Single y-counter circuit for supporting a plurality of devices with various data prefetch schemes

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination